coreboot-gerrit August 2018

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Change in coreboot[master]: [WIP]Documentation: Add basic flashing tutorial for Lenovo
by Felix Held (Code Review) 04 Aug '18

04 Aug '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/27852 ) Change subject: [WIP]Documentation: Add basic flashing tutorial for Lenovo ...................................................................... Patch Set 1: (1 comment) IIRC the reverse current protection diode isn't populated in at least some models; IIRC it's replaced with a 0 ohm resistor https://review.coreboot.org/#/c/27852/1/Documentation/mainboard/lenovo/t420… File Documentation/mainboard/lenovo/t420.md: https://review.coreboot.org/#/c/27852/1/Documentation/mainboard/lenovo/t420… PS1, Line 11: PCIexp-card ExpressCard -- To view, visit https://review.coreboot.org/27852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Gerrit-Change-Number: 27852 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Aug 2018 20:51:25 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP]Documentation: Add basic flashing tutorial for Lenovo
by Arthur Heymans (Code Review) 04 Aug '18

04 Aug '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27852 ) Change subject: [WIP]Documentation: Add basic flashing tutorial for Lenovo ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/27852/1/Documentation/mainboard/lenovo/t430… File Documentation/mainboard/lenovo/t430.md: https://review.coreboot.org/#/c/27852/1/Documentation/mainboard/lenovo/t430… PS1, Line 6: space https://review.coreboot.org/#/c/27852/1/Documentation/mainboard/lenovo/xx30… File Documentation/mainboard/lenovo/xx30_series.md: https://review.coreboot.org/#/c/27852/1/Documentation/mainboard/lenovo/xx30… PS1, Line 38: flash IC. In that case your BIOS region must not exceed 4MiB. Please add that in this case "ROM chip size" should still be 12MiB -- To view, visit https://review.coreboot.org/27852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Gerrit-Change-Number: 27852 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Aug 2018 18:17:51 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: southbridge/intel/bd82x6x/Kconfig: Do not include any IFD by default
by Felix Held (Code Review) 04 Aug '18

04 Aug '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/27218 ) Change subject: southbridge/intel/bd82x6x/Kconfig: Do not include any IFD by default ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/27218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1 Gerrit-Change-Number: 27218 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Aug 2018 17:38:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]drivers/pc80/rtc: Add ACPI support
by Patrick Rudolph (Code Review) 04 Aug '18

04 Aug '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27853 Change subject: [WIP]drivers/pc80/rtc: Add ACPI support ...................................................................... [WIP]drivers/pc80/rtc: Add ACPI support Implement GET and SET ACPI methods that take a string to read and write the CMOS variables defined in cmos.layout. Change-Id: I358fd745ebfcee6727890653c1f0efcdb8e870b2 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/drivers/pc80/rtc/Makefile.inc A src/drivers/pc80/rtc/acpi/rtc.asl M src/drivers/pc80/rtc/mc146818rtc.c M src/include/pc80/mc146818rtc.h M src/southbridge/intel/bd82x6x/acpi/lpc.asl M src/southbridge/intel/bd82x6x/lpc.c 6 files changed, 308 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/27853/1 diff --git a/src/drivers/pc80/rtc/Makefile.inc b/src/drivers/pc80/rtc/Makefile.inc index 998b7e7..fa4319e 100644 --- a/src/drivers/pc80/rtc/Makefile.inc +++ b/src/drivers/pc80/rtc/Makefile.inc @@ -5,6 +5,7 @@ postcar-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c +ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_ssdt.c smm-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c ifeq ($(CONFIG_USE_OPTION_TABLE),y) diff --git a/src/drivers/pc80/rtc/acpi/rtc.asl b/src/drivers/pc80/rtc/acpi/rtc.asl new file mode 100644 index 0000000..37e03ba --- /dev/null +++ b/src/drivers/pc80/rtc/acpi/rtc.asl @@ -0,0 +1,299 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 The Chromium OS Authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (CMOS) +{ + Name (_HID, EISAID("PNP0B00")) + External (KEY, PkgObj) + + OperationRegion (OPR, SystemIO, 0x70, 0x04) + Field (OPR, ByteAcc, NoLock, Preserve) + { + IDX0, 7, + , 1, + DAT0, 8, + IDX1, 7, + , 1, + DAT1, 8, + } + + /* Mutex for byte read / write access */ + Mutex (MTX1, 3) + + /* + * Write byte to CMOS + * @param Arg0 Offset in CMOS (0 - 255) + * @param Arg1 Byte to write to CMOS + */ + Method (WRT, 2, Serialized, 3) + { + If (LLess(Arg1, 0x100)) + { + If (Acquire (^MTX1, 1000)) + { + Return () + } + + If (LGreater (Arg0, 0x7f)) + { + Store (Subtract(Arg0, 0x80), IDX1) + Store (Arg1, DAT1) + } + Else + { + Store (Arg0, IDX0) + Store (Arg1, DAT0) + } + + Release (^MTX1) + } + } + + /* + * Read byte from CMOS at Arg0 + * + * @Return: Returns the byte at given address + */ + Method (RD, 1, Serialized, 3) + { + Store (Zero, Local0) + + If (LLess (Arg0, 0x100)) + { + If (Acquire (^MTX1, 1000)) + { + Return (Zero) + } + + If (LGreater (Arg0, 0x7f)) + { + Store (Subtract(Arg0, 0x80), IDX1) + Store (DAT1, Local0) + } + Else + { + Store (Arg0, IDX0) + Store (DAT0, Local0) + } + + Release (^MTX1) + } + + Return (Local0) + } + + /* Mutex for bit read / write access */ + Mutex (MTX2, 2) + + /* + * Write bit to CMOS + * @param Arg0 Offset in CMOS (0 - 2047) + * @param Arg1 Bit to write to CMOS + */ + Method (WRTB, 2, Serialized, 2) + { + If (LLess(Arg0, 0x800)) + { + If (Acquire (^MTX2, 1000)) + { + Return () + } + + Store (Divide(Arg0, 8), Local0) + Store (RD (Local0), Local1) + CreateBitField (Local1, And(Arg0, 7), BIT) + + If (LGreater(Arg1, 0)) + { + Store (One, BIT) + } + Else + { + Store (Zero, BIT) + } + + WRT (Local0, Local1) + + Release (^MTX2) + } + } + + /* + * Read bit from CMOS + * @param Arg0 Offset in CMOS (0 - 2047) + * @return Ones on error + */ + Method (RDB, 1, Serialized, 2) + { + Store (Zero, Local0) + + If (LLess(Arg0, 0x800)) + { + If (Acquire (^MTX2, 1000)) + { + Return (Ones) + } + + Store (Divide(Arg0, 8), Local0) + Store (RD (Local0), Local1) + CreateBitField (Local1, And(Arg0, 7), BIT) + Store (BIT, Local0) + + Release (^MTX2) + } + + Return (Local0) + } + + /* + * Compare two buffers + * @param Arg0 Buffer + * @param Arg1 Buffer + * @return 1 if buffers match + */ + Method (CMP, 2) + { + If (LNotEqual (SizeOf (Arg1), SizeOf (Arg0))) + { + Return (0x00) + } + Store (0x00, Local0) + While (LLess (Local0, SizeOf (Arg1))) + { + If (LNotEqual (DerefOf (Index (Arg0, Local0)), DerefOf (Index (Arg1, Local0)))) + { + Return (0x00) + } + Increment (Local0) + } + Return (0x01) + } + + /* + * Find the CMOS option in the KEY lookup table and return the Package + * containing it. + * @param Arg0 String of CMOS to find + * @return index of Package in KEY, Ones on error + */ + Method (FIND, 1) + { + Store (Zero, Local0) + Store (ToString(Arg0), Local1) + While (LLess(Local0, SizeOf (KEY))) + { + Store (DerefOf (Index (KEY, Local0)), Local2) + Store (DerefOf (Index (Local2, 0)), Local3) + If (CMP(Local3, Local1)) + { + Return (Local0) + } + Increment (Local0) + } + Return (Ones) + } + + /* Mutex for CMOS option read / write access */ + Mutex (MTX3, 1) + + /* + * Patch Bit Arg1 of Object Arg0 with value Arg2 and return previous value + */ + Method (PATC, 3, Serialized, 1) + { + CreateBitField(Arg0, Arg1, BIT) + Store (BIT, Local0) + Store (Arg2, BIT) + Return (Local0) + } + + /* + * Read value to CMOS + * @param Arg0 String of CMOS to read + * @return Ones on error + */ + Method (SET, 2, Serialized, 1) + { + Store (FIND (Arg0), Local0) + If (LEqual(Local0, Ones)) + { + Return (Ones) + } + // Local0 Package at index Local0 + Store (DerefOf (Index (KEY, Local0)), Local0) + + // Local1 CMOS start bit + Store (DerefOf (Index (Local0, 1)), Local1) + // Local2 CMOS bit length + Store (DerefOf (Index (Local0, 2)), Local2) + // Local3 counter + Store (Zero, Local3) + + If (Acquire (^MTX3, 1000)) + { + Return (Ones) + } + + While (LLess(Local3, Local2)) + { + WRTB (Add(Local1, Local3), PATC(Arg1, Local3, 0)) + Increment (Local3) + } + Release (^MTX3) + + Return (Zero) + } + + /* + * Read value from CMOS + * @param Arg0 String of CMOS to write + * @return Buffer read + */ + Method (GET, 1, Serialized, 1) + { + Store (FIND (Arg0), Local0) + If (LEqual(Local0, Ones)) + { + Return (Ones) + } + // Local0 Package at index Local0 + Store (DerefOf (Index (KEY, Local0)), Local0) + + // Local1 CMOS start bit + Store (DerefOf (Index (Local0, 1)), Local1) + // Local2 CMOS bit length + Store (DerefOf (Index (Local0, 2)), Local2) + // Local3 counter + Store (Zero, Local3) + // Create buffer with length = DIV_ROUND_UP(Local2) + Store (Buffer (Divide (Add (Local2, 7), 8)) {0}, Local4) + + If (Acquire (^MTX3, 1000)) + { + Return (Ones) + } + + While (LLess(Local3, Local2)) + { + PATC (Local4, Local3, RDB (Add(Local1, Local3))) + Increment (Local3) + } + + Release (^MTX3) + + Return (Local4) + } +} diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 34db4c3..1b5d0b7 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -240,7 +240,7 @@ return CB_SUCCESS; } -static enum cb_err locate_cmos_layout(struct region_device *rdev) +enum cb_err locate_cmos_layout(struct region_device *rdev) { uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; struct cbfsf fh; diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 5d7497d..8f75b16 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -5,6 +5,7 @@ #include <arch/io.h> #include <types.h> +#include <cbfs.h> #ifndef RTC_BASE_PORT #define RTC_BASE_PORT 0x70 @@ -256,6 +257,8 @@ #if IS_ENABLED(CONFIG_USE_OPTION_TABLE) void sanitize_cmos(void); +enum cb_err pc80_rtc_ssdt(const char *scope); +enum cb_err locate_cmos_layout(struct region_device *rdev); #else static inline void sanitize_cmos(void) {} #endif /* CONFIG_USE_OPTION_TABLE */ diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl index 5204b29..cf16e4c 100644 --- a/src/southbridge/intel/bd82x6x/acpi/lpc.asl +++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl @@ -67,6 +67,7 @@ #include "irqlinks.asl" #include "acpi/ec.asl" + #include "drivers/pc80/rtc/acpi/rtc.asl" Device (DMAC) // DMA Controller { diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index d9e72b4..c17a3b8 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -893,9 +893,12 @@ { struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); config_t *chip = dev->chip_info; + const char *path = acpi_device_path(dev); intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); intel_acpi_gen_def_acpi_pirq(dev); + if (IS_ENABLED(CONFIG_USE_OPTION_TABLE) && path != NULL) + pc80_rtc_ssdt(path); } static void lpc_final(struct device *dev) -- To view, visit https://review.coreboot.org/27853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I358fd745ebfcee6727890653c1f0efcdb8e870b2 Gerrit-Change-Number: 27853 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: [WIP]Documentation: Add basic flashing tutorial for Lenovo
by Patrick Rudolph (Code Review) 04 Aug '18

04 Aug '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27852 Change subject: [WIP]Documentation: Add basic flashing tutorial for Lenovo ...................................................................... [WIP]Documentation: Add basic flashing tutorial for Lenovo * Basic flashing tutorial for Lenovo devices. Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/flashlayout_xx20.svg A Documentation/mainboard/lenovo/flashlayout_xx30.svg A Documentation/mainboard/lenovo/t420.md A Documentation/mainboard/lenovo/t430.md A Documentation/mainboard/lenovo/xx20_series.md A Documentation/mainboard/lenovo/xx30_series.md 7 files changed, 267 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/27852/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 5d41cec..425ee89 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -14,6 +14,18 @@ - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md) +## Lenovo + +### Sandy Bridge Series + +- [T420](lenovo/t420.md) +- [T420 / T520 / X220 / T420s / W520 common](lenovo/xx20_series.md) + +### Ivy Bridge Series + +- [T430](lenovo/t430.md) +- [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md) + ## SiFive - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md) diff --git a/Documentation/mainboard/lenovo/flashlayout_xx20.svg b/Documentation/mainboard/lenovo/flashlayout_xx20.svg new file mode 100644 index 0000000..8884ac3 --- /dev/null +++ b/Documentation/mainboard/lenovo/flashlayout_xx20.svg @@ -0,0 +1,52 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="10cm" height="8cm" viewBox="265 -156 186 159" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="307.888" y="-152.131" width="49.1438" height="30.4667"/> + <rect style="fill: none; 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fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 380.877 -151.013 C 401.876,-151.013 379.377,-73.513 400.627,-72.513"/> + <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 381.377 -0.763268 C 395.238,-0.763268 387.016,-72.763 400.877,-72.763"/> + <text font-size="10.1598" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="406.127" y="-68.513"> + <tspan x="406.127" y="-68.513">Flash #0</tspan> + </text> + <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 381.223 -0.537117 C 402.222,-0.537117 379.285,28.8102 399.872,27.8376"/> + <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 382.176 54.9128 C 396.037,54.9128 385.445,27.9997 399.548,27.8376"/> + <text font-size="10.1598" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="407.157" y="30.2529"> + <tspan x="407.157" y="30.2529">Flash #1</tspan> + </text> + <text font-size="6.77333" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="266.591" y="54.9733"> + <tspan x="266.591" y="54.9733">0xc00000</tspan> + </text> + <line style="fill: none; fill-opacity:0; stroke-width: 2; stroke-dasharray: 4; stroke: #000000" x1="305.271" y1="-1.2113" x2="378.831" y2="-1.17038"/> +</svg> diff --git a/Documentation/mainboard/lenovo/t420.md b/Documentation/mainboard/lenovo/t420.md new file mode 100644 index 0000000..c5e4525 --- /dev/null +++ b/Documentation/mainboard/lenovo/t420.md @@ -0,0 +1,22 @@ +# Lenovo T420 + +## Flashing instructions +You have to disassemble the whole device, as the flash IC is on the bottom +of the mainboard. + +For more details have a look at [T420 / T520 / X220 / T420s / W520 common]. + +### Steps to access the flash IC: +* Unplug the battery +* Remove harddisk, CDROM, PCIexp-card, SIM-card, SDcard, SmartCard, ... +* Open the bottom flap and remove the keyboard screw +* Remove the keyboard +* Remove the screen +* Remove the top enclosure +* Remove the speakers +* Remove WWAN and WIFI card +* Remove the CPU fan +* Unplug the power cable +* Remove the bottom enclosure + +[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md diff --git a/Documentation/mainboard/lenovo/t430.md b/Documentation/mainboard/lenovo/t430.md new file mode 100644 index 0000000..195d74a --- /dev/null +++ b/Documentation/mainboard/lenovo/t430.md @@ -0,0 +1,18 @@ +# Lenovo T420 + +## Flashing instructions +* You have to disassemble the whole device, as the flash IC is on the bottom +of the mainboard. + +### Steps to access the flash IC: +* Unplug the battery +* Remove harddisk, CDROM, PCIexp-card, SIM-card, SDcard, SmartCard, ... +* Open the bottom flap and remove the keyboard screw +* Remove the keyboard +* Remove the screen +* Remove the top enclosure +* Remove the speakers +* Remove WWAN and WIFI card +* Remove the CPU fan +* Unplug the power cable +* Remove the bottom enclosure diff --git a/Documentation/mainboard/lenovo/xx20_series.md b/Documentation/mainboard/lenovo/xx20_series.md new file mode 100644 index 0000000..45b0bff --- /dev/null +++ b/Documentation/mainboard/lenovo/xx20_series.md @@ -0,0 +1,44 @@ +# Lenovo Sandy Bridge series + +## Flashing coreboot +```eval_rst ++---------------------+--------------------+ +| Type | Value | ++=====================+====================+ +| Socketed flash | no | ++---------------------+--------------------+ +| Model | MACRONIX MX25L6436 | ++---------------------+--------------------+ +| Size | 8 MiB | ++---------------------+--------------------+ +| In circuit flashing | Yes | ++---------------------+--------------------+ +| Package | SOIC-8 | ++---------------------+--------------------+ +| Write protection | No | ++---------------------+--------------------+ +| Dual BIOS feature | No | ++---------------------+--------------------+ +| Internal flashing | Yes | ++---------------------+--------------------+ +``` + +## Flashing instructions +* It's safe to use the SPI flasher power, as all devices have a protection + diode near the flash IC. +* Do **NOT** accidently swap pins or power on the board while a SPI flasher + is connected. It will permanently brick your device. +* It's recommended to only flash the BIOS region. In that case you don't + need to extract BLOBs from vendor firmware. + If you want to flash the whole chip, you need BLOBs when building + coreboot. +* The *Flash layout* shows that by default 3MiB of space are available for + the use with coreboot. + +Please also have a look at *TODO* [General Flashrom Usage]. + +## Flash layout +![][fl] + +[fl]: flashlayout_xx20.svg + diff --git a/Documentation/mainboard/lenovo/xx30_series.md b/Documentation/mainboard/lenovo/xx30_series.md new file mode 100644 index 0000000..c896d95 --- /dev/null +++ b/Documentation/mainboard/lenovo/xx30_series.md @@ -0,0 +1,58 @@ +# Lenovo Sandy Bridge series + +## Flashing coreboot +```eval_rst ++---------------------+--------------------+ +| Type | Value | ++=====================+====================+ +| Socketed flash | no | ++---------------------+--------------------+ +| Model | MACRONIX MX25L6436 | ++---------------------+--------------------+ +| Size | 8 MiB + 4MiB | ++---------------------+--------------------+ +| In circuit flashing | Yes | ++---------------------+--------------------+ +| Package | SOIC-8 | ++---------------------+--------------------+ +| Write protection | No | ++---------------------+--------------------+ +| Dual BIOS feature | No | ++---------------------+--------------------+ +| Internal flashing | Yes | ++---------------------+--------------------+ +``` + +## Flashing instructions +* It's safe to use the SPI flasher power, as all devices have a protection + diode near the flash IC. +* Do **NOT** accidently swap pins or power on the board while a SPI flasher + is connected. It will permanently brick your device. +* It's recommended to only flash the BIOS region. In that case you don't + need to extract BLOBs from vendor firmware. + If you want to flash the whole chip, you need BLOBs when building + coreboot. +* The *Flash layout* shows that by default 7MiB of space are available for + the use with coreboot. +* If you don't want to touch IFD, ME, GBE you must only flash the 4MiB + flash IC. In that case your BIOS region must not exceed 4MiB. + +Please also have a look at *TODO* [General Flashrom Usage]. + +## Splitting the coreboot.rom + +To split the coreboot.rom into two images (one for the 8MiB and one for the +4 MiB flash IC), run the following commands: + + dd of=top.rom bs=1M if=build/coreboot.rom skip=8 + dd of=bottom.rom bs=1M if=build/coreboot.rom count=8 + +That give two ROMs for each flash IC. + +## Flash layout +The two flash ICs appear as a 12MiB when flashing internaly. + +![][fl] + +[fl]: flashlayout_xx30.svg + -- To view, visit https://review.coreboot.org/27852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Gerrit-Change-Number: 27852 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: southbridge/intel/bd82x6x/Kconfig: Do not include any IFD by default
by Angel Pons (Code Review) 04 Aug '18

04 Aug '18

Hello Patrick Rudolph, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27218 to look at the new patch set (#2). Change subject: southbridge/intel/bd82x6x/Kconfig: Do not include any IFD by default ...................................................................... southbridge/intel/bd82x6x/Kconfig: Do not include any IFD by default Since only a handful of boards have descriptor blobs in the tree, it makes no sense to have `HAVE_IFD_BIN` enabled by default then disabled on each mainboard. This patch flips the default value of said variable, rendering all current overrides unnecessary. The few boards which have an IFD in the blobs repo use `select HAVE_IFD_BIN` to enable adding the IFD by default. Since `HAVE_ME_BIN` depends on `HAVE_IFD_BIN`, the former has been removed alongside the latter, and has been added to the boards with a ME blob as `select HAVE_ME_BIN`. Both `HAVE_IFD_BIN` and `HAVE_ME_BIN` have been removed from autoport as well. Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/apple/macbookair4_2/Kconfig M src/mainboard/asrock/b75pro3-m/Kconfig M src/mainboard/asus/maximus_iv_gene-z/Kconfig M src/mainboard/asus/p8h61-m_lx/Kconfig M src/mainboard/asus/p8h61-m_pro/Kconfig M src/mainboard/compulab/intense_pc/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-b75m-d3v/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/google/butterfly/Kconfig M src/mainboard/google/link/Kconfig M src/mainboard/google/parrot/Kconfig M src/mainboard/google/stout/Kconfig M src/mainboard/hp/2570p/Kconfig M src/mainboard/hp/2760p/Kconfig M src/mainboard/hp/8460p/Kconfig M src/mainboard/hp/8470p/Kconfig M src/mainboard/hp/8770w/Kconfig M src/mainboard/hp/compaq_8200_elite_sff/Kconfig M src/mainboard/hp/folio_9470m/Kconfig M src/mainboard/hp/revolve_810_g1/Kconfig M src/mainboard/intel/dcp847ske/Kconfig M src/mainboard/intel/emeraldlake2/Kconfig M src/mainboard/kontron/ktqm77/Kconfig M src/mainboard/lenovo/l520/Kconfig M src/mainboard/lenovo/s230u/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/mainboard/roda/rv11/Kconfig M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/stumpy/Kconfig M src/mainboard/sapphire/pureplatinumh61/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M util/autoport/sandybridge.go 42 files changed, 14 insertions(+), 262 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/27218/2 -- To view, visit https://review.coreboot.org/27218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1 Gerrit-Change-Number: 27218 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: nb/amd/pi/00730F01: Add initial native IVRS support
by build bot (Jenkins) (Code Review) 04 Aug '18

04 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/15164 ) Change subject: nb/amd/pi/00730F01: Add initial native IVRS support ...................................................................... Patch Set 23: (9 comments) https://review.coreboot.org/#/c/15164/23/src/northbridge/amd/pi/00730F01/no… File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/#/c/15164/23/src/northbridge/amd/pi/00730F01/no… PS23, Line 488: unsigned int depth, int linknum, int8_t *root_level, line over 80 characters https://review.coreboot.org/#/c/15164/23/src/northbridge/amd/pi/00730F01/no… PS23, Line 511: add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x97); line over 80 characters https://review.coreboot.org/#/c/15164/23/src/northbridge/amd/pi/00730F01/no… PS23, Line 517: add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x0); line over 80 characters https://review.coreboot.org/#/c/15164/23/src/northbridge/amd/pi/00730F01/no… PS23, Line 521: is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); line over 80 characters https://review.coreboot.org/#/c/15164/23/src/northbridge/amd/pi/00730F01/no… PS23, Line 526: add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x0); line over 80 characters https://review.coreboot.org/#/c/15164/23/src/northbridge/amd/pi/00730F01/no… PS23, Line 527: } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && line over 80 characters https://review.coreboot.org/#/c/15164/23/src/northbridge/amd/pi/00730F01/no… PS23, Line 529: add_ivhd_dev_entry(parent, dev, current, length, 0x42, 0x0); line over 80 characters https://review.coreboot.org/#/c/15164/23/src/northbridge/amd/pi/00730F01/no… PS23, Line 589: printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); line over 80 characters https://review.coreboot.org/#/c/15164/23/src/northbridge/amd/pi/00730F01/no… PS23, Line 590: printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); line over 80 characters -- To view, visit https://review.coreboot.org/15164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 Gerrit-Change-Number: 15164 Gerrit-PatchSet: 23 Gerrit-Owner: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Sat, 04 Aug 2018 00:14:10 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: security/tpm: Improve TCPA log generation
by Philipp Deppenwiese (Code Review) 04 Aug '18

04 Aug '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/27769 ) Change subject: security/tpm: Improve TCPA log generation ...................................................................... security/tpm: Improve TCPA log generation * Make tcpa_log_init static and move init code into the tcpa_log_add_table_entry routine. * Add more checks for log initialization. * Fix minor issues Change-Id: I215d79eed7ad17c6ab87f0c4b14a282e519ef07d Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-on: https://review.coreboot.org/27769 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/include/commonlib/tcpa_log_serialized.h M src/drivers/tpm/tpm.c M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/vboot/secdata_tpm.c 5 files changed, 26 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/tcpa_log_serialized.h b/src/commonlib/include/commonlib/tcpa_log_serialized.h index cd6fbec..6dfb566 100644 --- a/src/commonlib/include/commonlib/tcpa_log_serialized.h +++ b/src/commonlib/include/commonlib/tcpa_log_serialized.h @@ -29,7 +29,7 @@ uint32_t pcr; uint8_t digest[TCPA_DIGEST_MAX_LENGTH]; uint32_t digest_length; - uint8_t name[TCPA_PCR_HASH_NAME]; + char name[TCPA_PCR_HASH_NAME]; } __packed; struct tcpa_table { diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c index 8c68159..e4a81c3 100644 --- a/src/drivers/tpm/tpm.c +++ b/src/drivers/tpm/tpm.c @@ -30,9 +30,6 @@ #else tpm_setup(false); #endif - - // TCPA cbmem log - tcpa_log_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, init_tpm_dev, NULL); diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 94b53b0..e4ddefc 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -21,11 +21,6 @@ #include <commonlib/tcpa_log_serialized.h> /** - * Setup TCPA cbmem log. - */ -void tcpa_log_init(void); - -/** * Add table entry for cbmem TCPA log. */ void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 8ec4c6d..0a6655a 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -18,47 +18,45 @@ #include <console/console.h> #include <security/tpm/tspi.h> -void tcpa_log_init(void) +static struct tcpa_table *tcpa_log_init(void) { - const struct cbmem_entry *ce; - struct tcpa_table *tclt; + MAYBE_STATIC struct tcpa_table *tclt = NULL; if (!cbmem_possibly_online()) - return; + return NULL; - ce = cbmem_entry_find(CBMEM_ID_TCPA_LOG); - if (ce) - return; + if (tclt != NULL) + return tclt; + + tclt = (struct tcpa_table *) cbmem_entry_find(CBMEM_ID_TCPA_LOG); + if (tclt) + return tclt; tclt = cbmem_add(CBMEM_ID_TCPA_LOG, sizeof(struct tcpa_table) + - MAX_TCPA_LOG_ENTRIES * - sizeof(struct tcpa_entry)); + MAX_TCPA_LOG_ENTRIES * + sizeof(struct tcpa_entry)); - if (!tclt) - return; + if (!tclt) { + printk(BIOS_ERR, "ERROR: Could not create TCPA log table\n"); + return NULL; + } tclt->max_entries = MAX_TCPA_LOG_ENTRIES; tclt->num_entries = 0; printk(BIOS_DEBUG, "TCPA log created at %p\n", tclt); + + return tclt; } void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, const uint8_t *digest, const size_t digest_length) { - MAYBE_STATIC struct tcpa_table *tclt = NULL; + struct tcpa_table *tclt; struct tcpa_entry *tce; - if (!cbmem_possibly_online()) - return; - - tclt = cbmem_find(CBMEM_ID_TCPA_LOG); - if (!tclt) { - printk(BIOS_ERR, "ERROR: No TCPA log table found\n"); - return; - } - + tclt = tcpa_log_init(); if (tclt->num_entries == tclt->max_entries) { printk(BIOS_WARNING, "ERROR: TCPA log table is full\n"); return; @@ -66,8 +64,13 @@ tce = &tclt->entries[tclt->num_entries++]; - memcpy(tce->name, name, TCPA_PCR_HASH_NAME); + strncpy(tce->name, name, TCPA_PCR_HASH_NAME - 1); tce->pcr = pcr; + + if (digest_length > TCPA_DIGEST_MAX_LENGTH) { + printk(BIOS_WARNING, "ERROR: PCR digest too long for TCPA log entry\n"); + return; + } memcpy(tce->digest, digest, digest_length); tce->digest_length = digest_length; } diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index d3f4a11..c62f18b 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -451,9 +451,6 @@ if (result == TPM_E_MUST_REBOOT) ctx->flags |= VB2_CONTEXT_SECDATA_WANTS_REBOOT; - // TCPA cbmem log - tcpa_log_init(); - return result; } -- To view, visit https://review.coreboot.org/27769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I215d79eed7ad17c6ab87f0c4b14a282e519ef07d Gerrit-Change-Number: 27769 Gerrit-PatchSet: 9 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/octopus: Fix LPDDR4 nWR setting
by Ravishankar Sarawadi (Code Review) 04 Aug '18

04 Aug '18

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/27851 Change subject: mb/google/octopus: Fix LPDDR4 nWR setting ...................................................................... mb/google/octopus: Fix LPDDR4 nWR setting Update nWR setting for LPDDR4 from default to 24 cycles as per spec. BUG=b:112062440 TEST=Run memory stability test using Memtester. Change-Id: I949d30ca9d5bb8fd876fe3c6cac7a719e771e839 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/mainboard/google/octopus/variants/baseboard/memory.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/27851/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c index 452d3a9..6e0fe47 100644 --- a/src/mainboard/google/octopus/variants/baseboard/memory.c +++ b/src/mainboard/google/octopus/variants/baseboard/memory.c @@ -76,6 +76,7 @@ .ch0_dual_rank = 1, .ch1_dual_rank = 1, .part_num = "K4F6E304HB-MGCJ", + .enable_nWR_24 = 1, }, /* K4F8E304HB-MGCJ - both logical channels */ [1] = { @@ -83,6 +84,7 @@ .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "K4F8E304HB-MGCJ", + .enable_nWR_24 = 1, }, /* * MT53B512M32D2NP-062WT:C - both logical channels. While the parts @@ -97,6 +99,7 @@ .ch1_dual_rank = 1, .part_num = "MT53B512M32D2NP", .disable_periodic_retraining = 1, + .enable_nWR_24 = 1, }, /* MT53B256M32D1NP-062 WT:C - both logical channels */ [3] = { @@ -105,6 +108,7 @@ .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "MT53B256M32D1NP", .disable_periodic_retraining = 1, + .enable_nWR_24 = 1, }, /* * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts @@ -118,6 +122,7 @@ .ch0_dual_rank = 1, .ch1_dual_rank = 1, .part_num = "H9HCNNNBPUMLHR", + .enable_nWR_24 = 1, }, /* H9HCNNN8KUMLHR-NLE - both logical channels */ [5] = { @@ -125,6 +130,7 @@ .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "H9HCNNN8KUMLHR", + .enable_nWR_24 = 1, }, /* K4F6E3S4HM-MGCJ - both logical channels */ [6] = { @@ -132,6 +138,7 @@ .ch0_rank_density = LP4_16Gb_DENSITY, .ch1_rank_density = LP4_16Gb_DENSITY, .part_num = "K4F6E3S4HM-MGCJ", + .enable_nWR_24 = 1, }, /* MT53E512M32D2NP-046 - both logical channels */ [7] = { @@ -139,6 +146,7 @@ .ch0_rank_density = LP4_16Gb_DENSITY, .ch1_rank_density = LP4_16Gb_DENSITY, .part_num = "MT53E512M32D2NP", + .enable_nWR_24 = 1, }, }; -- To view, visit https://review.coreboot.org/27851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I949d30ca9d5bb8fd876fe3c6cac7a719e771e839 Gerrit-Change-Number: 27851 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Add support for LPDDR4 nWR setting
by Ravishankar Sarawadi (Code Review) 04 Aug '18

04 Aug '18

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/27850 Change subject: soc/intel/apollolake: Add support for LPDDR4 nWR setting ...................................................................... soc/intel/apollolake: Add support for LPDDR4 nWR setting nWR (Write-Recovery for AutoPre-charge commands), the programmed value of nWR is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of an internal Pre-charge operation after a Write burst with AP (auto-pre-charge) enabled. BUG=b:112062440 TEST= build test Change-Id: I1147538f72f4e2f14e32f3657c05f1f505a56fbf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/soc/intel/apollolake/include/soc/meminit.h M src/soc/intel/apollolake/meminit.c 2 files changed, 19 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27850/1 diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index 27b6556..adea59a 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -81,6 +81,7 @@ enum { ODT_A_B_HIGH_LOW = 0 << 1, ODT_A_B_HIGH_HIGH = 1 << 1, + nWR = 1 << 5, }; /* Provide bit swizzling per DQS and byte swapping within a channel. */ @@ -116,6 +117,7 @@ int ch1_dual_rank; const char *part_num; bool disable_periodic_retraining; + bool enable_nWR_24; }; struct lpddr4_cfg { diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index b0a5f4a..8690040 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -119,13 +119,6 @@ cfg->Ch1_Option = 0x3; cfg->Ch2_Option = 0x3; cfg->Ch3_Option = 0x3; - - /* Set CA ODT with default setting of ODT pins of LPDDR4 modules pulled - up to 1.1V. */ - cfg->Ch0_OdtConfig = ODT_A_B_HIGH_HIGH; - cfg->Ch1_OdtConfig = ODT_A_B_HIGH_HIGH; - cfg->Ch2_OdtConfig = ODT_A_B_HIGH_HIGH; - cfg->Ch3_OdtConfig = ODT_A_B_HIGH_HIGH; } struct speed_mapping { @@ -326,6 +319,7 @@ const struct lpddr4_cfg *lpcfg, size_t sku_id) { const struct lpddr4_sku *sku; + u8 odt_config; if (sku_id >= lpcfg->num_skus) { printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n", @@ -358,6 +352,22 @@ } cfg->PeriodicRetrainingDisable = sku->disable_periodic_retraining; + + + /* + * Set CA ODT with default setting of ODT pins of LPDDR4 modules pulled + * up to 1.1V. + * Set bit 5 in Ch0_OdtConfig to enable nWR24. + */ + if (sku->enable_nWR_24 == 1) + odt_config = ODT_A_B_HIGH_HIGH | nWR; + else + odt_config = ODT_A_B_HIGH_HIGH; + + cfg->Ch0_OdtConfig = odt_config; + cfg->Ch1_OdtConfig = odt_config; + cfg->Ch2_OdtConfig = odt_config; + cfg->Ch3_OdtConfig = odt_config; } uint8_t fsp_memory_soc_version(void) -- To view, visit https://review.coreboot.org/27850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1147538f72f4e2f14e32f3657c05f1f505a56fbf Gerrit-Change-Number: 27850 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>

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coreboot-gerrit August 2018