coreboot-gerrit August 2018

coreboot-gerrit@coreboot.org
  • 1 participants
  • 1120 discussions

Change in coreboot[master]: riscv: update the definition of intptr_t/uintptr_t
by Xiang Wang (Code Review)
3 years, 1 month

Change in coreboot[master]: riscv: update the definition of intptr_t/uintptr_t
by Xiang Wang (Code Review)
3 years, 1 month

Change in coreboot[master]: riscv: update the definition of intptr_t/uintptr_t
by Xiang Wang (Code Review)
3 years, 1 month

Change in coreboot[master]: riscv: update the definition of intptr_t/uintptr_t
by Xiang Wang (Code Review)
3 years, 1 month

Change in coreboot[master]: southbridge/intel: Remove leftover TPM ACPI code
by Philipp Deppenwiese (Code Review)
3 years, 1 month

Change in coreboot[master]: soc/intel/cannonlake: Report Whiskey Lake info
by Furquan Shaikh (Code Review)
3 years, 1 month

Change in coreboot[master]: soc/intel/cannonlake: Report Whiskey Lake info
by Lijian Zhao (Code Review)
3 years, 1 month

Change in coreboot[master]: soc/intel/cannonlake: Report Whiskey Lake info
by Lijian Zhao (Code Review)
3 years, 1 month

Change in coreboot[master]: soc/intel/cannonlake: Update UPD from device switch
by Lijian Zhao (Code Review)
3 years, 1 month

Change in coreboot[master]: google/banon: Add support for additional RAM types/configs
by Matt DeVillier (Code Review)
3 years, 1 month
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