coreboot-gerrit August 2018

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Change in coreboot[master]: riscv: update the definition of intptr_t/uintptr_t
by Xiang Wang (Code Review) 31 Jul '18

31 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27768 to look at the new patch set (#4). Change subject: riscv: update the definition of intptr_t/uintptr_t ...................................................................... riscv: update the definition of intptr_t/uintptr_t These RISC-V ABIs defined by GCC : ilp32 ilp32d ilp32f lp64 lp64d lp64f. Through this we know that the length of the long bit is equal to pointer. So update this code. This's more flexible. Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/include/stdint.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27768/4 -- To view, visit https://review.coreboot.org/27768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b Gerrit-Change-Number: 27768 Gerrit-PatchSet: 4 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: update the definition of intptr_t/uintptr_t
by Xiang Wang (Code Review) 31 Jul '18

31 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27768 to look at the new patch set (#3). Change subject: riscv: update the definition of intptr_t/uintptr_t ...................................................................... riscv: update the definition of intptr_t/uintptr_t These RISC-V ABIs defined by GCC : ilp32 ilp32d ilp32f lp64 lp64d lp64f. Through this we know that the length of the long bit is equal to point. So update this code. This's more flexible. Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/include/stdint.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27768/3 -- To view, visit https://review.coreboot.org/27768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b Gerrit-Change-Number: 27768 Gerrit-PatchSet: 3 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: update the definition of intptr_t/uintptr_t
by Xiang Wang (Code Review) 31 Jul '18

31 Jul '18

Xiang Wang has uploaded a new patch set (#2). ( https://review.coreboot.org/27768 ) Change subject: riscv: update the definition of intptr_t/uintptr_t ...................................................................... riscv: update the definition of intptr_t/uintptr_t This abi of RISC-V is defined by gcc : ilp32 ilp32d ilp32f lp64 lp64d lp64f. Through this we know that the length of the long bit is equal to point. So update this code. This's more flexible. Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/include/stdint.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27768/2 -- To view, visit https://review.coreboot.org/27768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b Gerrit-Change-Number: 27768 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: riscv: update the definition of intptr_t/uintptr_t
by Xiang Wang (Code Review) 31 Jul '18

31 Jul '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27768 Change subject: riscv: update the definition of intptr_t/uintptr_t ...................................................................... riscv: update the definition of intptr_t/uintptr_t This abi of RISC-V is defined by gcc:ilp32 ilp32d ilp32f lp64 lp64d lp64f. Through this we know that the length of the long bit is equal to point. So update this code. This's more flexible. Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/include/stdint.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27768/1 diff --git a/src/arch/riscv/include/stdint.h b/src/arch/riscv/include/stdint.h index 1980866..76f0d1b 100644 --- a/src/arch/riscv/include/stdint.h +++ b/src/arch/riscv/include/stdint.h @@ -70,8 +70,8 @@ #define false 0 /* Types for `void *' pointers. */ -typedef s64 intptr_t; -typedef u64 uintptr_t; +typedef long intptr_t; +typedef unsigned long uintptr_t; /* FIXME: This is used in some print code and may be removed in the future. */ #define PRIu64 "llu" -- To view, visit https://review.coreboot.org/27768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b Gerrit-Change-Number: 27768 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: southbridge/intel: Remove leftover TPM ACPI code
by Philipp Deppenwiese (Code Review) 31 Jul '18

31 Jul '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/27767 Change subject: southbridge/intel: Remove leftover TPM ACPI code ...................................................................... southbridge/intel: Remove leftover TPM ACPI code Remove ACPI code which isn't necessary anymore due to the LPC TPM ACPI generator. Change-Id: I2fae286d61ec7c1036d1a8fa800dc8d9603252e9 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/southbridge/intel/i82801gx/acpi/lpc.asl M src/southbridge/intel/lynxpoint/acpi/lpc.asl 2 files changed, 0 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/27767/1 diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index 2bcd06f..87eab07 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -199,29 +199,6 @@ #include "acpi/superio.asl" -#if IS_ENABLED(CONFIG_LPC_TPM) - Device (TPM) // Trusted Platform Module - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - }) - } -#endif - Device (PS2K) // Keyboard { Name(_HID, EISAID("PNP0303")) diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index 1df49e3..b677e6a 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -223,27 +223,4 @@ } #include "acpi/superio.asl" - -#if IS_ENABLED(CONFIG_LPC_TPM) - Device (TPM) // Trusted Platform Module - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - }) - } -#endif } -- To view, visit https://review.coreboot.org/27767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2fae286d61ec7c1036d1a8fa800dc8d9603252e9 Gerrit-Change-Number: 27767 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: soc/intel/cannonlake: Report Whiskey Lake info
by Furquan Shaikh (Code Review) 31 Jul '18

31 Jul '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27756 ) Change subject: soc/intel/cannonlake: Report Whiskey Lake info ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/27756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3fbc190e0520989d2fd4a9b3294e84d67e49b2cf Gerrit-Change-Number: 27756 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Aug 2018 00:51:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Report Whiskey Lake info
by Lijian Zhao (Code Review) 31 Jul '18

31 Jul '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/27756 ) Change subject: soc/intel/cannonlake: Report Whiskey Lake info ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27756/1/src/soc/intel/cannonlake/bootblock/… File src/soc/intel/cannonlake/bootblock/report_platform.c: https://review.coreboot.org/#/c/27756/1/src/soc/intel/cannonlake/bootblock/… PS1, Line 72: Cannonlake > Whiskeylake? Thanks for point it out, done. -- To view, visit https://review.coreboot.org/27756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3fbc190e0520989d2fd4a9b3294e84d67e49b2cf Gerrit-Change-Number: 27756 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Aug 2018 00:30:35 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/cannonlake: Report Whiskey Lake info
by Lijian Zhao (Code Review) 31 Jul '18

31 Jul '18

Hello Subrata Banik, Bora Guvendik, build bot (Jenkins), Krzysztof M Sywula, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27756 to look at the new patch set (#2). Change subject: soc/intel/cannonlake: Report Whiskey Lake info ...................................................................... soc/intel/cannonlake: Report Whiskey Lake info According to #574725, report Whiskey Lake CPUID, MCH device ID and graphics device ID in bootblock stage. BUG=N/A TEST=Build and boot up whiskey lake rvp platform and check serial log to see proper CPU/MCH/GFX/PCH got recognized. Change-Id: I3fbc190e0520989d2fd4a9b3294e84d67e49b2cf Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/report_platform.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/27756/2 -- To view, visit https://review.coreboot.org/27756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3fbc190e0520989d2fd4a9b3294e84d67e49b2cf Gerrit-Change-Number: 27756 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/cannonlake: Update UPD from device switch
by Lijian Zhao (Code Review) 31 Jul '18

31 Jul '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/27766 Change subject: soc/intel/cannonlake: Update UPD from device switch ...................................................................... soc/intel/cannonlake: Update UPD from device switch Some of the FSP silicon UPD entry can be updated base on device switch in pci device tree, have both static config setting and device tree "on" and "off" will be redundant. BUG=N/A TEST=Build and boot up fine with Whiskey Lake RVP platform. Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb M src/mainboard/google/zoombini/variants/meowth/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h 9 files changed, 40 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/27766/1 diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb index 479f280..f993ae9 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb @@ -21,9 +21,7 @@ # FSP configuration register "SaGv" = "3" register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index bbff695..ef40ccc 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -30,9 +30,7 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 6bd90a5..3357140 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -7,9 +7,7 @@ # FSP configuration register "SaGv" = "3" register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 4c62800..02d6b70 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -7,9 +7,7 @@ # FSP configuration register "SaGv" = "3" register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb index 9414b32..de316ca 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb @@ -7,9 +7,7 @@ # FSP configuration register "SaGv" = "3" register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb index 5bebdec..45877f4 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb @@ -7,9 +7,7 @@ # FSP configuration register "SaGv" = "3" register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb index 62a6635..7e5cd60 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb @@ -7,9 +7,7 @@ # FSP configuration register "SaGv" = "3" register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "1" register "HeciEnabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" @@ -30,7 +28,6 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - register "SataEnable" = "1" register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 30719ed..6768057 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -208,16 +208,25 @@ params->PchLockDownRtcMemoryLock = 0; /* SATA */ - params->SataEnable = config->SataEnable; - params->SataMode = config->SataMode; - params->SataSalpSupport = config->SataSalpSupport; - memcpy(params->SataPortsEnable, config->SataPortsEnable, + dev = dev_find_slot(0, PCH_DEVFN_SATA); + if (!dev) + params->SataEnable = 0; + else { + params->SataEnable = dev->enabled; + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + memcpy(params->SataPortsEnable, config->SataPortsEnable, sizeof(params->SataPortsEnable)); - memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, sizeof(params->SataPortsDevSlp)); + } /* Lan */ - params->PchLanEnable = config->PchLanEnable; + dev = dev_find_slot(0, PCH_DEVFN_GBE); + if (!dev) + params->PchLanEnable = 0; + else + params->PchLanEnable = dev->enabled; /* Audio */ params->PchHdaDspEnable = config->PchHdaDspEnable; @@ -283,16 +292,32 @@ sizeof(config->PcieClkSrcClkReq)); /* eMMC and SD */ - params->ScsEmmcEnabled = config->ScsEmmcEnabled; - params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; - params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed; - if (config->EmmcHs400DllNeed == 1) { - params->PchScsEmmcHs400RxStrobeDll1 = - config->EmmcHs400RxStrobeDll1; - params->PchScsEmmcHs400TxDataDll = config->EmmcHs400TxDataDll; + dev = dev_find_slot(0, PCH_DEVFN_EMMC); + if (!dev) + params->ScsEmmcEnabled = 0; + else { + params->ScsEmmcEnabled = dev->enabled; + params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed; + if (config->EmmcHs400DllNeed == 1) { + params->PchScsEmmcHs400RxStrobeDll1 = + config->EmmcHs400RxStrobeDll1; + params->PchScsEmmcHs400TxDataDll = + config->EmmcHs400TxDataDll; + } } - params->ScsSdCardEnabled = config->ScsSdCardEnabled; - params->ScsUfsEnabled = config->ScsUfsEnabled; + + dev = dev_find_slot(0, PCH_DEVFN_SDCARD); + if (!dev) + params->ScsSdCardEnabled = 0; + else + params->ScsSdCardEnabled = dev->enabled; + + dev = dev_find_slot(0, PCH_DEVFN_UFS); + if (!dev) + params->ScsUfsEnabled = 0; + else + params->ScsUfsEnabled = dev->enabled; params->Heci3Enabled = config->Heci3Enabled; params->Device4Enable = config->Device4Enable; diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 4704d1c..e018cab 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -118,9 +118,6 @@ /* Rank Margin Tool. 1:Enable, 0:Disable */ uint8_t RMT; - /* LAN controller. 1:Enable, 0:Disable */ - uint8_t PchLanEnable; - /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; @@ -130,9 +127,7 @@ /* Wake Enable Bitmap for USB3 ports */ uint16_t usb3_wake_enable_bitmap; - /* SATA related */ - uint8_t SataEnable; uint8_t SataMode; uint8_t SataSalpSupport; uint8_t SataPortsEnable[8]; @@ -168,7 +163,6 @@ uint8_t SmbusEnable; /* eMMC and SD */ - uint8_t ScsEmmcEnabled; uint8_t ScsEmmcHs400Enabled; /* Need to update DLL setting to get Emmc running at HS400 speed */ uint8_t EmmcHs400DllNeed; @@ -176,8 +170,6 @@ uint8_t EmmcHs400RxStrobeDll1; /* 0-78: number of active delay for TX data, unit is 125 psec */ uint8_t EmmcHs400TxDataDll; - uint8_t ScsSdCardEnabled; - uint8_t ScsUfsEnabled; /* Integrated Sensor */ uint8_t PchIshEnable; -- To view, visit https://review.coreboot.org/27766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9 Gerrit-Change-Number: 27766 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: google/banon: Add support for additional RAM types/configs
by Matt DeVillier (Code Review) 31 Jul '18

31 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27764 to look at the new patch set (#5). Change subject: google/banon: Add support for additional RAM types/configs ...................................................................... google/banon: Add support for additional RAM types/configs Adapted from chromium commits 831a372 and cc96c27 [Banon: board 2nd source DDR memory] Add support for hynix/H9CCNNN8GTALAR-NUD and Nanya/NT6CL256T32CM-H1 Original-Change-Id: Ifd161ba5ade44e71c88655f760ca66668b5c5178 Original-Change-Id: I5cba13701ed8e037e21d34ed55162ee56291a842 Original-Signed-off-by: T.H. Lin <T.H_Lin(a)quantatw.com> Original-Tested-by: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Original-Reviewed-by: Vincent Wang <vwang(a)chromium.org> Original-Reviewed-by: YH Lin <yueherngl(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I2166d1025ede33148c7ab623ba59190a342c4736 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/variants/banon/Makefile.inc M src/mainboard/google/cyan/variants/banon/spd_util.c 2 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/27764/5 -- To view, visit https://review.coreboot.org/27764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2166d1025ede33148c7ab623ba59190a342c4736 Gerrit-Change-Number: 27764 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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