coreboot-gerrit August 2018

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Change in coreboot[master]: Documentation/Makefile.sphinx: Be cautious when running `rm -rf`
by Tristan Corrick (Code Review) 01 Aug '18

01 Aug '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/27775 Change subject: Documentation/Makefile.sphinx: Be cautious when running `rm -rf` ...................................................................... Documentation/Makefile.sphinx: Be cautious when running `rm -rf` If BUILDDIR were an empty string, running `make clean` would result in running `rm -rf /*`. Omitting the trailing /* prevents this. With a valid BUILDDIR, the behaviour of `make clean` changes slightly in that BUILDDIR itself is removed. However, this is probably more in line with what one would expect from `make clean`. Change-Id: I51b52bb6e7fe73a07fed6291a4f1cc253f2bf319 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M Documentation/Makefile.sphinx 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/27775/1 diff --git a/Documentation/Makefile.sphinx b/Documentation/Makefile.sphinx index 0ecebbe..2357f18 100644 --- a/Documentation/Makefile.sphinx +++ b/Documentation/Makefile.sphinx @@ -46,7 +46,7 @@ .PHONY: clean clean: - rm -rf $(BUILDDIR)/* + rm -rf $(BUILDDIR) .PHONY: html html: -- To view, visit https://review.coreboot.org/27775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I51b52bb6e7fe73a07fed6291a4f1cc253f2bf319 Gerrit-Change-Number: 27775 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: sb/intel/common/pmutil: Add and use method to switch sleep state
by Patrick Rudolph (Code Review) 01 Aug '18

01 Aug '18

Hello Felix Held, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27774 to look at the new patch set (#3). Change subject: sb/intel/common/pmutil: Add and use method to switch sleep state ...................................................................... sb/intel/common/pmutil: Add and use method to switch sleep state Add pm_enter_sleepstate() to switch to a different sleep state. Make use of it on google mainboards. Change-Id: I0cc7aebd672f3c30b55cfe591a77ee1c65036d28 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/google/link/mainboard_smi.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/mainboard_smi.c M src/mainboard/samsung/lumpy/smihandler.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h 7 files changed, 50 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/27774/3 -- To view, visit https://review.coreboot.org/27774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0cc7aebd672f3c30b55cfe591a77ee1c65036d28 Gerrit-Change-Number: 27774 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/common/pmutil: Add and use method to switch sleep state
by Patrick Rudolph (Code Review) 01 Aug '18

01 Aug '18

Hello Felix Held, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27774 to look at the new patch set (#2). Change subject: sb/intel/common/pmutil: Add and use method to switch sleep state ...................................................................... sb/intel/common/pmutil: Add and use method to switch sleep state Add pm_enter_sleepstate() to switch to a different sleep state. Make use of it on google mainboards. Change-Id: I0cc7aebd672f3c30b55cfe591a77ee1c65036d28 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/google/link/mainboard_smi.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/mainboard_smi.c M src/mainboard/samsung/lumpy/smihandler.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h 7 files changed, 49 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/27774/2 -- To view, visit https://review.coreboot.org/27774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0cc7aebd672f3c30b55cfe591a77ee1c65036d28 Gerrit-Change-Number: 27774 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/common/pmutil: Add and use method to switch sleep state
by Patrick Rudolph (Code Review) 01 Aug '18

01 Aug '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27774 Change subject: sb/intel/common/pmutil: Add and use method to switch sleep state ...................................................................... sb/intel/common/pmutil: Add and use method to switch sleep state Add pm_enter_sleepstate() to switch to a different sleep state. Make use of it on google mainboards. Change-Id: I0cc7aebd672f3c30b55cfe591a77ee1c65036d28 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/google/link/mainboard_smi.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/mainboard_smi.c M src/mainboard/samsung/lumpy/smihandler.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h 7 files changed, 48 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/27774/1 diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index 0bd164e..2b1bf5c 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -20,7 +20,7 @@ #include <southbridge/intel/bd82x6x/nvs.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> -#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/pmutil.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> #include <elog.h> @@ -44,7 +44,7 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + pm_enter_sleepstate(5); break; } diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index e30f78f..694aa7a 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -20,7 +20,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/pmutil.h> -#include <southbridge/intel/common/pmbase.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> #include <elog.h> @@ -54,7 +53,7 @@ elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); #endif /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + pm_enter_sleepstate(5); break; } @@ -75,7 +74,7 @@ elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); #endif /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + pm_enter_sleepstate(5); } } diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 229f919..eaf0870 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -115,7 +115,7 @@ printk(BIOS_ERR, "EC critical_shutdown"); /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + pm_enter_sleepstate(5); } } #endif //__SMM__ diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 6a51645..ce693dc 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -19,7 +19,7 @@ #include <southbridge/intel/bd82x6x/nvs.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> -#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/pmutil.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> @@ -35,7 +35,7 @@ case EC_SMI_LID_CLOSED: printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + pm_enter_sleepstate(5); break; } diff --git a/src/mainboard/samsung/lumpy/smihandler.c b/src/mainboard/samsung/lumpy/smihandler.c index f2c2dc3..f2c8d10 100644 --- a/src/mainboard/samsung/lumpy/smihandler.c +++ b/src/mainboard/samsung/lumpy/smihandler.c @@ -19,7 +19,7 @@ #include <southbridge/intel/bd82x6x/nvs.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> -#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/pmutil.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> #include <ec/smsc/mec1308/ec.h> @@ -36,7 +36,7 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + pm_enter_sleepstate(5); break; } diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index ac72eba..06d0882 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -24,6 +24,8 @@ #include <pc80/mc146818rtc.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/gpio.h> +#include <arch/acpi.h> + #include "pmutil.h" @@ -234,3 +236,39 @@ return reg16; } + +/** + * @brief Enter the requested sleep state + * @arg Sx_state sleep state (0 - 5) + */ +void pm_enter_sleepstate(u8 Sx_state) +{ + u32 reg32; + + reg32 = read_pmbase32(PM1_CNT); + reg32 &= ~SLP_TYP; + + switch (Sx_state) { + case 0: + reg32 |= SLP_TYP_S0 << SLP_TYP_SHIFT; + break; + case 1: + reg32 |= SLP_TYP_S1 << SLP_TYP_SHIFT; + break; + case 3: + reg32 |= SLP_TYP_S3 << SLP_TYP_SHIFT; + break; + case 4: + reg32 |= SLP_TYP_S4 << SLP_TYP_SHIFT; + break; + case 5: + reg32 |= SLP_TYP_S5 << SLP_TYP_SHIFT; + break; + default: + return; + } + + reg32 |= SLP_EN; + + write_pmbase32(PM1_CNT, reg32); +} diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 273e0f8..983ba41 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -119,6 +119,7 @@ u16 reset_alt_gp_smi_status(void); void southbridge_smm_xhci_sleep(u8 slp_type); void gpi_route_interrupt(u8 gpi, u8 mode); +void pm_enter_sleepstate(u8 Sx_state); void southbridge_gate_memory_reset(void); void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); void southbridge_finalize_all(void); -- To view, visit https://review.coreboot.org/27774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0cc7aebd672f3c30b55cfe591a77ee1c65036d28 Gerrit-Change-Number: 27774 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: drivers/spi: Winbond specific write-protection enable
by build bot (Jenkins) (Code Review) 01 Aug '18

01 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25105 ) Change subject: drivers/spi: Winbond specific write-protection enable ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/#/c/25105/12/src/drivers/spi/winbond.c File src/drivers/spi/winbond.c: https://review.coreboot.org/#/c/25105/12/src/drivers/spi/winbond.c@39 PS12, Line 39: #define CMD_VOLTILE_SREG_WREN 0x50 /* Write Enable for Volatile Status Register */ line over 80 characters -- To view, visit https://review.coreboot.org/25105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Gerrit-Change-Number: 25105 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Aug 2018 10:22:49 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/spi: Winbond specific write-protection enable
by build bot (Jenkins) (Code Review) 01 Aug '18

01 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25105 ) Change subject: drivers/spi: Winbond specific write-protection enable ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/25105/11/src/drivers/spi/winbond.c File src/drivers/spi/winbond.c: https://review.coreboot.org/#/c/25105/11/src/drivers/spi/winbond.c@39 PS11, Line 39: #define CMD_VOLTILE_SREG_WREN 0x50 /* Write Enable for Volatile Status Register */ line over 80 characters -- To view, visit https://review.coreboot.org/25105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Gerrit-Change-Number: 25105 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Aug 2018 09:50:22 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/spi: Read Winbond's flash protection bits
by build bot (Jenkins) (Code Review) 01 Aug '18

01 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25082 ) Change subject: drivers/spi: Read Winbond's flash protection bits ...................................................................... Patch Set 13: (9 comments) https://review.coreboot.org/#/c/25082/13/src/drivers/spi/winbond.c File src/drivers/spi/winbond.c: https://review.coreboot.org/#/c/25082/13/src/drivers/spi/winbond.c@52 PS13, Line 52: uint8_t *const prot; "foo *const bar" should be "foo *const bar" https://review.coreboot.org/#/c/25082/13/src/drivers/spi/winbond.c@132 PS13, Line 132: .prot = (u8[6]){ space required before the open brace '{' https://review.coreboot.org/#/c/25082/13/src/drivers/spi/winbond.c@150 PS13, Line 150: .prot = (u8[7]){ space required before the open brace '{' https://review.coreboot.org/#/c/25082/13/src/drivers/spi/winbond.c@169 PS13, Line 169: .prot = (u8[7]){ space required before the open brace '{' https://review.coreboot.org/#/c/25082/13/src/drivers/spi/winbond.c@188 PS13, Line 188: .prot = (u8[7]){ space required before the open brace '{' https://review.coreboot.org/#/c/25082/13/src/drivers/spi/winbond.c@207 PS13, Line 207: .prot = (u8[7]){ space required before the open brace '{' https://review.coreboot.org/#/c/25082/13/src/drivers/spi/winbond.c@226 PS13, Line 226: .prot = (u8[7]){ space required before the open brace '{' https://review.coreboot.org/#/c/25082/13/src/drivers/spi/winbond.c@245 PS13, Line 245: .prot = (u8[7]){ space required before the open brace '{' https://review.coreboot.org/#/c/25082/13/src/drivers/spi/winbond.c@264 PS13, Line 264: .prot = (u8[10]){ space required before the open brace '{' -- To view, visit https://review.coreboot.org/25082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I933a8abdc28174ec32acf323c102d606b58c1ea5 Gerrit-Change-Number: 25082 Gerrit-PatchSet: 13 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Wed, 01 Aug 2018 09:12:42 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/spi: Winbond specific write-protection enable
by build bot (Jenkins) (Code Review) 01 Aug '18

01 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25105 ) Change subject: drivers/spi: Winbond specific write-protection enable ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/#/c/25105/10/src/drivers/spi/winbond.c File src/drivers/spi/winbond.c: https://review.coreboot.org/#/c/25105/10/src/drivers/spi/winbond.c@39 PS10, Line 39: #define CMD_VOLTILE_SREG_WREN 0x50 /* Write Enable for Volatile Status Register */ line over 80 characters -- To view, visit https://review.coreboot.org/25105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Gerrit-Change-Number: 25105 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Aug 2018 09:12:33 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/spi: Winbond specific write-protection enable
by build bot (Jenkins) (Code Review) 01 Aug '18

01 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25105 ) Change subject: drivers/spi: Winbond specific write-protection enable ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/25105/9/src/drivers/spi/winbond.c File src/drivers/spi/winbond.c: https://review.coreboot.org/#/c/25105/9/src/drivers/spi/winbond.c@39 PS9, Line 39: #define CMD_VOLTILE_SREG_WREN 0x50 /* Write Enable for Volatile Status Register */ line over 80 characters -- To view, visit https://review.coreboot.org/25105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Gerrit-Change-Number: 25105 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Aug 2018 06:58:03 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Set CABC_EN to GPO high before EDP...
by Seunghwan Kim (Code Review) 01 Aug '18

01 Aug '18

Seunghwan Kim has posted comments on this change. ( https://review.coreboot.org/27773 ) Change subject: mb/google/poppy/variants/nautilus: Set CABC_EN to GPO high before EDP power on ...................................................................... Patch Set 1: Need Marx@intel's confirm first. -- To view, visit https://review.coreboot.org/27773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I34e2fe86329a88eb05e0ea3c6beac6a64754b41e Gerrit-Change-Number: 27773 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Comment-Date: Wed, 01 Aug 2018 06:21:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit August 2018