coreboot-gerrit August 2018

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Change in coreboot[master]: mb/google, samsung/*: Add LPC TPM chip driver to devicetree
by Philipp Deppenwiese (Code Review) 02 Aug '18

02 Aug '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/27786 ) Change subject: mb/google,samsung/*: Add LPC TPM chip driver to devicetree ...................................................................... mb/google,samsung/*: Add LPC TPM chip driver to devicetree With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code] and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver (drivers/pc80/tpm) must be added to devicetree in order to ensure the new acpigen code is used to replace it. Test: boot various google/samsung boards, verify SSDT created with LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/27786 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/rambi/variants/banjo/devicetree.cb M src/mainboard/google/rambi/variants/candy/devicetree.cb M src/mainboard/google/rambi/variants/clapper/devicetree.cb M src/mainboard/google/rambi/variants/enguarde/devicetree.cb M src/mainboard/google/rambi/variants/glimmer/devicetree.cb M src/mainboard/google/rambi/variants/gnawty/devicetree.cb M src/mainboard/google/rambi/variants/heli/devicetree.cb M src/mainboard/google/rambi/variants/kip/devicetree.cb M src/mainboard/google/rambi/variants/ninja/devicetree.cb M src/mainboard/google/rambi/variants/orco/devicetree.cb M src/mainboard/google/rambi/variants/quawks/devicetree.cb M src/mainboard/google/rambi/variants/rambi/devicetree.cb M src/mainboard/google/rambi/variants/squawks/devicetree.cb M src/mainboard/google/rambi/variants/sumo/devicetree.cb M src/mainboard/google/rambi/variants/swanky/devicetree.cb M src/mainboard/google/rambi/variants/winky/devicetree.cb M src/mainboard/google/slippy/variants/falco/devicetree.cb M src/mainboard/google/slippy/variants/leon/devicetree.cb M src/mainboard/google/slippy/variants/peppy/devicetree.cb M src/mainboard/google/slippy/variants/wolf/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb 27 files changed, 81 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Philipp Deppenwiese: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 90409cd..89758dd 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -96,6 +96,9 @@ device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip superio/ite/it8772f # Skip keyboard init register "skip_keyboard" = "1" diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 9b44fe8..692414c 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -87,6 +87,9 @@ device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on #LPC bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/quanta/ene_kb3940q # 60/64 KBC device pnp ff.1 on # dummy address diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 8a2129f..d34bf7a 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -76,6 +76,9 @@ device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip superio/ite/it8772f # Skip keyboard init register "skip_keyboard" = "1" diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 437b3cb..07be8e7 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -86,6 +86,9 @@ device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/banjo/devicetree.cb b/src/mainboard/google/rambi/variants/banjo/devicetree.cb index e380920..acfb271 100644 --- a/src/mainboard/google/rambi/variants/banjo/devicetree.cb +++ b/src/mainboard/google/rambi/variants/banjo/devicetree.cb @@ -88,6 +88,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/candy/devicetree.cb b/src/mainboard/google/rambi/variants/candy/devicetree.cb index 5cbb974..e4a39e9 100644 --- a/src/mainboard/google/rambi/variants/candy/devicetree.cb +++ b/src/mainboard/google/rambi/variants/candy/devicetree.cb @@ -89,6 +89,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/clapper/devicetree.cb b/src/mainboard/google/rambi/variants/clapper/devicetree.cb index 13902b0..497a0b1 100644 --- a/src/mainboard/google/rambi/variants/clapper/devicetree.cb +++ b/src/mainboard/google/rambi/variants/clapper/devicetree.cb @@ -76,6 +76,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/enguarde/devicetree.cb b/src/mainboard/google/rambi/variants/enguarde/devicetree.cb index 89929b0..3b00bb7 100644 --- a/src/mainboard/google/rambi/variants/enguarde/devicetree.cb +++ b/src/mainboard/google/rambi/variants/enguarde/devicetree.cb @@ -88,6 +88,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/glimmer/devicetree.cb b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb index 5148225..db26366 100644 --- a/src/mainboard/google/rambi/variants/glimmer/devicetree.cb +++ b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb @@ -85,6 +85,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/gnawty/devicetree.cb b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb index 0024679..30320cc 100644 --- a/src/mainboard/google/rambi/variants/gnawty/devicetree.cb +++ b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb @@ -88,6 +88,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/heli/devicetree.cb b/src/mainboard/google/rambi/variants/heli/devicetree.cb index 8b3c83f..c3ec601 100644 --- a/src/mainboard/google/rambi/variants/heli/devicetree.cb +++ b/src/mainboard/google/rambi/variants/heli/devicetree.cb @@ -89,6 +89,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/kip/devicetree.cb b/src/mainboard/google/rambi/variants/kip/devicetree.cb index d1d6beb..5bb99f0 100644 --- a/src/mainboard/google/rambi/variants/kip/devicetree.cb +++ b/src/mainboard/google/rambi/variants/kip/devicetree.cb @@ -88,6 +88,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/ninja/devicetree.cb b/src/mainboard/google/rambi/variants/ninja/devicetree.cb index 5c9595c..c983681 100644 --- a/src/mainboard/google/rambi/variants/ninja/devicetree.cb +++ b/src/mainboard/google/rambi/variants/ninja/devicetree.cb @@ -89,6 +89,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/orco/devicetree.cb b/src/mainboard/google/rambi/variants/orco/devicetree.cb index 8291794..63b6097 100644 --- a/src/mainboard/google/rambi/variants/orco/devicetree.cb +++ b/src/mainboard/google/rambi/variants/orco/devicetree.cb @@ -88,6 +88,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/quawks/devicetree.cb b/src/mainboard/google/rambi/variants/quawks/devicetree.cb index 320b59b..0e1f789 100644 --- a/src/mainboard/google/rambi/variants/quawks/devicetree.cb +++ b/src/mainboard/google/rambi/variants/quawks/devicetree.cb @@ -85,6 +85,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/rambi/devicetree.cb b/src/mainboard/google/rambi/variants/rambi/devicetree.cb index ddd1914..a24bd33 100644 --- a/src/mainboard/google/rambi/variants/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/variants/rambi/devicetree.cb @@ -89,6 +89,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/squawks/devicetree.cb b/src/mainboard/google/rambi/variants/squawks/devicetree.cb index 46f2385..ae4bfe5 100644 --- a/src/mainboard/google/rambi/variants/squawks/devicetree.cb +++ b/src/mainboard/google/rambi/variants/squawks/devicetree.cb @@ -85,6 +85,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/sumo/devicetree.cb b/src/mainboard/google/rambi/variants/sumo/devicetree.cb index 89e2f2b..f354815 100644 --- a/src/mainboard/google/rambi/variants/sumo/devicetree.cb +++ b/src/mainboard/google/rambi/variants/sumo/devicetree.cb @@ -89,6 +89,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/swanky/devicetree.cb b/src/mainboard/google/rambi/variants/swanky/devicetree.cb index db21bd6..d591e3f 100644 --- a/src/mainboard/google/rambi/variants/swanky/devicetree.cb +++ b/src/mainboard/google/rambi/variants/swanky/devicetree.cb @@ -88,6 +88,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/winky/devicetree.cb b/src/mainboard/google/rambi/variants/winky/devicetree.cb index 6d52b89..9c25d1e 100644 --- a/src/mainboard/google/rambi/variants/winky/devicetree.cb +++ b/src/mainboard/google/rambi/variants/winky/devicetree.cb @@ -89,6 +89,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/slippy/variants/falco/devicetree.cb b/src/mainboard/google/slippy/variants/falco/devicetree.cb index cdf47cf..f2a9520 100644 --- a/src/mainboard/google/slippy/variants/falco/devicetree.cb +++ b/src/mainboard/google/slippy/variants/falco/devicetree.cb @@ -109,6 +109,9 @@ device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/slippy/variants/leon/devicetree.cb b/src/mainboard/google/slippy/variants/leon/devicetree.cb index b0edb7f..8951e99 100644 --- a/src/mainboard/google/slippy/variants/leon/devicetree.cb +++ b/src/mainboard/google/slippy/variants/leon/devicetree.cb @@ -114,6 +114,9 @@ device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/slippy/variants/peppy/devicetree.cb b/src/mainboard/google/slippy/variants/peppy/devicetree.cb index e9875a6..6451d95 100644 --- a/src/mainboard/google/slippy/variants/peppy/devicetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/devicetree.cb @@ -113,6 +113,9 @@ device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/slippy/variants/wolf/devicetree.cb b/src/mainboard/google/slippy/variants/wolf/devicetree.cb index 7655c41..2cad23b 100644 --- a/src/mainboard/google/slippy/variants/wolf/devicetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/devicetree.cb @@ -114,6 +114,9 @@ device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 76f2856..0fdb55e 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -97,6 +97,9 @@ device pci 1d.0 on end # USB2 EHCI #1 (Camera, WLAN, WWAN) device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/quanta/it8518 # 60h/64h KBC device pnp ff.1 on # dummy address diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 0dd3228..0362b2c 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -119,6 +119,9 @@ register "base" = "(void *)0xfec00000" device ioapic 4 on end end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end device pci 1f.2 on # SATA Controller 1 ioapic_irq 4 INTA 0x10 diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index adc15e6..825dfa0 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -116,6 +116,9 @@ end # Mouse device pnp 2e.a off end # IR end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on end # SMBus -- To view, visit https://review.coreboot.org/27786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480 Gerrit-Change-Number: 27786 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/mb/google/poppy/variants/atlas: Apply correct AC/DC loadlines
by Gaggery Tsai (Code Review) 02 Aug '18

02 Aug '18

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/27788 Change subject: src/mb/google/poppy/variants/atlas: Apply correct AC/DC loadlines ...................................................................... src/mb/google/poppy/variants/atlas: Apply correct AC/DC loadlines This patch applies correct AC/DC loadline settings for Atlas from VRTT report. BUG=b/111419622 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage and use DbC to check the AC/DC loadline settgins. Change-Id: I6e85b885a6d3a1db9a980d12f3cfc036a771422a Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/27788/1 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index f6610df..f2c2a12 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -88,8 +88,8 @@ #| ImonOffset | 0 | 0 | 0 | 0 | #| IccMax | 4A | 24A | 24A | 24A | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 14.9 | 5 | 5.7 | 4.57 | - #| DcLoadline | 14.2 | 4.86 | 4.2 | 4.3 | + #| AcLoadline | 14.75 | 4.42 | 4.7 | 4.7 | + #| DcLoadline | 14.2 | 4.2 | 4.41 | 4.41 | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, @@ -102,7 +102,7 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(4), .voltage_limit = 1520, - .ac_loadline = 1490, + .ac_loadline = 1475, .dc_loadline = 1420, }" @@ -117,8 +117,8 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, - .ac_loadline = 500, - .dc_loadline = 486, + .ac_loadline = 442, + .dc_loadline = 420, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ @@ -132,8 +132,8 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, - .ac_loadline = 570, - .dc_loadline = 420, + .ac_loadline = 470, + .dc_loadline = 441, }" register "domain_vr_config[VR_GT_SLICED]" = "{ @@ -147,8 +147,8 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, - .ac_loadline = 457, - .dc_loadline = 430, + .ac_loadline = 470, + .dc_loadline = 441, }" # PCIe Root port 1 with SRCCLKREQ1# -- To view, visit https://review.coreboot.org/27788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6e85b885a6d3a1db9a980d12f3cfc036a771422a Gerrit-Change-Number: 27788 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com>

1 0

Change in coreboot[master]: mb/google, samsung/*: Add LPC TPM chip driver to devicetree
by Philipp Deppenwiese (Code Review) 02 Aug '18

02 Aug '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27786 ) Change subject: mb/google,samsung/*: Add LPC TPM chip driver to devicetree ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/27786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480 Gerrit-Change-Number: 27786 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Aug 2018 22:23:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/lenovo/x1_carbon_gen1: add support for hynix memory
by Arthur Heymans (Code Review) 01 Aug '18

01 Aug '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27781 ) Change subject: mb/lenovo/x1_carbon_gen1: add support for hynix memory ...................................................................... Patch Set 3: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/27781/3/src/mainboard/lenovo/x1_carbon_gen1… File src/mainboard/lenovo/x1_carbon_gen1/romstage.c: https://review.coreboot.org/#/c/27781/3/src/mainboard/lenovo/x1_carbon_gen1… PS3, Line 116: memcpy(&spd[2], memory, 256); Not sure if I fully get the comment above but if a configuration has only one slot populated you might want to make this conditional? -- To view, visit https://review.coreboot.org/27781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib93c0e3cbdc29cbf6cff26292df4fbbb8208082f Gerrit-Change-Number: 27781 Gerrit-PatchSet: 3 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Aug 2018 20:26:14 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/lenovo/x1_carbon_gen1: add vbt
by Arthur Heymans (Code Review) 01 Aug '18

01 Aug '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27782 ) Change subject: mb/lenovo/x1_carbon_gen1: add vbt ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/27782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id59517d9040c98e67a42fbce537f42f6b0c6db2d Gerrit-Change-Number: 27782 Gerrit-PatchSet: 4 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Aug 2018 20:22:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google, samsung/*: Add LPC TPM chip driver to devicetree
by Arthur Heymans (Code Review) 01 Aug '18

01 Aug '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27786 ) Change subject: mb/google,samsung/*: Add LPC TPM chip driver to devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480 Gerrit-Change-Number: 27786 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Aug 2018 19:47:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/bucts: Add tool to manipulate BUC.TS bit on Intel targets
by build bot (Jenkins) (Code Review) 01 Aug '18

01 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18224 ) Change subject: util/bucts: Add tool to manipulate BUC.TS bit on Intel targets ...................................................................... Patch Set 5: (18 comments) https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c File util/bucts/bucts.c: https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@31 PS5, Line 31: #if defined (__sun) && (defined(__i386) || defined(__amd64)) space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@75 PS5, Line 75: return MAP_FAILED == virt_addr ? NULL : virt_addr; Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@113 PS5, Line 113: if (EINVAL == errno) { Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@131 PS5, Line 131: static int get_platform_info(struct pci_dev *sb, int *has_var_bb, uint32_t *rcba_addr) line over 80 characters https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@238 PS5, Line 238: int spi_is_bootdevice = ((*(uint16_t *)(rcba + GCS_OFFSET) >> 10) & 3) == 3; line over 80 characters https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@241 PS5, Line 241: *(uint32_t *)(rcba + SPIBAR + FDOC) = (PCHSTRAPS_SECTION << 12) | 0; line over 80 characters https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@262 PS5, Line 262: ? "set, changing top swap not possible" : "unset, changing top swap is possible"); line over 80 characters https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@263 PS5, Line 263: printf("Top Swap : %s\n", ts ? "Enabled" : "Disabled"); line over 80 characters https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@266 PS5, Line 266: printf("Ranges swapped : 0x%llx-0x%08llx <-> 0x%08llx-0x%08llx", line over 80 characters https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@289 PS5, Line 289: printf("BIOS Interface Lock-Down set, Changing Top Swap not possible.\n"); line over 80 characters https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@342 PS5, Line 342: printf("Invalid setting: multiple set/unset arguments\n"); line over 80 characters https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@346 PS5, Line 346: printf("Print and Set are mutually exclusive!\n"); line over 80 characters https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@354 PS5, Line 354: printf("Invalid setting: multiple set/unset arguments\n"); line over 80 characters https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@358 PS5, Line 358: printf("Print and Set are mutually exclusive!\n"); line over 80 characters https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@366 PS5, Line 366: printf("Print and Set are mutually exclusive!\n"); line over 80 characters https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@375 PS5, Line 375: default: Possible switch case/default not preceded by break or fallthrough comment https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@389 PS5, Line 389: if ((io_fd = open("/dev/io", O_RDWR)) < 0) { do not use assignment in if condition https://review.coreboot.org/#/c/18224/5/util/bucts/bucts.c@399 PS5, Line 399: if (-1 == (fd_mem = open(MEM_DEV, O_RDWR | O_SYNC))) { do not use assignment in if condition -- To view, visit https://review.coreboot.org/18224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I12cc2e91396f096fc979e23848e1929cb6c44fc5 Gerrit-Change-Number: 18224 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Aug 2018 19:45:52 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: util/bucts: Add tool to manipulate BUC.TS bit on Intel targets
by build bot (Jenkins) (Code Review) 01 Aug '18

01 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18224 ) Change subject: util/bucts: Add tool to manipulate BUC.TS bit on Intel targets ...................................................................... Patch Set 4: (19 comments) https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c File util/bucts/bucts.c: https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@31 PS4, Line 31: #if defined (__sun) && (defined(__i386) || defined(__amd64)) space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@75 PS4, Line 75: return MAP_FAILED == virt_addr ? NULL : virt_addr; Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@113 PS4, Line 113: if (EINVAL == errno) { Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@131 PS4, Line 131: static int get_platform_info(struct pci_dev *sb, int *has_var_bb, uint32_t *rcba_addr) line over 80 characters https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@238 PS4, Line 238: int spi_is_bootdevice = ((*(uint16_t *)(rcba + GCS_OFFSET) >> 10) & 3) == 3; line over 80 characters https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@241 PS4, Line 241: *(uint32_t *)(rcba + SPIBAR + FDOC) = (PCHSTRAPS_SECTION << 12) | 0; line over 80 characters https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@262 PS4, Line 262: ? "set, changing top swap not possible" : "unset, changing top swap is possible"); line over 80 characters https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@263 PS4, Line 263: printf("Top Swap : %s\n", ts ? "Enabled" : "Disabled"); line over 80 characters https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@266 PS4, Line 266: printf("Ranges swapped : 0x%llx-0x%08llx <-> 0x%08llx-0x%08llx", line over 80 characters https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@289 PS4, Line 289: printf("BIOS Interface Lock-Down set, Changing Top Swap not possible.\n"); line over 80 characters https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@342 PS4, Line 342: printf("Invalid setting: multiple set/unset arguments\n"); line over 80 characters https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@346 PS4, Line 346: printf("Print and Set are mutually exclusive!\n"); line over 80 characters https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@354 PS4, Line 354: printf("Invalid setting: multiple set/unset arguments\n"); line over 80 characters https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@358 PS4, Line 358: printf("Print and Set are mutually exclusive!\n"); line over 80 characters https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@366 PS4, Line 366: printf("Print and Set are mutually exclusive!\n"); line over 80 characters https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@375 PS4, Line 375: default: Possible switch case/default not preceded by break or fallthrough comment https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@389 PS4, Line 389: if ((io_fd = open("/dev/io", O_RDWR)) < 0) { do not use assignment in if condition https://review.coreboot.org/#/c/18224/4/util/bucts/bucts.c@399 PS4, Line 399: if (-1 == (fd_mem = open(MEM_DEV, O_RDWR | O_SYNC))) { do not use assignment in if condition https://review.coreboot.org/#/c/18224/4/util/bucts/readme.md File util/bucts/readme.md: https://review.coreboot.org/#/c/18224/4/util/bucts/readme.md@30 PS4, Line 30: trailing whitespace -- To view, visit https://review.coreboot.org/18224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I12cc2e91396f096fc979e23848e1929cb6c44fc5 Gerrit-Change-Number: 18224 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Aug 2018 19:38:16 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/auron, cyan: Remove interrupt from devicetree LPC TPM chip d...
by Matt DeVillier (Code Review) 01 Aug '18

01 Aug '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27787 Change subject: mb/google/auron,cyan: Remove interrupt from devicetree LPC TPM chip driver ...................................................................... mb/google/auron,cyan: Remove interrupt from devicetree LPC TPM chip driver These boards require polling vs interrupts, so remove the IRQ definition to prevent it being added to the SSDT device entry. Test: Boot Linux on various auron and cyan variants, verify no error for 'TPM interrupt not working' present in kernel boot log. Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/variants/auron_paine/devicetree.cb M src/mainboard/google/auron/variants/auron_yuna/devicetree.cb M src/mainboard/google/auron/variants/gandof/devicetree.cb M src/mainboard/google/auron/variants/lulu/devicetree.cb M src/mainboard/google/auron/variants/samus/devicetree.cb M src/mainboard/google/cyan/variants/banon/devicetree.cb M src/mainboard/google/cyan/variants/celes/devicetree.cb M src/mainboard/google/cyan/variants/cyan/devicetree.cb M src/mainboard/google/cyan/variants/edgar/devicetree.cb M src/mainboard/google/cyan/variants/kefka/devicetree.cb M src/mainboard/google/cyan/variants/reks/devicetree.cb M src/mainboard/google/cyan/variants/relm/devicetree.cb M src/mainboard/google/cyan/variants/setzer/devicetree.cb M src/mainboard/google/cyan/variants/terra/devicetree.cb M src/mainboard/google/cyan/variants/ultima/devicetree.cb M src/mainboard/google/cyan/variants/wizpig/devicetree.cb 16 files changed, 17 insertions(+), 81 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/27787/1 diff --git a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb index 5872cf2..b31d829 100644 --- a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb @@ -91,11 +91,7 @@ device pci 1e.0 off end # PCI bridge device pci 1f.0 on chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb index 34051a7..3c00ec9 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb @@ -91,11 +91,7 @@ device pci 1e.0 off end # PCI bridge device pci 1f.0 on chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/auron/variants/gandof/devicetree.cb b/src/mainboard/google/auron/variants/gandof/devicetree.cb index 06ff8ae..118e646 100644 --- a/src/mainboard/google/auron/variants/gandof/devicetree.cb +++ b/src/mainboard/google/auron/variants/gandof/devicetree.cb @@ -90,12 +90,8 @@ device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on - chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + chip drivers/pc80/tpm + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb index 84fc8c4..622ea34 100644 --- a/src/mainboard/google/auron/variants/lulu/devicetree.cb +++ b/src/mainboard/google/auron/variants/lulu/devicetree.cb @@ -92,11 +92,7 @@ device pci 1e.0 off end # PCI bridge device pci 1f.0 on chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/auron/variants/samus/devicetree.cb b/src/mainboard/google/auron/variants/samus/devicetree.cb index d12762d..a6c2fea 100644 --- a/src/mainboard/google/auron/variants/samus/devicetree.cb +++ b/src/mainboard/google/auron/variants/samus/devicetree.cb @@ -95,11 +95,7 @@ device pci 1e.0 off end # PCI bridge device pci 1f.0 on chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/cyan/variants/banon/devicetree.cb b/src/mainboard/google/cyan/variants/banon/devicetree.cb index 8d16d04..60076c2 100644 --- a/src/mainboard/google/cyan/variants/banon/devicetree.cb +++ b/src/mainboard/google/cyan/variants/banon/devicetree.cb @@ -135,11 +135,7 @@ device pci 1e.7 off end # 8086 22ac - SPI 3 device pci 1f.0 on # 8086 229c - LPC bridge chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/cyan/variants/celes/devicetree.cb b/src/mainboard/google/cyan/variants/celes/devicetree.cb index 84edd74..2e708af 100644 --- a/src/mainboard/google/cyan/variants/celes/devicetree.cb +++ b/src/mainboard/google/cyan/variants/celes/devicetree.cb @@ -135,11 +135,7 @@ device pci 1e.7 off end # 8086 22ac - SPI 3 device pci 1f.0 on # 8086 229c - LPC bridge chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/cyan/variants/cyan/devicetree.cb b/src/mainboard/google/cyan/variants/cyan/devicetree.cb index 0454650..dd9b05e 100644 --- a/src/mainboard/google/cyan/variants/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/variants/cyan/devicetree.cb @@ -128,11 +128,7 @@ device pci 1e.7 off end # 8086 22ac - SPI 3 device pci 1f.0 on # 8086 229c - LPC bridge chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/cyan/variants/edgar/devicetree.cb b/src/mainboard/google/cyan/variants/edgar/devicetree.cb index 2033f9e..0ba221e 100644 --- a/src/mainboard/google/cyan/variants/edgar/devicetree.cb +++ b/src/mainboard/google/cyan/variants/edgar/devicetree.cb @@ -129,11 +129,7 @@ device pci 1e.7 off end # 8086 22ac - SPI 3 device pci 1f.0 on # 8086 229c - LPC bridge chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/cyan/variants/kefka/devicetree.cb b/src/mainboard/google/cyan/variants/kefka/devicetree.cb index e6542cb..1ce056f 100644 --- a/src/mainboard/google/cyan/variants/kefka/devicetree.cb +++ b/src/mainboard/google/cyan/variants/kefka/devicetree.cb @@ -142,11 +142,7 @@ device pci 1e.7 off end # 8086 22ac - SPI 3 device pci 1f.0 on # 8086 229c - LPC bridge chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/cyan/variants/reks/devicetree.cb b/src/mainboard/google/cyan/variants/reks/devicetree.cb index 53239b5..302f2da 100644 --- a/src/mainboard/google/cyan/variants/reks/devicetree.cb +++ b/src/mainboard/google/cyan/variants/reks/devicetree.cb @@ -126,11 +126,7 @@ device pci 1e.7 off end # 8086 22ac - SPI 3 device pci 1f.0 on # 8086 229c - LPC bridge chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/cyan/variants/relm/devicetree.cb b/src/mainboard/google/cyan/variants/relm/devicetree.cb index eb48ace..65e662c 100644 --- a/src/mainboard/google/cyan/variants/relm/devicetree.cb +++ b/src/mainboard/google/cyan/variants/relm/devicetree.cb @@ -142,11 +142,7 @@ device pci 1e.7 off end # 8086 22ac - SPI 3 device pci 1f.0 on # 8086 229c - LPC bridge chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/cyan/variants/setzer/devicetree.cb b/src/mainboard/google/cyan/variants/setzer/devicetree.cb index b8480a3..f0b2c6f 100644 --- a/src/mainboard/google/cyan/variants/setzer/devicetree.cb +++ b/src/mainboard/google/cyan/variants/setzer/devicetree.cb @@ -135,11 +135,7 @@ device pci 1e.7 off end # 8086 22ac - SPI 3 device pci 1f.0 on # 8086 229c - LPC bridge chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/cyan/variants/terra/devicetree.cb b/src/mainboard/google/cyan/variants/terra/devicetree.cb index 2feb1a3..d7d0f1f 100644 --- a/src/mainboard/google/cyan/variants/terra/devicetree.cb +++ b/src/mainboard/google/cyan/variants/terra/devicetree.cb @@ -135,11 +135,7 @@ device pci 1e.7 off end # 8086 22ac - SPI 3 device pci 1f.0 on # 8086 229c - LPC bridge chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/cyan/variants/ultima/devicetree.cb b/src/mainboard/google/cyan/variants/ultima/devicetree.cb index 287dd02..d4ed38b 100644 --- a/src/mainboard/google/cyan/variants/ultima/devicetree.cb +++ b/src/mainboard/google/cyan/variants/ultima/devicetree.cb @@ -129,11 +129,7 @@ device pci 1e.7 off end # 8086 22ac - SPI 3 device pci 1f.0 on # 8086 229c - LPC bridge chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/cyan/variants/wizpig/devicetree.cb b/src/mainboard/google/cyan/variants/wizpig/devicetree.cb index 3fb3053..7be7a0f 100644 --- a/src/mainboard/google/cyan/variants/wizpig/devicetree.cb +++ b/src/mainboard/google/cyan/variants/wizpig/devicetree.cb @@ -136,11 +136,7 @@ device pci 1e.7 off end # 8086 22ac - SPI 3 device pci 1f.0 on # 8086 229c - LPC bridge chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end -- To view, visit https://review.coreboot.org/27787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88 Gerrit-Change-Number: 27787 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: mb/google, samsung/*: Add LPC TPM chip driver to devicetree
by Matt DeVillier (Code Review) 01 Aug '18

01 Aug '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27786 Change subject: mb/google,samsung/*: Add LPC TPM chip driver to devicetree ...................................................................... mb/google,samsung/*: Add LPC TPM chip driver to devicetree With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code] and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver (drivers/pc80/tpm) must be added to devicetree in order to ensure the new acpigen code is used to replace it. Test: boot various google/samsung boards, verify SSDT created with LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/rambi/variants/banjo/devicetree.cb M src/mainboard/google/rambi/variants/candy/devicetree.cb M src/mainboard/google/rambi/variants/clapper/devicetree.cb M src/mainboard/google/rambi/variants/enguarde/devicetree.cb M src/mainboard/google/rambi/variants/glimmer/devicetree.cb M src/mainboard/google/rambi/variants/gnawty/devicetree.cb M src/mainboard/google/rambi/variants/heli/devicetree.cb M src/mainboard/google/rambi/variants/kip/devicetree.cb M src/mainboard/google/rambi/variants/ninja/devicetree.cb M src/mainboard/google/rambi/variants/orco/devicetree.cb M src/mainboard/google/rambi/variants/quawks/devicetree.cb M src/mainboard/google/rambi/variants/rambi/devicetree.cb M src/mainboard/google/rambi/variants/squawks/devicetree.cb M src/mainboard/google/rambi/variants/sumo/devicetree.cb M src/mainboard/google/rambi/variants/swanky/devicetree.cb M src/mainboard/google/rambi/variants/winky/devicetree.cb M src/mainboard/google/slippy/variants/falco/devicetree.cb M src/mainboard/google/slippy/variants/leon/devicetree.cb M src/mainboard/google/slippy/variants/peppy/devicetree.cb M src/mainboard/google/slippy/variants/wolf/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb 27 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/27786/1 diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 90409cd..89758dd 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -96,6 +96,9 @@ device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip superio/ite/it8772f # Skip keyboard init register "skip_keyboard" = "1" diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 9b44fe8..692414c 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -87,6 +87,9 @@ device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on #LPC bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/quanta/ene_kb3940q # 60/64 KBC device pnp ff.1 on # dummy address diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 8a2129f..d34bf7a 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -76,6 +76,9 @@ device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip superio/ite/it8772f # Skip keyboard init register "skip_keyboard" = "1" diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 437b3cb..07be8e7 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -86,6 +86,9 @@ device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/banjo/devicetree.cb b/src/mainboard/google/rambi/variants/banjo/devicetree.cb index e380920..acfb271 100644 --- a/src/mainboard/google/rambi/variants/banjo/devicetree.cb +++ b/src/mainboard/google/rambi/variants/banjo/devicetree.cb @@ -88,6 +88,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/candy/devicetree.cb b/src/mainboard/google/rambi/variants/candy/devicetree.cb index 5cbb974..e4a39e9 100644 --- a/src/mainboard/google/rambi/variants/candy/devicetree.cb +++ b/src/mainboard/google/rambi/variants/candy/devicetree.cb @@ -89,6 +89,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/clapper/devicetree.cb b/src/mainboard/google/rambi/variants/clapper/devicetree.cb index 13902b0..497a0b1 100644 --- a/src/mainboard/google/rambi/variants/clapper/devicetree.cb +++ b/src/mainboard/google/rambi/variants/clapper/devicetree.cb @@ -76,6 +76,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/enguarde/devicetree.cb b/src/mainboard/google/rambi/variants/enguarde/devicetree.cb index 89929b0..3b00bb7 100644 --- a/src/mainboard/google/rambi/variants/enguarde/devicetree.cb +++ b/src/mainboard/google/rambi/variants/enguarde/devicetree.cb @@ -88,6 +88,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/glimmer/devicetree.cb b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb index 5148225..db26366 100644 --- a/src/mainboard/google/rambi/variants/glimmer/devicetree.cb +++ b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb @@ -85,6 +85,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/gnawty/devicetree.cb b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb index 0024679..30320cc 100644 --- a/src/mainboard/google/rambi/variants/gnawty/devicetree.cb +++ b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb @@ -88,6 +88,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/heli/devicetree.cb b/src/mainboard/google/rambi/variants/heli/devicetree.cb index 8b3c83f..c3ec601 100644 --- a/src/mainboard/google/rambi/variants/heli/devicetree.cb +++ b/src/mainboard/google/rambi/variants/heli/devicetree.cb @@ -89,6 +89,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/kip/devicetree.cb b/src/mainboard/google/rambi/variants/kip/devicetree.cb index d1d6beb..5bb99f0 100644 --- a/src/mainboard/google/rambi/variants/kip/devicetree.cb +++ b/src/mainboard/google/rambi/variants/kip/devicetree.cb @@ -88,6 +88,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/ninja/devicetree.cb b/src/mainboard/google/rambi/variants/ninja/devicetree.cb index 5c9595c..c983681 100644 --- a/src/mainboard/google/rambi/variants/ninja/devicetree.cb +++ b/src/mainboard/google/rambi/variants/ninja/devicetree.cb @@ -89,6 +89,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/orco/devicetree.cb b/src/mainboard/google/rambi/variants/orco/devicetree.cb index 8291794..63b6097 100644 --- a/src/mainboard/google/rambi/variants/orco/devicetree.cb +++ b/src/mainboard/google/rambi/variants/orco/devicetree.cb @@ -88,6 +88,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/quawks/devicetree.cb b/src/mainboard/google/rambi/variants/quawks/devicetree.cb index 320b59b..0e1f789 100644 --- a/src/mainboard/google/rambi/variants/quawks/devicetree.cb +++ b/src/mainboard/google/rambi/variants/quawks/devicetree.cb @@ -85,6 +85,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/rambi/devicetree.cb b/src/mainboard/google/rambi/variants/rambi/devicetree.cb index ddd1914..a24bd33 100644 --- a/src/mainboard/google/rambi/variants/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/variants/rambi/devicetree.cb @@ -89,6 +89,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/squawks/devicetree.cb b/src/mainboard/google/rambi/variants/squawks/devicetree.cb index 46f2385..ae4bfe5 100644 --- a/src/mainboard/google/rambi/variants/squawks/devicetree.cb +++ b/src/mainboard/google/rambi/variants/squawks/devicetree.cb @@ -85,6 +85,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/sumo/devicetree.cb b/src/mainboard/google/rambi/variants/sumo/devicetree.cb index 89e2f2b..f354815 100644 --- a/src/mainboard/google/rambi/variants/sumo/devicetree.cb +++ b/src/mainboard/google/rambi/variants/sumo/devicetree.cb @@ -89,6 +89,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/swanky/devicetree.cb b/src/mainboard/google/rambi/variants/swanky/devicetree.cb index db21bd6..d591e3f 100644 --- a/src/mainboard/google/rambi/variants/swanky/devicetree.cb +++ b/src/mainboard/google/rambi/variants/swanky/devicetree.cb @@ -88,6 +88,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/winky/devicetree.cb b/src/mainboard/google/rambi/variants/winky/devicetree.cb index 6d52b89..9c25d1e 100644 --- a/src/mainboard/google/rambi/variants/winky/devicetree.cb +++ b/src/mainboard/google/rambi/variants/winky/devicetree.cb @@ -89,6 +89,9 @@ device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/slippy/variants/falco/devicetree.cb b/src/mainboard/google/slippy/variants/falco/devicetree.cb index cdf47cf..f2a9520 100644 --- a/src/mainboard/google/slippy/variants/falco/devicetree.cb +++ b/src/mainboard/google/slippy/variants/falco/devicetree.cb @@ -109,6 +109,9 @@ device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/slippy/variants/leon/devicetree.cb b/src/mainboard/google/slippy/variants/leon/devicetree.cb index b0edb7f..8951e99 100644 --- a/src/mainboard/google/slippy/variants/leon/devicetree.cb +++ b/src/mainboard/google/slippy/variants/leon/devicetree.cb @@ -114,6 +114,9 @@ device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/slippy/variants/peppy/devicetree.cb b/src/mainboard/google/slippy/variants/peppy/devicetree.cb index e9875a6..6451d95 100644 --- a/src/mainboard/google/slippy/variants/peppy/devicetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/devicetree.cb @@ -113,6 +113,9 @@ device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/slippy/variants/wolf/devicetree.cb b/src/mainboard/google/slippy/variants/wolf/devicetree.cb index 7655c41..2cad23b 100644 --- a/src/mainboard/google/slippy/variants/wolf/devicetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/devicetree.cb @@ -114,6 +114,9 @@ device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 76f2856..0fdb55e 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -97,6 +97,9 @@ device pci 1d.0 on end # USB2 EHCI #1 (Camera, WLAN, WWAN) device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/quanta/it8518 # 60h/64h KBC device pnp ff.1 on # dummy address diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 0dd3228..0362b2c 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -119,6 +119,9 @@ register "base" = "(void *)0xfec00000" device ioapic 4 on end end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end device pci 1f.2 on # SATA Controller 1 ioapic_irq 4 INTA 0x10 diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index adc15e6..825dfa0 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -116,6 +116,9 @@ end # Mouse device pnp 2e.a off end # IR end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on end # SMBus -- To view, visit https://review.coreboot.org/27786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480 Gerrit-Change-Number: 27786 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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coreboot-gerrit August 2018