coreboot-gerrit August 2018

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Set CABC_EN to GPO high before EDP...
by Seunghwan Kim (Code Review) 01 Aug '18

01 Aug '18

Seunghwan Kim has uploaded this change for review. ( https://review.coreboot.org/27773 Change subject: mb/google/poppy/variants/nautilus: Set CABC_EN to GPO high before EDP power on ...................................................................... mb/google/poppy/variants/nautilus: Set CABC_EN to GPO high before EDP power on If GPP_E22(CABC_EN) remained floating GPI(SoC default) at V3.3_DX_EDP on, it may cause damage on the GPIO pad. To prevent, we would set this pad to GPO on romstage before EDP power on. Since we need to cover all systems in market, I put it into romstage instead of early_gpio_table. BUG=b:111860510 BRANCH=poppy TEST=Verified CABC_EN is set to GPO high 5ms before EDP power on Change-Id: I34e2fe86329a88eb05e0ea3c6beac6a64754b41e Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/poppy/variants/nautilus/memory.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/27773/1 diff --git a/src/mainboard/google/poppy/variants/nautilus/memory.c b/src/mainboard/google/poppy/variants/nautilus/memory.c index dc845bc..bf2accf 100644 --- a/src/mainboard/google/poppy/variants/nautilus/memory.c +++ b/src/mainboard/google/poppy/variants/nautilus/memory.c @@ -14,6 +14,7 @@ */ #include <baseboard/variants.h> +#include <gpio.h> /* DQ byte map */ static const u8 dq_map[][12] = { @@ -46,4 +47,8 @@ p->rcomp_resistor_size = sizeof(rcomp_resistor); p->rcomp_target = rcomp_target; p->rcomp_target_size = sizeof(rcomp_target); + + /* Ensure GPP_E22(CABC_EN) is set to GPO before enabling V3.3_DX_EDP. + * If it is remained floating GPI, it may cause damage on the pad.*/ + gpio_output(GPP_E22, 1); } -- To view, visit https://review.coreboot.org/27773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I34e2fe86329a88eb05e0ea3c6beac6a64754b41e Gerrit-Change-Number: 27773 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com>

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Change in coreboot[master]: mb/google/poppy/variant/nami: Set IA/GT/SA
by TH Lin (Code Review) 01 Aug '18

01 Aug '18

TH Lin has posted comments on this change. ( https://review.coreboot.org/27772 ) Change subject: mb/google/poppy/variant/nami: Set IA/GT/SA ...................................................................... Patch Set 2: Here is another possible solution. Only set IslVrCmd, no changing on slowslewrate on IA/SA/GT.... -- To view, visit https://review.coreboot.org/27772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iccc52a60bbf6fba7550794c417c7293d870fe3a0 Gerrit-Change-Number: 27772 Gerrit-PatchSet: 2 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Aug 2018 06:09:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/nami: Set IA/GT/SA
by TH Lin (Code Review) 01 Aug '18

01 Aug '18

TH Lin has uploaded a new patch set (#2). ( https://review.coreboot.org/27772 ) Change subject: mb/google/poppy/variant/nami: Set IA/GT/SA ...................................................................... mb/google/poppy/variant/nami: Set IA/GT/SA Set IA/GT 0.25V Set SA PS4 BUG=b:111912585 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Iccc52a60bbf6fba7550794c417c7293d870fe3a0 Signed-off-by: T.H. Lin <t.h_lin(a)quanta.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/mainboard.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/27772/2 -- To view, visit https://review.coreboot.org/27772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iccc52a60bbf6fba7550794c417c7293d870fe3a0 Gerrit-Change-Number: 27772 Gerrit-PatchSet: 2 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variant/nami: Set IA/GT/SA
by build bot (Jenkins) (Code Review) 01 Aug '18

01 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27772 ) Change subject: mb/google/poppy/variant/nami: Set IA/GT/SA ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27772/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nami/mainboard.c: https://review.coreboot.org/#/c/27772/1/src/mainboard/google/poppy/variants… PS1, Line 91: cfg->IslVrCmd = 2; code indent should use tabs where possible -- To view, visit https://review.coreboot.org/27772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iccc52a60bbf6fba7550794c417c7293d870fe3a0 Gerrit-Change-Number: 27772 Gerrit-PatchSet: 1 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Aug 2018 06:02:27 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/nami: Set IA/GT/SA
by TH Lin (Code Review) 01 Aug '18

01 Aug '18

TH Lin has uploaded this change for review. ( https://review.coreboot.org/27772 Change subject: mb/google/poppy/variant/nami: Set IA/GT/SA ...................................................................... mb/google/poppy/variant/nami: Set IA/GT/SA Set IA/GT 0.25V Set SA PS4 BUG=b:111912585 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Iccc52a60bbf6fba7550794c417c7293d870fe3a0 Signed-off-by: T.H. Lin <t.h_lin(a)quanta.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/mainboard.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/27772/1 diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 8080c94..a589068 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -83,6 +83,13 @@ /* Disable unused port USB port */ cfg->usb2_ports[5].enable = 0; break; + case SKU_0_AKALI: + case SKU_1_AKALI: + case SKU_0_AKALI360: + case SKU_1_AKALI360: + /* send VR mailbox command for IA/GT/SA rails */ + cfg->IslVrCmd = 2; + break; default: break; } -- To view, visit https://review.coreboot.org/27772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iccc52a60bbf6fba7550794c417c7293d870fe3a0 Gerrit-Change-Number: 27772 Gerrit-PatchSet: 1 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: security/tpm: TCPA log follow up
by Julius Werner (Code Review) 01 Aug '18

01 Aug '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/27769 ) Change subject: security/tpm: TCPA log follow up ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/27769/1/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/27769/1/src/security/tpm/tspi/log.c@24 PS1, Line 24: static Does this build correctly for x86 verstage? I guess it might get optimized out. Still, I think it's safer to use MAYBE_STATIC (and explicitly initialize to NULL) so correctness is not dependent on such details. https://review.coreboot.org/#/c/27769/1/src/security/tpm/tspi/log.c@31 PS1, Line 31: NULL Doesn't this need to be 'return ce'? https://review.coreboot.org/#/c/27769/1/src/security/tpm/tspi/log.c@57 PS1, Line 57: printk(BIOS_ERR, "ERROR: No TCPA log table found\n"); Now you'll have the problem Furquan fixed again. I think you probably just want to move this error message back into tcpa_log_init() and only print it for the cbmem_add() failure (which is the only real error, all other code paths are WAI). https://review.coreboot.org/#/c/27769/1/src/security/tpm/tspi/log.c@68 PS1, Line 68: TCPA_PCR_HASH_NAME You need to subtract 1 here or you might not write the null terminator and get weird output in cbmem. (Or you can fix the cbmem implementation to not read more than TCPA_PCR_HASH_NAME chars from this, which I don't think it currently checks for.) -- To view, visit https://review.coreboot.org/27769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I215d79eed7ad17c6ab87f0c4b14a282e519ef07d Gerrit-Change-Number: 27769 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Aug 2018 05:02:22 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: add suport to check machine length at runtime
by Xiang Wang (Code Review) 01 Aug '18

01 Aug '18

Xiang Wang has uploaded a new patch set (#2). ( https://review.coreboot.org/27770 ) Change subject: riscv: add suport to check machine length at runtime ...................................................................... riscv: add suport to check machine length at runtime Highest two bits of misa can be used to check machine length. Add code to support this. Change-Id: I3bab301d38ea8aabf2c70437e179287814298b25 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/include/arch/cpu.h 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/27770/2 -- To view, visit https://review.coreboot.org/27770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3bab301d38ea8aabf2c70437e179287814298b25 Gerrit-Change-Number: 27770 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: riscv: add suport to check machine length at runtime
by Xiang Wang (Code Review) 01 Aug '18

01 Aug '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27770 Change subject: riscv: add suport to check machine length at runtime ...................................................................... riscv: add suport to check machine length at runtime Highest two bits of misa can be used to check machine length. Add code to support this. Change-Id: I3bab301d38ea8aabf2c70437e179287814298b25 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/include/arch/cpu.h 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/27770/1 diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index 6008c75..d8a49b8 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -51,5 +51,17 @@ return read_csr(misa) & (1 << (ext - 'A')); } +static inline int xlen(void) +{ + long t = read_csr(misa); + if (t < 0) { + t = t << 1; + if (t < 0) + return 128; + return 64; + } + return 32; +} + struct cpu_info *cpu_info(void); #endif /* __ARCH_CPU_H__ */ -- To view, visit https://review.coreboot.org/27770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3bab301d38ea8aabf2c70437e179287814298b25 Gerrit-Change-Number: 27770 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: security/tpm: TCPA log follow up
by Philipp Deppenwiese (Code Review) 01 Aug '18

01 Aug '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/27769 Change subject: security/tpm: TCPA log follow up ...................................................................... security/tpm: TCPA log follow up * Make tcpa_log_init static and remove init call * Fix tcpa_log_add_table_entry Change-Id: I215d79eed7ad17c6ab87f0c4b14a282e519ef07d Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/commonlib/include/commonlib/tcpa_log_serialized.h M src/drivers/tpm/tpm.c M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/vboot/secdata_tpm.c 5 files changed, 18 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27769/1 diff --git a/src/commonlib/include/commonlib/tcpa_log_serialized.h b/src/commonlib/include/commonlib/tcpa_log_serialized.h index cd6fbec..6dfb566 100644 --- a/src/commonlib/include/commonlib/tcpa_log_serialized.h +++ b/src/commonlib/include/commonlib/tcpa_log_serialized.h @@ -29,7 +29,7 @@ uint32_t pcr; uint8_t digest[TCPA_DIGEST_MAX_LENGTH]; uint32_t digest_length; - uint8_t name[TCPA_PCR_HASH_NAME]; + char name[TCPA_PCR_HASH_NAME]; } __packed; struct tcpa_table { diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c index 8c68159..e4a81c3 100644 --- a/src/drivers/tpm/tpm.c +++ b/src/drivers/tpm/tpm.c @@ -30,9 +30,6 @@ #else tpm_setup(false); #endif - - // TCPA cbmem log - tcpa_log_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, init_tpm_dev, NULL); diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 94b53b0..e4ddefc 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -21,11 +21,6 @@ #include <commonlib/tcpa_log_serialized.h> /** - * Setup TCPA cbmem log. - */ -void tcpa_log_init(void); - -/** * Add table entry for cbmem TCPA log. */ void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 8ec4c6d..50a23d9 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -18,42 +18,41 @@ #include <console/console.h> #include <security/tpm/tspi.h> -void tcpa_log_init(void) +static struct tcpa_table *tcpa_log_init(void) { const struct cbmem_entry *ce; - struct tcpa_table *tclt; + static struct tcpa_table *tclt; if (!cbmem_possibly_online()) - return; + return NULL; ce = cbmem_entry_find(CBMEM_ID_TCPA_LOG); if (ce) - return; + return NULL; tclt = cbmem_add(CBMEM_ID_TCPA_LOG, sizeof(struct tcpa_table) + - MAX_TCPA_LOG_ENTRIES * - sizeof(struct tcpa_entry)); + MAX_TCPA_LOG_ENTRIES * + sizeof(struct tcpa_entry)); if (!tclt) - return; + return NULL; tclt->max_entries = MAX_TCPA_LOG_ENTRIES; tclt->num_entries = 0; printk(BIOS_DEBUG, "TCPA log created at %p\n", tclt); + + return tclt; } void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, const uint8_t *digest, const size_t digest_length) { - MAYBE_STATIC struct tcpa_table *tclt = NULL; + struct tcpa_table *tclt; struct tcpa_entry *tce; - if (!cbmem_possibly_online()) - return; - - tclt = cbmem_find(CBMEM_ID_TCPA_LOG); + tclt = tcpa_log_init(); if (!tclt) { printk(BIOS_ERR, "ERROR: No TCPA log table found\n"); return; @@ -66,8 +65,13 @@ tce = &tclt->entries[tclt->num_entries++]; - memcpy(tce->name, name, TCPA_PCR_HASH_NAME); + strncpy(tce->name, name, TCPA_PCR_HASH_NAME); tce->pcr = pcr; + + if (digest_length > TCPA_DIGEST_MAX_LENGTH) { + printk(BIOS_WARNING, "ERROR: PCR digest too long for TCPA log entry\n"); + return; + } memcpy(tce->digest, digest, digest_length); tce->digest_length = digest_length; } diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index d3f4a11..c62f18b 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -451,9 +451,6 @@ if (result == TPM_E_MUST_REBOOT) ctx->flags |= VB2_CONTEXT_SECDATA_WANTS_REBOOT; - // TCPA cbmem log - tcpa_log_init(); - return result; } -- To view, visit https://review.coreboot.org/27769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I215d79eed7ad17c6ab87f0c4b14a282e519ef07d Gerrit-Change-Number: 27769 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: riscv: update the definition of intptr_t/uintptr_t
by Xiang Wang (Code Review) 01 Aug '18

01 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27768 to look at the new patch set (#5). Change subject: riscv: update the definition of intptr_t/uintptr_t ...................................................................... riscv: update the definition of intptr_t/uintptr_t These RISC-V ABIs defined by GCC : ilp32 ilp32d ilp32f lp64 lp64d lp64f. Through this we know that the length of the long's bit is equal to pointer. So update this code. This's more flexible. Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/include/stdint.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27768/5 -- To view, visit https://review.coreboot.org/27768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b Gerrit-Change-Number: 27768 Gerrit-PatchSet: 5 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit August 2018