coreboot-gerrit August 2018

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Change in coreboot[master]: mb/google/poppy/variant/nami: GT Slow Slew rate
by TH Lin (Code Review) 02 Aug '18

02 Aug '18

TH Lin has posted comments on this change. ( https://review.coreboot.org/27799 ) Change subject: mb/google/poppy/variant/nami: GT Slow Slew rate ...................................................................... Patch Set 1: Use new mainboard.c for GT slow slew rate -- To view, visit https://review.coreboot.org/27799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I12c1e558889717ce8becc2c7059a5c099d019ca5 Gerrit-Change-Number: 27799 Gerrit-PatchSet: 1 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Aug 2018 09:43:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/nami: GT Slow Slew rate
by TH Lin (Code Review) 02 Aug '18

02 Aug '18

TH Lin has uploaded this change for review. ( https://review.coreboot.org/27799 Change subject: mb/google/poppy/variant/nami: GT Slow Slew rate ...................................................................... mb/google/poppy/variant/nami: GT Slow Slew rate Set GT:Fast/8 BUG=b:111912585 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I12c1e558889717ce8becc2c7059a5c099d019ca5 Signed-off-by: T.H. Lin <t.h_lin(a)quanta.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/mainboard.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/27799/1 diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 2052ae0..3723c26 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -238,6 +238,14 @@ /* Disable unused port USB port */ cfg->usb2_ports[5].enable = 0; break; + case SKU_0_AKALI: + case SKU_1_AKALI: + case SKU_0_AKALI360: + case SKU_1_AKALI360: + /* Adjust the VR slew rates */ + cfg->AcousticNoiseMitigation = 1; + /* Fast/8 */ + cfg->SlowSlewRateForGt = 2; default: break; } -- To view, visit https://review.coreboot.org/27799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I12c1e558889717ce8becc2c7059a5c099d019ca5 Gerrit-Change-Number: 27799 Gerrit-PatchSet: 1 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: superio/nuvoton/nct6776/acpi: Add PS/2 mouse support
by Arthur Heymans (Code Review) 02 Aug '18

02 Aug '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27797 ) Change subject: superio/nuvoton/nct6776/acpi: Add PS/2 mouse support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7983f85b3fd23547950f1f75a81bbca63c63d52b Gerrit-Change-Number: 27797 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 02 Aug 2018 09:11:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: superio/nuvoton/nct6776/acpi: Add parallel port support
by Arthur Heymans (Code Review) 02 Aug '18

02 Aug '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27795 ) Change subject: superio/nuvoton/nct6776/acpi: Add parallel port support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2529a074e24433d093ad0650a45c7b29238620f3 Gerrit-Change-Number: 27795 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 02 Aug 2018 09:10:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: superio/nuvoton/nct6776/acpi: Fix typo in comments
by Arthur Heymans (Code Review) 02 Aug '18

02 Aug '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27794 ) Change subject: superio/nuvoton/nct6776/acpi: Fix typo in comments ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9ba69384866088f84a516557d76864104a024968 Gerrit-Change-Number: 27794 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 02 Aug 2018 09:09:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: superio/nuvoton/nct6776/acpi: Add PS/2 mouse support
by Tristan Corrick (Code Review) 02 Aug '18

02 Aug '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/27797 Change subject: superio/nuvoton/nct6776/acpi: Add PS/2 mouse support ...................................................................... superio/nuvoton/nct6776/acpi: Add PS/2 mouse support By defining SUPERIO_KBC_PS2M, ACPI code is added to show the PS/2 mouse. This has been tested on an ASUS P8H61-M LX with Linux 4.9.110 and 4.17.8. In each case, the PS/2 mouse works automatically, whereas it was not detected before. Change-Id: I7983f85b3fd23547950f1f75a81bbca63c63d52b Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/superio/nuvoton/nct6776/acpi/superio.asl 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/27797/1 diff --git a/src/superio/nuvoton/nct6776/acpi/superio.asl b/src/superio/nuvoton/nct6776/acpi/superio.asl index 980eab9..abd5562 100644 --- a/src/superio/nuvoton/nct6776/acpi/superio.asl +++ b/src/superio/nuvoton/nct6776/acpi/superio.asl @@ -152,6 +152,7 @@ #undef SUPERIO_KBC_PS2M #undef SUPERIO_KBC_PS2LDN #define SUPERIO_KBC_LDN 5 + #define SUPERIO_KBC_PS2M #include <superio/acpi/pnp_kbc.asl> #endif -- To view, visit https://review.coreboot.org/27797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7983f85b3fd23547950f1f75a81bbca63c63d52b Gerrit-Change-Number: 27797 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: mainboard: Add ASUS P8H61-M LX
by Tristan Corrick (Code Review) 02 Aug '18

02 Aug '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/27798 Change subject: mainboard: Add ASUS P8H61-M LX ...................................................................... mainboard: Add ASUS P8H61-M LX Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. This code is based on the output of autoport. The file `data.vbt` matches the VBT in the latest version of the vendor firmware (version 4601). This board works well under coreboot. A list of what works and what doesn't can be found in the documentation part of this commit. To summarise: the only known issues are that that S3 suspend/resume doesn't work, and that there is no automatic fan control via the super I/O. Change-Id: I2a0579f486d3a44de2dd927fa1e76b90c3b48f62 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- A Documentation/mainboard/asus/p8h61-m_lx.md M Documentation/mainboard/index.md A src/mainboard/asus/p8h61-m_lx/Kconfig A src/mainboard/asus/p8h61-m_lx/Kconfig.name A src/mainboard/asus/p8h61-m_lx/Makefile.inc A src/mainboard/asus/p8h61-m_lx/acpi/ec.asl A src/mainboard/asus/p8h61-m_lx/acpi/platform.asl A src/mainboard/asus/p8h61-m_lx/acpi/superio.asl A src/mainboard/asus/p8h61-m_lx/acpi_tables.c A src/mainboard/asus/p8h61-m_lx/board_info.txt A src/mainboard/asus/p8h61-m_lx/cmos.default A src/mainboard/asus/p8h61-m_lx/cmos.layout A src/mainboard/asus/p8h61-m_lx/data.vbt A src/mainboard/asus/p8h61-m_lx/devicetree.cb A src/mainboard/asus/p8h61-m_lx/dsdt.asl A src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads A src/mainboard/asus/p8h61-m_lx/gpio.c A src/mainboard/asus/p8h61-m_lx/hda_verb.c A src/mainboard/asus/p8h61-m_lx/mainboard.c A src/mainboard/asus/p8h61-m_lx/romstage.c 20 files changed, 892 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/27798/1 diff --git a/Documentation/mainboard/asus/p8h61-m_lx.md b/Documentation/mainboard/asus/p8h61-m_lx.md new file mode 100644 index 0000000..1ff22f8 --- /dev/null +++ b/Documentation/mainboard/asus/p8h61-m_lx.md @@ -0,0 +1,120 @@ +# ASUS P8H61-M LX + +This page describes how to run coreboot on the [ASUS P8H61-M LX]. + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | yes | ++---------------------+------------+ +| Model | W25Q32BV | ++---------------------+------------+ +| Size | 4 MiB | ++---------------------+------------+ +| Package | DIP-8 | ++---------------------+------------+ +| Write protection | no | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. By default, only +the BIOS region of the flash is writable. If you wish to change any +other region (Management Engine or flash descriptor), then an external +programmer is required. + +The following command may be used to flash coreboot: + +``` +$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom +``` + +The use of `--noverify-all` is required since the Management Engine +region is not readable even by the host. + +## Known issues + +- S3 suspend/resume does not work. This is the case for both coreboot + and the vendor firmware, tested with Linux 4.9, Linux 4.17, and + OpenBSD 6.3. Interestingly, it is possible to resume from S3 with + Linux, but _only_ if the resume is started immediately after the + suspend. + +- There is no automatic, OS-independent fan control. This is because + the super I/O hardware monitor can only obtain valid CPU temperature + readings from the PECI agent, whose complete initialisation is not + publicly documented. The `coretemp` driver can still be used for + accurate CPU temperature readings. + +## Untested + +- PCIe graphics +- parallel port +- PS/2 keyboard +- EHCI debug +- S/PDIF audio + +## Working + +- USB +- Gigabit Ethernet +- integrated graphics +- PCIe +- SATA +- PS/2 mouse +- serial port +- hardware monitor (see [Known issues](#known-issues) for caveats) +- onboard audio +- front panel audio +- native raminit (2 x 2GB, DDR3-1333) +- native graphics init (libgfxinit) +- flashrom under the vendor firmware +- flashrom under coreboot +- Wake-on-LAN + +## me_cleaner + +If using `me_cleaner` to remove modules from the Management Engine, +you might experience some issues (incorrect super I/O readings, +kernel warnings about loading audio codecs). If you add the argument +`--whitelist EFFS,FOVD,MDES,FCRS` when running `me_cleaner`, the +resulting ME should still allow correct system operation while having +most of its code removed. You may be able to whitelist fewer modules, +but this is not yet tested. Additionally, setting the AltMeDisable bit +doesn't appear to cause any problems. + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6776 | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +- [Board manual] +- [Flash chip datasheet][W25Q32BV] + +[ASUS P8H61-M LX]: https://www.asus.com/Motherboards/P8H61M_LX/ +[W25Q32BV]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.p… +[flashrom]: https://flashrom.org/Flashrom +[Board manual]: http://dlcdnet.asus.com/pub/ASUS/mb/LGA1155/P8H61_M_LX/E6803_P8H61-M_LX.zip diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 5d41cec..8bf0963 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -2,6 +2,10 @@ This section contains documentation about coreboot on specific mainboards. +## ASUS + +- [P8H61-M LX](asus/p8h61-m_lx.md) + ## Cavium - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md) diff --git a/src/mainboard/asus/p8h61-m_lx/Kconfig b/src/mainboard/asus/p8h61-m_lx/Kconfig new file mode 100644 index 0000000..715ba25 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/Kconfig @@ -0,0 +1,63 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASUS_P8H61_M_LX + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select CPU_INTEL_SOCKET_LGA1155 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select USE_NATIVE_RAMINIT + +config HAVE_IFD_BIN + bool + default n + +config MAINBOARD_DIR + string + default asus/p8h61-m_lx + +config MAINBOARD_PART_NUMBER + string + default "P8H61-M LX" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x844d + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1043 + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/asus/p8h61-m_lx/Kconfig.name b/src/mainboard/asus/p8h61-m_lx/Kconfig.name new file mode 100644 index 0000000..d62f437 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P8H61_M_LX + bool "P8H61-M LX" diff --git a/src/mainboard/asus/p8h61-m_lx/Makefile.inc b/src/mainboard/asus/p8h61-m_lx/Makefile.inc new file mode 100644 index 0000000..7c1bf9e --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8h61-m_lx/acpi/ec.asl b/src/mainboard/asus/p8h61-m_lx/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/acpi/ec.asl diff --git a/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl b/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl new file mode 100644 index 0000000..adaf51a --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK, 1) +{ + Return (Package() { 0, 0 }) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl b/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl new file mode 100644 index 0000000..b671e3c --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c new file mode 100644 index 0000000..1a584e0 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ +} diff --git a/src/mainboard/asus/p8h61-m_lx/board_info.txt b/src/mainboard/asus/p8h61-m_lx/board_info.txt new file mode 100644 index 0000000..9c7f972 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P8H61M_LX/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/asus/p8h61-m_lx/cmos.default b/src/mainboard/asus/p8h61-m_lx/cmos.default new file mode 100644 index 0000000..d3812ab --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +gfx_uma_size=64M +nmi=Enable +power_on_after_fail=Disable +sata_mode=AHCI diff --git a/src/mainboard/asus/p8h61-m_lx/cmos.layout b/src/mainboard/asus/p8h61-m_lx/cmos.layout new file mode 100644 index 0000000..9fe6fc2 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/cmos.layout @@ -0,0 +1,114 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 4 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode + +# coreboot config options: northbridge +412 3 e 7 gfx_uma_size + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +6 0 AHCI +6 1 Compatible + +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asus/p8h61-m_lx/data.vbt b/src/mainboard/asus/p8h61-m_lx/data.vbt new file mode 100644 index 0000000..7eda3ab --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/p8h61-m_lx/devicetree.cb new file mode 100644 index 0000000..5a40b31 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/devicetree.cb @@ -0,0 +1,137 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/socket_LGA1155 + device lapic 0 on end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off end + end + end + + register "pci_mmio_size" = "2048" + + device domain 0 on + subsystemid 0x1043 0x844d inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe bridge for discrete graphics + device pci 02.0 on end # VGA controller + + chip southbridge/intel/bd82x6x + register "c2_latency" = "101" + register "gen1_dec" = "0x00000295" # Super I/O HWM + register "p_cnt_throttling_supported" = "1" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # Management Engine interface 1 + device pci 16.1 off end # Management Engine interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on # HD audio controller + subsystemid 0x1043 0x8445 + end + device pci 1c.0 on end # PCIe 1x slot (PCIEX1_1) + device pci 1c.1 on end # PCIe 1x slot (PCIEX1_2) + device pci 1c.2 on # Realtek Gigabit Ethernet + subsystemid 0x1043 0x8432 + chip drivers/net + register "customized_leds" = "0x00f6" + device pci 00.0 on end + end + end + device pci 1c.3 off end # Unused PCIe port + device pci 1c.4 on end # PCIe 1x slot (PCIEX1_3) + device pci 1c.5 off end # Unused PCIe port + device pci 1c.6 off end # Unused PCIe port + device pci 1c.7 off end # Unused PCIe port + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on # ACPI + # Power RAM in S3. + irq 0xe4 = 0x10 + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0x0200 + + # Global registers to select + # HWM/LED functions instead of + # floppy functions. + irq 0x1c = 0x03 + irq 0x24 = 0x24 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on end # SATA controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p8h61-m_lx/dsdt.asl b/src/mainboard/asus/p8h61-m_lx/dsdt.asl new file mode 100644 index 0000000..60cbde3 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/dsdt.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, /* DSDT Revision: ACPI v3.0 */ + "COREv4", /* OEM ID */ + "COREBOOT", /* OEM Table ID */ + 0x20171231 /* OEM Revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) + { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads b/src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads new file mode 100644 index 0000000..652fa3f --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads @@ -0,0 +1,29 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8h61-m_lx/gpio.c b/src/mainboard/asus/p8h61-m_lx/gpio.c new file mode 100644 index 0000000..2a66322 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/gpio.c @@ -0,0 +1,140 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio31 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8h61-m_lx/hda_verb.c b/src/mainboard/asus/p8h61-m_lx/hda_verb.c new file mode 100644 index 0000000..fb56759 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/hda_verb.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Realtek ALC887-VD */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of entries */ + AZALIA_SUBVENDOR(0x0, 0x10438445), + AZALIA_PIN_CFG(0x0, 0x11, 0x99430130), + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0x0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c50), + AZALIA_PIN_CFG(0x0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8h61-m_lx/mainboard.c b/src/mainboard/asus/p8h61-m_lx/mainboard.c new file mode 100644 index 0000000..54176c4 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/mainboard.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/p8h61-m_lx/romstage.c b/src/mainboard/asus/p8h61-m_lx/romstage.c new file mode 100644 index 0000000..76fc8aa --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx/romstage.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/pci_ops.h> +#include <device/dram/ddr3.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void pch_enable_lpc(void) +{ + pci_or_config16(PCH_LPC_DEV, LPC_EN, + CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); +} + +void mainboard_rcba_config(void) +{ +} + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} -- To view, visit https://review.coreboot.org/27798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2a0579f486d3a44de2dd927fa1e76b90c3b48f62 Gerrit-Change-Number: 27798 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: superio/acpi: Make _CRS methods Serialized, eliminating IASL remarks
by Tristan Corrick (Code Review) 02 Aug '18

02 Aug '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/27796 Change subject: superio/acpi: Make _CRS methods Serialized, eliminating IASL remarks ...................................................................... superio/acpi: Make _CRS methods Serialized, eliminating IASL remarks When compiling for the ASUS P8H61-M LX, IASL 20180531 emitted the following remark: "Control Method should be made Serialized (due to creation of named objects within)". Making the appropriate methods Serialized eliminates these remarks. Change-Id: I8e95d9a00a629a2f904c79b78fac20810327ed37 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/superio/acpi/pnp_generic.asl M src/superio/acpi/pnp_kbc.asl M src/superio/acpi/pnp_uart.asl 3 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/27796/1 diff --git a/src/superio/acpi/pnp_generic.asl b/src/superio/acpi/pnp_generic.asl index c878827..980404e 100644 --- a/src/superio/acpi/pnp_generic.asl +++ b/src/superio/acpi/pnp_generic.asl @@ -95,7 +95,7 @@ } #endif - Method (_CRS) + Method (_CRS, 0, Serialized) { Name (CRS, ResourceTemplate () { #ifdef SUPERIO_PNP_IO0 diff --git a/src/superio/acpi/pnp_kbc.asl b/src/superio/acpi/pnp_kbc.asl index db81ea2..cbcfd55 100644 --- a/src/superio/acpi/pnp_kbc.asl +++ b/src/superio/acpi/pnp_kbc.asl @@ -73,7 +73,7 @@ PNP_DEFAULT_PSC } - Method (_CRS) + Method (_CRS, 0, Serialized) { Name (CRS, ResourceTemplate () { IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) @@ -133,7 +133,7 @@ Return (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._PSC ()) } - Method (_CRS) + Method (_CRS, 0, Serialized) { Name (CRS, ResourceTemplate () { IRQNoFlags (IR1) {} @@ -188,7 +188,7 @@ PNP_DEFAULT_PSC } - Method (_CRS) + Method (_CRS, 0, Serialized) { Name (CRS, ResourceTemplate () { IRQNoFlags (IR1) {} diff --git a/src/superio/acpi/pnp_uart.asl b/src/superio/acpi/pnp_uart.asl index 1bbdb37..f42cc42 100644 --- a/src/superio/acpi/pnp_uart.asl +++ b/src/superio/acpi/pnp_uart.asl @@ -79,7 +79,7 @@ } #endif - Method (_CRS) + Method (_CRS, 0, Serialized) { Name (CRS, ResourceTemplate () { IO (Decode16, 0x0000, 0x0000, 0x08, 0x08, IO0) -- To view, visit https://review.coreboot.org/27796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8e95d9a00a629a2f904c79b78fac20810327ed37 Gerrit-Change-Number: 27796 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: superio/nuvoton/nct6776/acpi: Add parallel port support
by Tristan Corrick (Code Review) 02 Aug '18

02 Aug '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/27795 Change subject: superio/nuvoton/nct6776/acpi: Add parallel port support ...................................................................... superio/nuvoton/nct6776/acpi: Add parallel port support Exposing the parallel port via ACPI causes Linux to automatically detect the parallel port and load the appropriate modules. Tested on an ASUS P8H61-M LX with Linux 4.9.110 and 4.17.8. However, no parallel port device has been tested. Change-Id: I2529a074e24433d093ad0650a45c7b29238620f3 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/superio/nuvoton/nct6776/acpi/superio.asl 1 file changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/27795/1 diff --git a/src/superio/nuvoton/nct6776/acpi/superio.asl b/src/superio/nuvoton/nct6776/acpi/superio.asl index b985115..980eab9 100644 --- a/src/superio/nuvoton/nct6776/acpi/superio.asl +++ b/src/superio/nuvoton/nct6776/acpi/superio.asl @@ -23,6 +23,7 @@ * devices, disabling and reenabling logical devices. * * LDN State + * 0x1 PP Implemented, untested * 0x2 SP1 Implemented, untested * 0x5 KBC Implemented, untested * 0x8 GPIO Implemented, untested @@ -31,6 +32,7 @@ * Controllable through preprocessor defines: * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * NCT6776_SHOW_PP If defined, the parallel port will be exposed. * NCT6776_SHOW_SP1 If defined, Serial Port 1 will be exposed. * NCT6776_SHOW_KBC If defined, the Keyboard Controller will be exposed. * NCT6776_SHOW_GPIO If defined, GPIO support will be exposed. @@ -85,6 +87,8 @@ PNP_IRQ0, 8, /* First IRQ */ Offset (0x72), PNP_IRQ1, 8, /* Second IRQ */ + Offset (0x74), + PNP_DMA0, 8, /* DRQ */ } Method (_CRS) @@ -107,6 +111,32 @@ #define PNP_EXIT_MAGIC_1ST 0xaa #include <superio/acpi/pnp_config.asl> +#ifdef NCT6776_SHOW_PP + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + /* + * The extra code required to dynamically reflect ECP in the HID + * isn't currently justified, so the HID is hardcoded as not + * using ECP. "PNP0401" would indicate ECP. + */ + #define SUPERIO_PNP_HID "PNP0400" + #define SUPERIO_PNP_LDN 1 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IRQ0 + #define SUPERIO_PNP_DMA + #include <superio/acpi/pnp_generic.asl> +#endif + #ifdef NCT6776_SHOW_SP1 #undef SUPERIO_UART_LDN #undef SUPERIO_UART_DDN -- To view, visit https://review.coreboot.org/27795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2529a074e24433d093ad0650a45c7b29238620f3 Gerrit-Change-Number: 27795 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: superio/nuvoton/nct6776/acpi: Fix typo in comments
by Tristan Corrick (Code Review) 02 Aug '18

02 Aug '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/27794 Change subject: superio/nuvoton/nct6776/acpi: Fix typo in comments ...................................................................... superio/nuvoton/nct6776/acpi: Fix typo in comments The constant used in the ACPI code is NCT6776_SHOW_KBC, so update the comments to reflect that. Change-Id: I9ba69384866088f84a516557d76864104a024968 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/superio/nuvoton/nct6776/acpi/superio.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/27794/1 diff --git a/src/superio/nuvoton/nct6776/acpi/superio.asl b/src/superio/nuvoton/nct6776/acpi/superio.asl index 8e892e8..b985115 100644 --- a/src/superio/nuvoton/nct6776/acpi/superio.asl +++ b/src/superio/nuvoton/nct6776/acpi/superio.asl @@ -24,7 +24,7 @@ * * LDN State * 0x2 SP1 Implemented, untested - * 0x5 KBCK Implemented, untested + * 0x5 KBC Implemented, untested * 0x8 GPIO Implemented, untested * 0xb HWM Implemented, untested * @@ -32,7 +32,7 @@ * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) * SUPERIO_PNP_BASE I/O address of the first PnP configuration register * NCT6776_SHOW_SP1 If defined, Serial Port 1 will be exposed. - * NCT6776_SHOW_KBCK If defined, the Keyboard Controller will be exposed. + * NCT6776_SHOW_KBC If defined, the Keyboard Controller will be exposed. * NCT6776_SHOW_GPIO If defined, GPIO support will be exposed. * NCT6776_SHOW_HWM If defined, the Environment Controller will be exposed. */ -- To view, visit https://review.coreboot.org/27794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9ba69384866088f84a516557d76864104a024968 Gerrit-Change-Number: 27794 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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coreboot-gerrit August 2018