coreboot-gerrit August 2018

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Change in coreboot[master]: mb/supermicro/h8qme_fam10: Use common pnp_{enter, exit} functions
by Elyes HAOUAS (Code Review) 06 Aug '18

06 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27866 Change subject: mb/supermicro/h8qme_fam10: Use common pnp_{enter,exit} functions ...................................................................... mb/supermicro/h8qme_fam10: Use common pnp_{enter,exit} functions Change-Id: Ie3ee4acfd272991133f02a56df6e23aa6071d3e9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/supermicro/h8qme_fam10/romstage.c 1 file changed, 6 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/27866/1 diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index f5222ed..ddbb97c 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -120,23 +120,9 @@ #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3) -/* TODO: superio code should really not be in mainboard */ -static void pnp_enter_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - static void write_GPIO(void) { - pnp_enter_ext_func_mode(GPIO1_DEV); + pnp_enter_conf_state(GPIO1_DEV); pnp_set_logical_device(GPIO1_DEV); pnp_write_config(GPIO1_DEV, 0x30, 0x01); pnp_write_config(GPIO1_DEV, 0x60, 0x00); @@ -147,9 +133,9 @@ pnp_write_config(GPIO1_DEV, 0xf0, 0xff); pnp_write_config(GPIO1_DEV, 0xf1, 0xff); pnp_write_config(GPIO1_DEV, 0xf2, 0x00); - pnp_exit_ext_func_mode(GPIO1_DEV); + pnp_exit_conf_state(GPIO1_DEV); - pnp_enter_ext_func_mode(GPIO2_DEV); + pnp_enter_conf_state(GPIO2_DEV); pnp_set_logical_device(GPIO2_DEV); pnp_write_config(GPIO2_DEV, 0x30, 0x01); pnp_write_config(GPIO2_DEV, 0xf0, 0xef); @@ -159,16 +145,16 @@ pnp_write_config(GPIO2_DEV, 0xf5, 0x48); pnp_write_config(GPIO2_DEV, 0xf6, 0x00); pnp_write_config(GPIO2_DEV, 0xf7, 0xc0); - pnp_exit_ext_func_mode(GPIO2_DEV); + pnp_exit_conf_state(GPIO2_DEV); - pnp_enter_ext_func_mode(GPIO3_DEV); + pnp_enter_conf_state(GPIO3_DEV); pnp_set_logical_device(GPIO3_DEV); pnp_write_config(GPIO3_DEV, 0x30, 0x00); pnp_write_config(GPIO3_DEV, 0xf0, 0xff); pnp_write_config(GPIO3_DEV, 0xf1, 0xff); pnp_write_config(GPIO3_DEV, 0xf2, 0xff); pnp_write_config(GPIO3_DEV, 0xf3, 0x40); - pnp_exit_ext_func_mode(GPIO3_DEV); + pnp_exit_conf_state(GPIO3_DEV); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -- To view, visit https://review.coreboot.org/27866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie3ee4acfd272991133f02a56df6e23aa6071d3e9 Gerrit-Change-Number: 27866 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/kontron/986lcd-m: Use common pnp_{enter, exit} functions
by Elyes HAOUAS (Code Review) 06 Aug '18

06 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27865 to look at the new patch set (#2). Change subject: mb/kontron/986lcd-m: Use common pnp_{enter,exit} functions ...................................................................... mb/kontron/986lcd-m: Use common pnp_{enter,exit} functions Some unneeded includes are also removed. Change-Id: Icd518c46d8503d11d24466c30840d7e514e9a05d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/kontron/986lcd-m/romstage.c 1 file changed, 13 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/27865/2 -- To view, visit https://review.coreboot.org/27865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icd518c46d8503d11d24466c30840d7e514e9a05d Gerrit-Change-Number: 27865 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/kontron/986lcd-m: Use common pnp_{enter, exit} functions
by Elyes HAOUAS (Code Review) 06 Aug '18

06 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27865 Change subject: mb/kontron/986lcd-m: Use common pnp_{enter,exit} functions ...................................................................... mb/kontron/986lcd-m: Use common pnp_{enter,exit} functions Some unneeded includes are also removed. Change-Id: Icd518c46d8503d11d24466c30840d7e514e9a05d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/kontron/986lcd-m/romstage.c 1 file changed, 13 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/27865/1 diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index f7e8131..5996045 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -16,25 +16,21 @@ /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include <stdint.h> -#include <string.h> -#include <lib.h> -#include <arch/acpi.h> -#include <cbmem.h> +#include <halt.h> #include <timestamp.h> -#include <arch/io.h> +#include <console/console.h> +#include <cpu/intel/romstage.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> #include <device/pci_def.h> #include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include "option_table.h" -#include <console/console.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <halt.h> -#include <superio/winbond/w83627thg/w83627thg.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627thg/w83627thg.h> + +#include "option_table.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) @@ -62,20 +58,6 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301); } -/* TODO: superio code should really not be in mainboard */ -static void pnp_enter_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - /* This box has two superios, so enabling serial becomes slightly excessive. * We disable a lot of stuff to make sure that there are no conflicts between * the two. Also set up the GPIOs from the beginning. This is the "no schematic @@ -86,7 +68,7 @@ pnp_devfn_t dev; dev = PNP_DEV(0x2e, W83627THG_SP1); - pnp_enter_func_mode(dev); + pnp_enter_conf_state(dev); pnp_write_config(dev, 0x24, 0xc6); /* PNPCSV */ @@ -146,10 +128,10 @@ pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); pnp_set_enable(dev, 1); - pnp_exit_func_mode(dev); + pnp_exit_conf_state(dev); dev = PNP_DEV(0x4e, W83627THG_SP1); - pnp_enter_func_mode(dev); + pnp_enter_conf_state(dev); pnp_set_logical_device(dev); /* Set COM3 to sane non-conflicting values */ pnp_set_enable(dev, 0); @@ -178,7 +160,7 @@ pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); - pnp_exit_func_mode(dev); + pnp_exit_conf_state(dev); } static void rcba_config(void) -- To view, visit https://review.coreboot.org/27865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icd518c46d8503d11d24466c30840d7e514e9a05d Gerrit-Change-Number: 27865 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/soc/intel: Add AML IGD in platform reporting
by Patrick Georgi (Code Review) 06 Aug '18

06 Aug '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27846 ) Change subject: src/soc/intel: Add AML IGD in platform reporting ...................................................................... src/soc/intel: Add AML IGD in platform reporting This patch revises IGD naming and adds AML IGD in platform reporting. BUG=None BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage & Ensure AML IGD is shown in platform reporting. Change-Id: Id8f8379703abdaa5b14a4337a4fca04b370f3a2a Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> Reviewed-on: https://review.coreboot.org/27846 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/vr_config.c 4 files changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 7a26667..b3a8c57 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2868,7 +2868,7 @@ #define PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM 0x5916 #define PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR 0x5917 #define PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM 0x591B -#define PCI_DEVICE_ID_INTEL_KBL_GT2_ULX_R 0x591C +#define PCI_DEVICE_ID_INTEL_AML_GT2_ULX 0x591C #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_505 0x5a84 #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_500 0x5a85 #define PCI_DEVICE_ID_INTEL_GLK_IGD 0x3184 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 1c31d73..c6ea7e2 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -124,7 +124,7 @@ PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR, PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, - PCI_DEVICE_ID_INTEL_KBL_GT2_ULX_R, + PCI_DEVICE_ID_INTEL_AML_GT2_ULX, PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM, PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM, PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM, diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 7d5bc3f..a652b52 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -102,6 +102,7 @@ { PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR, "Kabylake-R ULT GT2"}, { PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, "Kabylake HALO GT2" }, { PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, "Kabylake DT GT2" }, + { PCI_DEVICE_ID_INTEL_AML_GT2_ULX, "Amberlake ULX GT2" }, }; static uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index ce40e35..4508fda 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -186,7 +186,7 @@ sku = KBL_R_SKU; else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_Y) { id = get_dev_id(SA_DEV_IGD); - if (id == PCI_DEVICE_ID_INTEL_KBL_GT2_ULX_R) + if (id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) sku = AML_Y_SKU; else sku = KBL_Y_SKU; -- To view, visit https://review.coreboot.org/27846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Id8f8379703abdaa5b14a4337a4fca04b370f3a2a Gerrit-Change-Number: 27846 Gerrit-PatchSet: 2 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge: Enable spread spectrum in bootblock
by Patrick Georgi (Code Review) 06 Aug '18

06 Aug '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27813 ) Change subject: soc/amd/stoneyridge: Enable spread spectrum in bootblock ...................................................................... soc/amd/stoneyridge: Enable spread spectrum in bootblock setup_spread_spectrum is called in early_init, meaning the console is not initialized yet. So you won't see boot block booting twice. BUG=b:111610455 TEST=booted grunt and verified that AmdInitReset does not reboot. I had AGESA patched to skip the JTAG check. Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Reviewed-on: https://review.coreboot.org/27813 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 89 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 15c9581..64b4b46 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -367,6 +367,28 @@ #define GPP_CLK0_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT) #define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 1 +/* Bit definitions for MISC_MMIO_BASE register MiscClkCntl1 */ +#define MISC_CGPLL_CONFIG1 0x08 +#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) +#define MISC_CGPLL_CONFIG3 0x10 +#define CG1PLL_REFDIV_SHIFT 0 +#define CG1PLL_REFDIV_MASK (0x3FF << CG1PLL_REFDIV_SHIFT) +#define CG1PLL_FBDIV_SHIFT 10 +#define CG1PLL_FBDIV_MASK (0xFFF << CG1PLL_FBDIV_SHIFT) +#define MISC_CGPLL_CONFIG4 0x14 +#define CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT 0 +#define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xFFFF << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) +#define CG1PLL_SS_AMOUNT_DSFRAC_SHIFT 16 +#define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xFFFF << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) +#define MISC_CGPLL_CONFIG5 0x18 +#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT 8 +#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xF << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) +#define MISC_CGPLL_CONFIG6 0x1C +#define CG1PLL_LF_MODE_SHIFT 9 +#define CG1PLL_LF_MODE_MASK (0x1FF << CG1PLL_LF_MODE_SHIFT) +#define MISC_CLK_CNTL1 0x40 +#define CG1PLL_FBDIV_TEST BIT(26) + struct stoneyridge_aoac { int enable; int status; @@ -404,6 +426,8 @@ void pm_write8(u8 reg, u8 value); void pm_write16(u8 reg, u16 value); void pm_write32(u8 reg, u32 value); +u32 misc_read32(u8 reg); +void misc_write32(u8 reg, u32 value); uint8_t smi_read8(uint8_t offset); uint16_t smi_read16(uint8_t offset); uint32_t smi_read32(uint8_t offset); diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index 26c86e8..9daf0bb 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -36,6 +36,16 @@ return read16((void *)(PM_MMIO_BASE + reg)); } +void misc_write32(u8 reg, u32 value) +{ + write32((void *)(MISC_MMIO_BASE + reg), value); +} + +u32 misc_read32(u8 reg) +{ + return read32((void *)(MISC_MMIO_BASE + reg)); +} + void pm_write32(u8 reg, u32 value) { write32((void *)(PM_MMIO_BASE + reg), value); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index f098c1c..348d5f1 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -33,6 +33,7 @@ #include <soc/pci_devs.h> #include <agesa_headers.h> #include <soc/nvs.h> +#include <reset.h> /* * Table of devices that need their AOAC registers enabled and waited @@ -555,6 +556,59 @@ } } +static void setup_spread_spectrum(void) +{ + uint16_t rstcfg = pm_read16(PWR_RESET_CFG); + + rstcfg &= ~TOGGLE_ALL_PWR_GOOD; + pm_write16(PWR_RESET_CFG, rstcfg); + + uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1); + + if (cntl1 & CG1PLL_FBDIV_TEST) { + printk(BIOS_DEBUG, "Spread spectrum is ready\n"); + misc_write32(MISC_CGPLL_CONFIG1, + misc_read32(MISC_CGPLL_CONFIG1) | + CG1PLL_SPREAD_SPECTRUM_ENABLE); + + return; + } + + printk(BIOS_DEBUG, "Setting up spread spectrum\n"); + + uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6); + cfg6 &= ~CG1PLL_LF_MODE_MASK; + cfg6 |= (0x0F8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK; + misc_write32(MISC_CGPLL_CONFIG6, cfg6); + + uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3); + cfg3 &= ~CG1PLL_REFDIV_MASK; + cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK; + cfg3 &= ~CG1PLL_FBDIV_MASK; + cfg3 |= (0x04B << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK; + misc_write32(MISC_CGPLL_CONFIG3, cfg3); + + uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5); + cfg5 &= ~CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK; + cfg5 |= (0x2 << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) & CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK; + misc_write32(MISC_CGPLL_CONFIG5, cfg5); + + uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4); + cfg4 &= ~CG1PLL_SS_AMOUNT_DSFRAC_MASK; + cfg4 |= (0xD000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK; + cfg4 &= ~CG1PLL_SS_STEP_SIZE_DSFRAC_MASK; + cfg4 |= (0x02D5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK; + misc_write32(MISC_CGPLL_CONFIG4, cfg4); + + rstcfg |= TOGGLE_ALL_PWR_GOOD; + pm_write16(PWR_RESET_CFG, rstcfg); + + cntl1 |= CG1PLL_FBDIV_TEST; + misc_write32(MISC_CLK_CNTL1, cntl1); + + soft_reset(); +} + void bootblock_fch_early_init(void) { sb_enable_rom(); @@ -565,6 +619,7 @@ sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ sb_acpi_mmio_decode(); sb_enable_cf9_io(); + setup_spread_spectrum(); sb_enable_legacy_io(); enable_aoac_devices(); } -- To view, visit https://review.coreboot.org/27813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 Gerrit-Change-Number: 27813 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: exception: Fix segment error code mask
by Patrick Georgi (Code Review) 06 Aug '18

06 Aug '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27812 ) Change subject: exception: Fix segment error code mask ...................................................................... exception: Fix segment error code mask The segment error descriptor is actually 13 bits long. BUG=b:109749762 TEST=Verified by causing a segment error Change-Id: I3439f9ce1e8cf0c472c4eb82d74a787718c9609f Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Reviewed-on: https://review.coreboot.org/27812 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M payloads/libpayload/arch/x86/exception.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/payloads/libpayload/arch/x86/exception.c b/payloads/libpayload/arch/x86/exception.c index f6bb8c9..b562660 100644 --- a/payloads/libpayload/arch/x86/exception.c +++ b/payloads/libpayload/arch/x86/exception.c @@ -59,7 +59,7 @@ static void print_segment_error_code(u32 code) { - printf("%#x - descriptor %#x in the ", code, (code >> 3) & 0x1f); + printf("%#x - descriptor %#x in the ", code, (code >> 3) & 0x1FFF); if (code & (0x1 << 1)) { printf("IDT"); } else { -- To view, visit https://review.coreboot.org/27812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I3439f9ce1e8cf0c472c4eb82d74a787718c9609f Gerrit-Change-Number: 27812 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variants/rammus: add rammus devicetree.cb
by Patrick Georgi (Code Review) 06 Aug '18

06 Aug '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27808 ) Change subject: mb/google/poppy/variants/rammus: add rammus devicetree.cb ...................................................................... mb/google/poppy/variants/rammus: add rammus devicetree.cb Use the default value for Iccmax which is specified in vr_config.c. The AcLoadline and DcLoadline keep the poppy value. Besides, the USB 2.0 ports located on the mainboard are set to USB2_PORT_SHORT and the others on the daughterboard are set to USB2_PORT_LONG. Those setting need to be fine tuned later. BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: Icabfac04c94b3d480872c243d811509e274ef122 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-on: https://review.coreboot.org/27808 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/Kconfig A src/mainboard/google/poppy/variants/rammus/devicetree.cb 2 files changed, 337 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 2ca0f96..fc090df 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -30,6 +30,7 @@ default "variants/nami/devicetree.cb" if BOARD_GOOGLE_NAMI default "variants/nautilus/devicetree.cb" if BOARD_GOOGLE_NAUTILUS default "variants/nocturne/devicetree.cb" if BOARD_GOOGLE_NOCTURNE + default "variants/rammus/devicetree.cb" if BOARD_GOOGLE_RAMMUS default "variants/soraka/devicetree.cb" if BOARD_GOOGLE_SORAKA default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb new file mode 100644 index 0000000..78de3ca --- /dev/null +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -0,0 +1,336 @@ +chip soc/intel/skylake + + # Deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable S0ix + register "s0ix_enable" = "1" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "1" + register "SaImguEnable" = "1" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "2" + register "PttSwitch" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" + register "VmxEnable" = "1" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 2A | 2A | 2A | 2A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 | + #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 1500, + .dc_loadline = 1430, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 570, + .dc_loadline = 483, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 550, + .dc_loadline = 420, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 550, + .dc_loadline = 420, + }" + + # Enable Root port 1. + register "PcieRpEnable[0]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[0]" = "1" + # RP 1 uses SRCCLKREQ1# + register "PcieRpClkReqNumber[0]" = "1" + # RP 1 uses uses CLK SRC 1 + register "PcieRpClkSrcNumber[0]" = "1" + # RP 1, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[0]" = "1" + # RP 1, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[0]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC0)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-A Port + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1 + register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| I2C0 | Touchscreen | + #| I2C1 | Trackpad | + #| I2C5 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 36, + }, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 36, + }, + .early_init = 1, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 36, + }, + }, + }" + + # Touchscreen + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" + + # Trackpad + register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" + + # Audio + register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSpi0] = PchSerialIoPci, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + register "speed_shift_enable" = "1" + register "psys_pmax" = "45" + # PL2 override 18W for AML-Y + register "tdp_pl2_override" = "18" + register "tcc_offset" = "10" # TCC of 90C + + # Use default SD card detect GPIO configuration + register "sdcard_cd_gpio_default" = "GPP_E15" + + # PCH Trip Temperature in degree C + register "pch_trip_temp" = "75" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_05" # GPP_B5 + device i2c 15 on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 off end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on + chip drivers/i2c/max98927 + register "interleave_mode" = "1" + register "vmon_slot_no" = "4" + register "imon_slot_no" = "5" + register "uid" = "0" + register "desc" = ""SSM4567 Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 39 on end + end + chip drivers/i2c/max98927 + register "interleave_mode" = "1" + register "vmon_slot_no" = "6" + register "imon_slot_no" = "7" + register "uid" = "1" + register "desc" = ""SSM4567 Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 3A on end + end + end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW0_00" # GPP_B0 + device pci 00.0 on end + end + end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" + device spi 0 on end + end + end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 on end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 on end # SDCard + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end -- To view, visit https://review.coreboot.org/27808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Icabfac04c94b3d480872c243d811509e274ef122 Gerrit-Change-Number: 27808 Gerrit-PatchSet: 3 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variants/rammus: add gpio setting
by Patrick Georgi (Code Review) 06 Aug '18

06 Aug '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27807 ) Change subject: mb/google/poppy/variants/rammus: add gpio setting ...................................................................... mb/google/poppy/variants/rammus: add gpio setting The gpio setting is based on the proto board schematics BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: I20fc081d372b8686f6128a7e85276f9c6798b199 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-on: https://review.coreboot.org/27807 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/rammus/Makefile.inc A src/mainboard/google/poppy/variants/rammus/gpio.c 2 files changed, 391 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/rammus/Makefile.inc b/src/mainboard/google/poppy/variants/rammus/Makefile.inc index edfacea..eed7c44 100644 --- a/src/mainboard/google/poppy/variants/rammus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/rammus/Makefile.inc @@ -1,5 +1,8 @@ SPD_SOURCES = empty # 0b0000 +bootblock-y += gpio.c + romstage-y += memory.c +ramstage-y += gpio.c ramstage-y += nhlt.c diff --git a/src/mainboard/google/poppy/variants/rammus/gpio.c b/src/mainboard/google/poppy/variants/rammus/gpio.c new file mode 100644 index 0000000..771a3f4 --- /dev/null +++ b/src/mainboard/google/poppy/variants/rammus/gpio.c @@ -0,0 +1,388 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { + /* A0 : RCIN# ==> NC(T0804) */ + PAD_CFG_NC(GPP_A0), + /* A1 : ESPI_IO0 */ + /* A2 : ESPI_IO1 */ + /* A3 : ESPI_IO2 */ + /* A4 : ESPI_IO3 */ + /* A5 : ESPI_CS# */ + /* A6 : SERIRQ ==> NC(T0805) */ + PAD_CFG_NC(GPP_A6), + /* A7 : PIRQA# ==> NC(T0501) */ + PAD_CFG_NC(GPP_A7), + /* A8 : CLKRUN# ==> NC(T0806) */ + PAD_CFG_NC(GPP_A8), + /* A9 : ESPI_CLK */ + /* A10 : CLKOUT_LPC1 ==> NC */ + PAD_CFG_NC(GPP_A10), + /* A11 : PME# ==> NC(T0913) */ + PAD_CFG_NC(GPP_A11), + /* A12 : BM_BUSY# ==> NC */ + PAD_CFG_NC(GPP_A12), + /* A13 : SUSWARN# ==> SUSWARN_L */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + /* A14 : ESPI_RESET# */ + /* A15 : SUSACK# ==> SUSACK_L */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : SD_1P8_SEL ==> SD_PWR_1800_SEL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */ + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + /* A18 : ISH_GP0 ==> NC */ + PAD_CFG_NC(GPP_A18), + /* A19 : ISH_GP1 ==> NC */ + PAD_CFG_NC(GPP_A19), + /* A20 : ISH_GP2 ==> NC */ + PAD_CFG_NC(GPP_A20), + /* A21 : ISH_GP3 ==> NC */ + PAD_CFG_NC(GPP_A21), + /* A22 : ISH_GP4 ==> NC */ + PAD_CFG_NC(GPP_A22), + /* A23 : ISH_GP5 ==> NC */ + PAD_CFG_NC(GPP_A23), + + /* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */ + PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT), + /* B1 : CORE_VID1 ==> NC */ + PAD_CFG_NC(GPP_B1), + /* B2 : VRALERT# ==> NC */ + PAD_CFG_NC(GPP_B2), + /* B3 : CPU_GP2 ==> TRACKPAD_INT_L */ + PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), + /* B4 : CPU_GP3 ==> NC */ + PAD_CFG_NC(GPP_B4), + /* B5 : SRCCLKREQ0# ==> TRACKPAD_INT_L for wakeup event */ + PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, INVERT), + /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : SRCCLKREQ2# ==> NC */ + PAD_CFG_NC(GPP_B7), + /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ + PAD_CFG_GPO(GPP_B8, 0, DEEP), + /* B9 : SRCCLKREQ4# ==> NC */ + PAD_CFG_NC(GPP_B9), + /* B10 : SRCCLKREQ5# ==> NC */ + PAD_CFG_NC(GPP_B10), + /* B11 : EXT_PWR_GATE# ==> NC */ + PAD_CFG_NC(GPP_B11), + /* B12 : SLP_S0# ==> SLP_S0_L_G */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST_L_PCH */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR ==> NC */ + PAD_CFG_NC(GPP_B14), + /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* B19 : GSPI1_CS# ==> NC(T0807) */ + PAD_CFG_NC(GPP_B19), + /* B20 : GSPI1_CLK ==> NC(T0808) */ + PAD_CFG_NC(GPP_B20), + /* B21 : GSPI1_MISO ==> NC(T0809) */ + PAD_CFG_NC(GPP_B21), + /* B22 : GSPI1_MOSI ==> NC(T0810) */ + PAD_CFG_NC(GPP_B22), + /* B23 : SM1ALERT# ==> NC */ + PAD_CFG_NC(GPP_B23), + + /* C0 : SMBCLK ==> SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA ==> SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C2 : SMBALERT# ==> NC */ + PAD_CFG_NC(GPP_C2), + /* C3 : SML0CLK ==> NC */ + PAD_CFG_NC(GPP_C3), + /* C4 : SML0DATA ==> NC */ + PAD_CFG_NC(GPP_C4), + /* C5 : SML0ALERT# ==> NC */ + PAD_CFG_NC(GPP_C5), + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + /* C7 : SM1DATA ==> NC */ + PAD_CFG_NC(GPP_C7), + /* C8 : UART0_RXD ==> NC(BT_OFF#) */ + PAD_CFG_NC(GPP_C8), + /* C9 : UART0_TXD ==> NC(WLAN_OFF#) */ + PAD_CFG_NC(GPP_C9), + /* C10 : UART0_RTS# ==> NC(T0817) */ + PAD_CFG_NC(GPP_C10), + /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), + /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), + /* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), + /* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TRACKPAD_3V3_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TRACKPAD_3V3_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> PCH_WP */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + + /* D0 : SPI1_CS# ==> NC */ + PAD_CFG_NC(GPP_D0), + /* D1 : SPI1_CLK ==> NC(T0818) */ + PAD_CFG_NC(GPP_D1), + /* D2 : SPI1_MISO ==> NC(T0819) */ + PAD_CFG_NC(GPP_D2), + /* D3 : SPI1_MOSI ==> NC(T0820) */ + PAD_CFG_NC(GPP_D3), + /* D4 : FASHTRIG ==> NC */ + PAD_CFG_NC(GPP_D4), + /* D5 : ISH_I2C0_SDA ==> NC */ + PAD_CFG_NC(GPP_D5), + /* D6 : ISH_I2C0_SCL ==> NC */ + PAD_CFG_NC(GPP_D6), + /* D7 : ISH_I2C1_SDA ==> NC */ + PAD_CFG_NC(GPP_D7), + /* D8 : ISH_I2C1_SCL ==> NC(T0815) */ + PAD_CFG_NC(GPP_D8), + /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ + PAD_CFG_GPI_APIC(GPP_D9, 20K_PU, DEEP), + /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */ + PAD_CFG_GPO(GPP_D10, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> SPKR_IRQ_L */ + PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), + /* D12 : ISH_SPI_MOSI ==> NC(T0816) */ + PAD_CFG_NC(GPP_D12), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_CFG_NC(GPP_D13), + /* D14 : ISH_UART0_TXD ==> NC */ + PAD_CFG_NC(GPP_D14), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_CFG_NC(GPP_D15), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_CFG_NC(GPP_D16), + /* D17 : ISH_UART0_CTS# ==> DMIC_CLK1_PCH */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* D18 : DMIC_DATA1 ==> NC(T0703) */ + PAD_CFG_NC(GPP_D18), + /* D19 : DMIC_CLK0 ==> DMIC_CLK0_PCH */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* D20 : DMIC_DATA0 ==> DMIC_DATA0_PCH */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* D21 : SPI1_IO2 ==> NC */ + PAD_CFG_NC(GPP_D21), + /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */ + PAD_CFG_GPO(GPP_D22, 1, DEEP), + /* D23 : I2S_MCLK ==> I2S_MCLK */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + + /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + /* E1 : SATAXPCIE1 ==> NC */ + PAD_CFG_NC(GPP_E1), + /* E2 : SATAXPCIE2 ==> NC */ + PAD_CFG_NC(GPP_E2), + /* E3 : CPU_GP0 ==> NC */ + PAD_CFG_NC(GPP_E3), + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_CFG_NC(GPP_E4), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_CFG_NC(GPP_E5), + /* E6 : SATA_DEVSLP2 ==> NC */ + PAD_CFG_NC(GPP_E6), + /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + /* E8 : SATALED# ==> NC */ + PAD_CFG_NC(GPP_E8), + /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + /* E11 : USB2_OC2# ==> NC(T0504) */ + PAD_CFG_NC(GPP_E11), + /* E12 : USB2_OC3# ==> USB_A0_OC# */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + /* E15 : DDPD_HPD2 ==> SD_CD_ODL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP), + /* E16 : DDPE_HPD3 ==> NC(T0602) */ + PAD_CFG_NC(GPP_E16), + /* E17 : EDP_HPD ==> EDP_HPD */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + /* E18 : DDPB_CTRLCLK ==> NC */ + PAD_CFG_NC(GPP_E18), + /* E19 : DDPB_CTRLDATA ==> NC */ + PAD_CFG_NC(GPP_E19), + /* E20 : DDPC_CTRLCLK ==> NC */ + PAD_CFG_NC(GPP_E20), + /* E21 : DDPC_CTRLDATA ==> NC */ + PAD_CFG_NC(GPP_E21), + /* E22 : DDPD_CTRLCLK ==> NC */ + PAD_CFG_NC(GPP_E22), + /* E23 : DDPD_CTRLDATA ==> NC*/ + PAD_CFG_NC(GPP_E23), + + /* The next 4 pads are for bit banging the amplifiers, default to I2S */ + /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), + /* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), + /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), + /* F3 : I2S2_RXD ==> NC */ + PAD_CFG_NC(GPP_F3), + /* F4 : I2C2_SDA ==> I2C_2_SDA */ + PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), + /* F5 : I2C2_SCL ==> I2C_2_SCL */ + PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), + /* F6 : I2C3_SDA ==> PCH_I2C3_PEN_1V8_SDA */ + PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), + /* F7 : I2C3_SCL ==> PCH_I2C3_PEN_1V8_SCL */ + PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), + /* F8 : I2C4_SDA ==> PCH_I2C4_H1_1V8_SDA */ + PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), + /* F9 : I2C4_SCL ==> PCH_I2C4_H1_1V8_SCL */ + PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), + /* F10 : I2C5_SDA ==> PCH_I2C5_AUDIO_1V8_SDA */ + PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), + /* F11 : I2C5_SCL ==> PCH_I2C5_AUDIO_1V8_SCL */ + PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA0 ==> EMMC_DAT0 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA1 ==> EMMC_DAT1 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA2 ==> EMMC_DAT2 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA3 ==> EMMC_DAT3 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA4 ==> EMMC_DAT4 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA5 ==> EMMC_DAT5 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA6 ==> EMMC_DAT6 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_DATA7 ==> EMMC_DAT7 */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : RSVD ==> NC */ + PAD_CFG_NC(GPP_F23), + + /* G0 : SD_CMD ==> SD_CMD */ + PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + /* G1 : SD_DATA0 ==> SD_DATA0 */ + PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + /* G2 : SD_DATA1 ==> SD_DATA1 */ + PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + /* G3 : SD_DATA2 ==> SD_DATA2 */ + PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + /* G4 : SD_DATA3 ==> SD_DATA3 */ + PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + /* G5 : SD_CD# ==> SD_CD_ODL */ + PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), + /* G6 : SD_CLK ==> SD_CLK */ + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), + /* G7 : SD_WP ==> NC(T0701) */ + PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + + /* GPD0: BATLOW# ==> PCH_BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ + PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + /* GPD4: SLP_S3# ==> SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SLP_S4# ==> SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SLP_A# ==> NC(T0912) */ + PAD_CFG_NC(GPD6), + /* GPD7: RSVD ==> NC */ + PAD_CFG_NC(GPD7), + /* GPD8: SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SLP_WLAN# ==> NC(T0911) */ + PAD_CFG_NC(GPD9), + /* GPD10: SLP_S5# ==> NC(T0905) */ + PAD_CFG_NC(GPD10), + /* GPD11: LANPHYC ==> NC */ + PAD_CFG_NC(GPD11), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* Ensure UART pins are in native mode for H1. */ + /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + + /* C23 : UART2_CTS# ==> PCH_WP */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + + /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} -- To view, visit https://review.coreboot.org/27807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I20fc081d372b8686f6128a7e85276f9c6798b199 Gerrit-Change-Number: 27807 Gerrit-PatchSet: 2 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variants/rammus: add memory configuration
by Patrick Georgi (Code Review) 06 Aug '18

06 Aug '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27806 ) Change subject: mb/google/poppy/variants/rammus: add memory configuration ...................................................................... mb/google/poppy/variants/rammus: add memory configuration Add memory configuration based on the proto board schematics BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: I45efdc7893b5bcbca0de6e932e1452cc1a2ff028 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-on: https://review.coreboot.org/27806 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/rammus/Makefile.inc A src/mainboard/google/poppy/variants/rammus/memory.c 2 files changed, 52 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/rammus/Makefile.inc b/src/mainboard/google/poppy/variants/rammus/Makefile.inc index 98464af..edfacea 100644 --- a/src/mainboard/google/poppy/variants/rammus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/rammus/Makefile.inc @@ -1,2 +1,5 @@ SPD_SOURCES = empty # 0b0000 + +romstage-y += memory.c + ramstage-y += nhlt.c diff --git a/src/mainboard/google/poppy/variants/rammus/memory.c b/src/mainboard/google/poppy/variants/rammus/memory.c new file mode 100644 index 0000000..92e66bd --- /dev/null +++ b/src/mainboard/google/poppy/variants/rammus/memory.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> + +/* DQ byte map */ +static const u8 dq_map[][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } +}; + +/* DQS CPU<>DRAM map */ +static const u8 dqs_map[][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 }, +}; + +/* Rcomp resistor */ +static const u16 rcomp_resistor[] = { 200, 81, 162 }; + +/* Rcomp target */ +static const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; + +void variant_memory_params(struct memory_params *p) +{ + p->type = MEMORY_LPDDR3; + p->dq_map = dq_map; + p->dq_map_size = sizeof(dq_map); + p->dqs_map = dqs_map; + p->dqs_map_size = sizeof(dqs_map); + p->rcomp_resistor = rcomp_resistor; + p->rcomp_resistor_size = sizeof(rcomp_resistor); + p->rcomp_target = rcomp_target; + p->rcomp_target_size = sizeof(rcomp_target); +} -- To view, visit https://review.coreboot.org/27806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I45efdc7893b5bcbca0de6e932e1452cc1a2ff028 Gerrit-Change-Number: 27806 Gerrit-PatchSet: 2 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variants/rammus: add audio, mic and codec configuration
by Patrick Georgi (Code Review) 06 Aug '18

06 Aug '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27805 ) Change subject: mb/google/poppy/variants/rammus: add audio, mic and codec configuration ...................................................................... mb/google/poppy/variants/rammus: add audio, mic and codec configuration Rammus uses DA7219 Headset, Maxim MAX98927 Smart Amps and 4 channel dmic BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: If21a3870ee4b000a776d2f3e025fb43ef2fe48c7 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-on: https://review.coreboot.org/27805 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/rammus/Makefile.inc A src/mainboard/google/poppy/variants/rammus/nhlt.c 3 files changed, 52 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 9a75d9c..2ca0f96 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -86,6 +86,12 @@ select NHLT_DMIC_4CH select NHLT_MAX98373 +config INCLUDE_NHLT_BLOBS_RAMMUS + bool "Include blobs for rammus audio." + select NHLT_DA7219 + select NHLT_DMIC_4CH + select NHLT_MAX98927 + config MAINBOARD_DIR string default "google/poppy" @@ -186,6 +192,8 @@ config VARIANT_SPECIFIC_OPTIONS_RAMMUS def_bool n select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_MAX98927 + select DRIVERS_I2C_DA7219 select MAINBOARD_HAS_SPI_TPM_CR50 config VARIANT_SPECIFIC_OPTIONS_SORAKA diff --git a/src/mainboard/google/poppy/variants/rammus/Makefile.inc b/src/mainboard/google/poppy/variants/rammus/Makefile.inc index f24f8a7..98464af 100644 --- a/src/mainboard/google/poppy/variants/rammus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/rammus/Makefile.inc @@ -1 +1,2 @@ SPD_SOURCES = empty # 0b0000 +ramstage-y += nhlt.c diff --git a/src/mainboard/google/poppy/variants/rammus/nhlt.c b/src/mainboard/google/poppy/variants/rammus/nhlt.c new file mode 100644 index 0000000..70c2524 --- /dev/null +++ b/src/mainboard/google/poppy/variants/rammus/nhlt.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +void variant_nhlt_init(struct nhlt *nhlt) +{ + /* 4 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 4)) + printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n"); + + /* Dialog DA7219 Headset codec. */ + if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add Dialog DA7219.\n"); + + /* Maxim MAX98927 Smart Amps for left and right channel */ + if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0)) + printk(BIOS_ERR, "Couldn't add Maxim MAX98927\n"); + +} + +void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, + uint32_t *oem_revision) +{ + *oem_id = "GOOGLE"; + *oem_table_id = "RAMMUSMAX"; + *oem_revision = 0; +} -- To view, visit https://review.coreboot.org/27805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: If21a3870ee4b000a776d2f3e025fb43ef2fe48c7 Gerrit-Change-Number: 27805 Gerrit-PatchSet: 2 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit August 2018