coreboot-gerrit August 2018

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Change in coreboot[master]: nb/intel/*: Account for cbmem_top alignment
by Arthur Heymans (Code Review) 06 Aug '18

06 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27871 to look at the new patch set (#3). Change subject: nb/intel/*: Account for cbmem_top alignment ...................................................................... nb/intel/*: Account for cbmem_top alignment Having cbmem floating between two ram regions is a bad idea and some payloads (e.g. tianocore) even bail out on this. To overcome this issue mark the region between tom and cbmem as uma. Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/x4x/northbridge.c 4 files changed, 48 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/27871/3 -- To view, visit https://review.coreboot.org/27871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 Gerrit-Change-Number: 27871 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: cpu/intel/smm: Don't make assumptions on TSEG_SIZE
by build bot (Jenkins) (Code Review) 06 Aug '18

06 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27872 ) Change subject: cpu/intel/smm: Don't make assumptions on TSEG_SIZE ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/27872/2/src/cpu/intel/smm/gen1/smmrelocate.c File src/cpu/intel/smm/gen1/smmrelocate.c: https://review.coreboot.org/#/c/27872/2/src/cpu/intel/smm/gen1/smmrelocate.… PS2, Line 161: ASSERT(CONFIG_IED_REGION_SIZE > params->smram_size); Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/27872/2/src/cpu/intel/smm/gen1/smmrelocate.… PS2, Line 169: ASSERT(CONFIG_SMM_RESERVED_SIZE > params->smram_size); Comparisons should place the constant on the right side of the test -- To view, visit https://review.coreboot.org/27872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1aadc6f0459a8035864dcf02b0a07e00b284fe2a Gerrit-Change-Number: 27872 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Aug 2018 18:58:25 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/*: Account for cbmem_top alignment
by build bot (Jenkins) (Code Review) 06 Aug '18

06 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27871 ) Change subject: nb/intel/*: Account for cbmem_top alignment ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/#/c/27871/2/src/northbridge/intel/gm45/northbri… File src/northbridge/intel/gm45/northbridge.c: https://review.coreboot.org/#/c/27871/2/src/northbridge/intel/gm45/northbri… PS2, Line 142: /* cbmem_top can be shifted downwards due to aligment. 'aligment' may be misspelled - perhaps 'alignment'? https://review.coreboot.org/#/c/27871/2/src/northbridge/intel/i945/northbri… File src/northbridge/intel/i945/northbridge.c: https://review.coreboot.org/#/c/27871/2/src/northbridge/intel/i945/northbri… PS2, Line 106: /* cbmem_top can be shifted downwards due to aligment. 'aligment' may be misspelled - perhaps 'alignment'? https://review.coreboot.org/#/c/27871/2/src/northbridge/intel/pineview/nort… File src/northbridge/intel/pineview/northbridge.c: https://review.coreboot.org/#/c/27871/2/src/northbridge/intel/pineview/nort… PS2, Line 106: /* cbmem_top can be shifted downwards due to aligment. 'aligment' may be misspelled - perhaps 'alignment'? https://review.coreboot.org/#/c/27871/2/src/northbridge/intel/x4x/northbrid… File src/northbridge/intel/x4x/northbridge.c: https://review.coreboot.org/#/c/27871/2/src/northbridge/intel/x4x/northbrid… PS2, Line 104: /* cbmem_top can be shifted downwards due to aligment. 'aligment' may be misspelled - perhaps 'alignment'? -- To view, visit https://review.coreboot.org/27871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 Gerrit-Change-Number: 27871 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Aug 2018 18:58:18 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/*: Account for cbmem_top alignment
by Arthur Heymans (Code Review) 06 Aug '18

06 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27871 to look at the new patch set (#2). Change subject: nb/intel/*: Account for cbmem_top alignment ...................................................................... nb/intel/*: Account for cbmem_top alignment Having cbmem floating between two ram regions is a bad idea and some payloads (e.g. tianocore) even bail out on this. To overcome this issue mark the region between tom and cbmem as uma. Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/x4x/northbridge.c 4 files changed, 48 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/27871/2 -- To view, visit https://review.coreboot.org/27871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 Gerrit-Change-Number: 27871 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: cpu/intel/smm: Make sure SMRR base is aligned to SMRR size
by Arthur Heymans (Code Review) 06 Aug '18

06 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27870 to look at the new patch set (#2). Change subject: cpu/intel/smm: Make sure SMRR base is aligned to SMRR size ...................................................................... cpu/intel/smm: Make sure SMRR base is aligned to SMRR size If TSEG_BASE is not TSEG_SIZE aligned the SMRR settings are invalid, therefore guard against this. Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/smm/gen1/smmrelocate.c 1 file changed, 19 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/27870/2 -- To view, visit https://review.coreboot.org/27870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315 Gerrit-Change-Number: 27870 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: soc/amd/stoneyridge/acpi.c: Fix plen usage
by Richard Spiegel (Code Review) 06 Aug '18

06 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27877 Change subject: soc/amd/stoneyridge/acpi.c: Fix plen usage ...................................................................... soc/amd/stoneyridge/acpi.c: Fix plen usage In procedure generate_cpu_entries(), plen is first assigned a value of 6, and used when calling acpigen_write_processor, then 0 is written to it, but nex call to acpigen_write_processor uses a hardcoded 0 instead of plen. Replace hardcoded 0 with plen. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I0258b19960b050e8da9d218ded3f1f3bfccad163 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/27877/1 diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 5f9e792..25160d9 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -254,7 +254,7 @@ pcontrol_blk = 0; plen = 0; for (cpu = 1; cpu < cores; cpu++) { - acpigen_write_processor(cpu, pcontrol_blk, 0); + acpigen_write_processor(cpu, pcontrol_blk, plen); acpigen_pop_len(); } } -- To view, visit https://review.coreboot.org/27877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0258b19960b050e8da9d218ded3f1f3bfccad163 Gerrit-Change-Number: 27877 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: src: Fix typo
by build bot (Jenkins) (Code Review) 06 Aug '18

06 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27875 ) Change subject: src: Fix typo ...................................................................... Patch Set 2: (40 comments) https://review.coreboot.org/#/c/27875/2/src/commonlib/include/commonlib/tim… File src/commonlib/include/commonlib/timestamp_serialized.h: https://review.coreboot.org/#/c/27875/2/src/commonlib/include/commonlib/tim… PS2, Line 243: { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgment of raminit"}, line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/advansus/a785e-i/reso… File src/mainboard/advansus/a785e-i/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/advansus/a785e-i/reso… PS2, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/bimini_fam10/reso… File src/mainboard/amd/bimini_fam10/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/bimini_fam10/reso… PS2, Line 123: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/mahogany_fam10/re… File src/mainboard/amd/mahogany_fam10/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/mahogany_fam10/re… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/serengeti_cheetah… PS2, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/south_station/mai… File src/mainboard/amd/south_station/mainboard.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/south_station/mai… PS2, Line 21: #include "SBPLATFORM.h" /* Platform Specific Definitions */ please, no space before tabs https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/tilapia_fam10/res… File src/mainboard/amd/tilapia_fam10/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/tilapia_fam10/res… PS2, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/torpedo/gpio.h File src/mainboard/amd/torpedo/gpio.h: https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/torpedo/gpio.h@301 PS2, Line 301: #define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECEIVER, INPUT, low active line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/torpedo/gpio.h@302 PS2, Line 302: #define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERRUPT FROM BATT CHARGER, INPUT line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/union_station/mai… File src/mainboard/amd/union_station/mainboard.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/union_station/mai… PS2, Line 20: #include "SBPLATFORM.h" /* Platform Specific Definitions */ please, no space before tabs https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kcma-d8/resource… File src/mainboard/asus/kcma-d8/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kcma-d8/resource… PS2, Line 127: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kcma-d8/resource… PS2, Line 382: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kfsn4-dre/resour… File src/mainboard/asus/kfsn4-dre/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kfsn4-dre/resour… PS2, Line 127: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kgpe-d16/resourc… File src/mainboard/asus/kgpe-d16/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kgpe-d16/resourc… PS2, Line 127: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kgpe-d16/resourc… PS2, Line 382: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m4a78-em/resourc… File src/mainboard/asus/m4a78-em/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m4a78-em/resourc… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m4a785-m/resourc… File src/mainboard/asus/m4a785-m/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m4a785-m/resourc… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m5a88-v/resource… File src/mainboard/asus/m5a88-v/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m5a88-v/resource… PS2, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/avalue/eax-785e/resou… File src/mainboard/avalue/eax-785e/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/avalue/eax-785e/resou… PS2, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma785gm/reso… File src/mainboard/gigabyte/ma785gm/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma785gm/reso… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma785gmt/res… File src/mainboard/gigabyte/ma785gmt/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma785gmt/res… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma78gm/resou… File src/mainboard/gigabyte/ma78gm/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma78gm/resou… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/iei/kino-780am2-fam10… File src/mainboard/iei/kino-780am2-fam10/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/iei/kino-780am2-fam10… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/jetway/pa78vm5/resour… File src/mainboard/jetway/pa78vm5/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/jetway/pa78vm5/resour… PS2, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/msi/ms9652_fam10/reso… File src/mainboard/msi/ms9652_fam10/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/msi/ms9652_fam10/reso… PS2, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/siemens/mc_tcu3/ptn34… File src/mainboard/siemens/mc_tcu3/ptn3460.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/siemens/mc_tcu3/ptn34… PS2, Line 117: status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/siemens/mc_tcu3/ptn34… PS2, Line 143: status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/siemens/mc_tcu3/ptn34… PS2, Line 171: status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4, line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8dmr_fam1… File src/mainboard/supermicro/h8dmr_fam10/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8dmr_fam1… PS2, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8qme_fam1… File src/mainboard/supermicro/h8qme_fam10/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8qme_fam1… PS2, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8scm_fam1… File src/mainboard/supermicro/h8scm_fam10/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8scm_fam1… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/mainboard/tyan/s2912_fam10/reso… File src/mainboard/tyan/s2912_fam10/resourcemap.c: https://review.coreboot.org/#/c/27875/2/src/mainboard/tyan/s2912_fam10/reso… PS2, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdfam10/amdfam… File src/northbridge/amd/amdfam10/amdfam10.h: https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdfam10/amdfam… PS2, Line 371: for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of all DIMMs line over 80 characters https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdfam10/amdfam… PS2, Line 372: for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of DIMM0 line over 80 characters https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdfam10/amdfam… PS2, Line 373: F2x[1,0]9C_x[102:101], [103], [106:105], [107] control timing of DIMM1 line over 80 characters https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdht/h3ffeat.h File src/northbridge/amd/amdht/h3ffeat.h: https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdht/h3ffeat.h… PS2, Line 160: /* The number of coherent links coming off of each node (i.e. the 'Degree' of the node) */ line over 80 characters https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdht/h3ncmn.c File src/northbridge/amd/amdht/h3ncmn.c: https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdht/h3ncmn.c@… PS2, Line 1119: * InitComplete = 1,Link initialization is complete line over 80 characters https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdmct/mct_ddr3… PS2, Line 849: /* Restore DRAM Address/Timing Control Register */ line over 80 characters https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdmct/wrappers… File src/northbridge/amd/amdmct/wrappers/mcti_d.c: https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdmct/wrappers… PS2, Line 172: //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node initialization */ line over 80 characters https://review.coreboot.org/#/c/27875/2/src/superio/smsc/sio1036/sio1036_ea… File src/superio/smsc/sio1036/sio1036_early_init.c: https://review.coreboot.org/#/c/27875/2/src/superio/smsc/sio1036/sio1036_ea… PS2, Line 76: pnp_write_config (dev, 0x0A, 0x00 | IR_OUTPUT_MUX); space prohibited between function name and open parenthesis '(' -- To view, visit https://review.coreboot.org/27875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882 Gerrit-Change-Number: 27875 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Aug 2018 17:34:27 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src: Fix typo
by Elyes HAOUAS (Code Review) 06 Aug '18

06 Aug '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/27875 ) Change subject: src: Fix typo ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/27875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882 Gerrit-Change-Number: 27875 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Aug 2018 17:26:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware
by Patrick Rudolph (Code Review) 06 Aug '18

06 Aug '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/27873 ) Change subject: nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware ...................................................................... Patch Set 1: Add comment which explains why 2MB TSEG is used, to prevent someone sets it to 8MB in the future ? -- To view, visit https://review.coreboot.org/27873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b Gerrit-Change-Number: 27873 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Aug 2018 17:24:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Prevent reboot in romstage
by Raul Rangel (Code Review) 06 Aug '18

06 Aug '18

Hello Garrett Kirkendall, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27876 to look at the new patch set (#3). Change subject: soc/amd/stoneyridge: Prevent reboot in romstage ...................................................................... soc/amd/stoneyridge: Prevent reboot in romstage By setting this register in bootblock AmdInitEnv will no longer trigger a reset in romstage. This fixes a few vboot test failures and also speeds up boot time. BUG=b:111610455 TEST=Built grunt and made sure bootblock only happens once on cold boot, and S3 resume. Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/soc/amd/stoneyridge/southbridge.c 1 file changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/27876/3 -- To view, visit https://review.coreboot.org/27876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e Gerrit-Change-Number: 27876 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit August 2018