coreboot-gerrit August 2018

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Change in coreboot[master]: nb/intel/*: Account for cbmem_top alignment
by Elyes HAOUAS (Code Review) 07 Aug '18

07 Aug '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/27871 ) Change subject: nb/intel/*: Account for cbmem_top alignment ...................................................................... Patch Set 4: indeed, it is using an external GPU. -- To view, visit https://review.coreboot.org/27871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 Gerrit-Change-Number: 27871 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Aug 2018 07:23:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src/soc/intel/common: Configure the gspi chip select state correctly
by Aamir Bohra (Code Review) 07 Aug '18

07 Aug '18

Aamir Bohra has uploaded a new patch set (#2). ( https://review.coreboot.org/27889 ) Change subject: src/soc/intel/common: Configure the gspi chip select state correctly ...................................................................... src/soc/intel/common: Configure the gspi chip select state correctly This implementation updates the chip select control register programming in gspi controller setup call to program the correct bit fields for chip select state. Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/common/block/gspi/gspi.c 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/27889/2 -- To view, visit https://review.coreboot.org/27889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53 Gerrit-Change-Number: 27889 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com>

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Change in coreboot[master]: src/soc/intel/common: Configure the chip select state correctly
by Aamir Bohra (Code Review) 07 Aug '18

07 Aug '18

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/27889 Change subject: src/soc/intel/common: Configure the chip select state correctly ...................................................................... src/soc/intel/common: Configure the chip select state correctly This implementation updates the chip select control register programming in gspi controller setup call to program the correct bit fields for chip select state. Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/common/block/gspi/gspi.c 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/27889/1 diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 35c34ce..fc7dd46 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -481,12 +481,9 @@ cs_ctrl = CS_MODE_SW | CS_0; pol = gspi_csctrl_polarity(cfg.cs_polarity); cs_ctrl |= pol << CS_0_POL_SHIFT; - cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT); + cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT) << CS_STATE_SHIFT; gspi_write_mmio_reg(p, SPI_CS_CONTROL, cs_ctrl); - /* De-assert chip select. */ - __gspi_cs_change(p, CS_DEASSERT); - /* Disable SPI controller. */ gspi_write_mmio_reg(p, SSCR0, SSCR0_SSE_DISABLE); -- To view, visit https://review.coreboot.org/27889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53 Gerrit-Change-Number: 27889 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com>

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Change in coreboot[master]: nb/intel/*: Account for cbmem_top alignment
by Arthur Heymans (Code Review) 07 Aug '18

07 Aug '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27871 ) Change subject: nb/intel/*: Account for cbmem_top alignment ...................................................................... Patch Set 4: > tested on i945g-m4: > I'm getting Grub2 boot menu faster. > > - Linux start, but can see only one CPU. dmsg: " smpboot: > do_boot_cpu failed(-1) to wakeup CPU#1" > - S3 not working > - "# ./flashrom -p internal", gives : > flashrom v0.9.7-r1711 on Linux 4.17.0-1-amd64 (x86_64) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Error accessing high tables, 0x100000 bytes at 0x00000000cef38000 > /dev/mem mmap failed: Operation not permitted > Failed getting access to coreboot high tables. > Found chipset "Intel ICH7/ICH7R". Enabling flash write... OK. > Found SST flash chip "SST49LF004A/B" (512 kB, FWH) at physical > address 0xfff80000. > No operations were specified. > to solve this, I need to comment line #949 intel/i945/early_init.c > > Console log: https://pastebin.com/6QQKQHa7 Do you happen to run with an external GPU? -- To view, visit https://review.coreboot.org/27871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 Gerrit-Change-Number: 27871 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Aug 2018 06:59:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: cbmem: rename vdat to chromeos_acpi
by Joel Kitching (Code Review) 07 Aug '18

07 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27888 to look at the new patch set (#3). Change subject: cbmem: rename vdat to chromeos_acpi ...................................................................... cbmem: rename vdat to chromeos_acpi There is a confusingly named section in cbmem called vdat. This section holds a data structure called chromeos_acpi_t, which exposes some system information to the Chrome OS userland utility crossystem. Within the chromeos_acpi_t structure, there is a member called vdat. This (currently) holds a VbSharedDataHeader. Rename the outer vdat to chromeos_acpi to make its purpose clear, and prevent the bizarreness of being able to access vdat->vdat. Additionally, disallow external references to the chromeos_acpi data structure in gnvs.c. BUG=b:112288216 TEST=emerge-eve coreboot, run on eve CQ-DEPEND=CL:1164722 Signed-off-by: Joel Kitching <kitching(a)google.com> Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/arch/x86/smbios.c M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c M src/vendorcode/google/chromeos/gnvs.c M src/vendorcode/google/chromeos/gnvs.h 8 files changed, 42 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/27888/3 -- To view, visit https://review.coreboot.org/27888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e Gerrit-Change-Number: 27888 Gerrit-PatchSet: 3 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/*: Account for cbmem_top alignment
by Elyes HAOUAS (Code Review) 07 Aug '18

07 Aug '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/27871 ) Change subject: nb/intel/*: Account for cbmem_top alignment ...................................................................... Patch Set 4: Code-Review+1 tested on i945g-m4: I'm getting Grub2 boot menu faster. - Linux start, but can see only one CPU. dmsg: " smpboot: do_boot_cpu failed(-1) to wakeup CPU#1" - S3 not working - "# ./flashrom -p internal", gives : flashrom v0.9.7-r1711 on Linux 4.17.0-1-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Error accessing high tables, 0x100000 bytes at 0x00000000cef38000 /dev/mem mmap failed: Operation not permitted Failed getting access to coreboot high tables. Found chipset "Intel ICH7/ICH7R". Enabling flash write... OK. Found SST flash chip "SST49LF004A/B" (512 kB, FWH) at physical address 0xfff80000. No operations were specified. to solve this, I need to comment line #949 intel/i945/early_init.c Console log: https://pastebin.com/6QQKQHa7 -- To view, visit https://review.coreboot.org/27871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 Gerrit-Change-Number: 27871 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Aug 2018 06:07:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cbmem: rename vdat to chromeos_acpi
by Joel Kitching (Code Review) 07 Aug '18

07 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27888 to look at the new patch set (#2). Change subject: cbmem: rename vdat to chromeos_acpi ...................................................................... cbmem: rename vdat to chromeos_acpi There is a confusingly named section in cbmem called vdat. This section holds a data structure called chromeos_acpi_t, which exposes some system information to the Chrome OS userland utility crossystem. Within the chromeos_acpi_t structure, there is a member called vdat. This (currently) holds a VbSharedDataHeader. Rename the outer vdat to chromeos_acpi to make its purpose clear, and prevent the bizarreness of being able to access vdat->vdat. Additionally, disallow external references to the chromeos_acpi data structure in gnvs.c. BUG=b:112288216 TEST=emerge-eve coreboot, run on eve CQ-DEPEND=CL:1164722 Signed-off-by: Joel Kitching <kitching(a)google.com> Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e --- M 3rdparty/blobs M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/arch/x86/smbios.c M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c M src/vendorcode/google/chromeos/gnvs.c M src/vendorcode/google/chromeos/gnvs.h 9 files changed, 43 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/27888/2 -- To view, visit https://review.coreboot.org/27888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e Gerrit-Change-Number: 27888 Gerrit-PatchSet: 2 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: cbmem: rename vdat to chromeos_acpi
by Joel Kitching (Code Review) 07 Aug '18

07 Aug '18

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/27888 Change subject: cbmem: rename vdat to chromeos_acpi ...................................................................... cbmem: rename vdat to chromeos_acpi There is a confusingly named section in cbmem called vdat. This section holds a data structure called chromeos_acpi_t, which exposes some system information to the Chrome OS userland utility crossystem. Within the chromeos_acpi_t structure, there is a member called vdat. This (currently) holds a VbSharedDataHeader. Rename the outer vdat to chromeos_acpi to make its purpose clear, and prevent the bizarreness of being able to access vdat->vdat. Additionally, disallow external references to the chromeos_acpi data structure in gnvs.c. BUG=b:112288216 TEST=emerge-eve coreboot, run on eve CQ-DEPEND=CL:1164722 Signed-off-by: Joel Kitching <kitching(a)google.com> Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e --- M 3rdparty/blobs M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/arch/x86/smbios.c M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c M src/vendorcode/google/chromeos/gnvs.c M src/vendorcode/google/chromeos/gnvs.h 9 files changed, 43 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/27888/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index 372012e..8e9f99b 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 372012e8e1d0d01f3e77ff73b118665b41ff68b6 +Subproject commit 8e9f99b3e60d0ffe8b67cc93ea4ab1b9ed191e45 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 6b6d1b4..4cf57c5 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -200,7 +200,7 @@ struct cb_gpio gpios[0]; }; -#define CB_TAG_VDAT 0x0015 +#define CB_TAG_CHROMEOS_ACPI 0x0015 #define CB_TAG_VBNV 0x0019 #define CB_TAG_VBOOT_HANDOFF 0x0020 #define CB_TAG_DMA 0x0022 diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index f221a15..66933e3 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -97,8 +97,8 @@ void *vboot_handoff; u32 vboot_handoff_size; - void *vdat_addr; - u32 vdat_size; + void *chromeos_acpi_addr; + u32 chromeos_acpi_size; #if IS_ENABLED(CONFIG_LP_ARCH_X86) int x86_rom_var_mtrr_index; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index d831b96..b879987 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -106,12 +106,12 @@ info->gpios[i] = gpios->gpios[i]; } -static void cb_parse_vdat(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_chromeos_acpi(unsigned char *ptr, struct sysinfo_t *info) { - struct lb_range *vdat = (struct lb_range *) ptr; + struct lb_range *chromeos_acpi = (struct lb_range *) ptr; - info->vdat_addr = phys_to_virt(vdat->range_start); - info->vdat_size = vdat->range_size; + info->chromeos_acpi_addr = phys_to_virt(chromeos_acpi->range_start); + info->chromeos_acpi_size = chromeos_acpi->range_size; } static void cb_parse_mac_addresses(unsigned char *ptr, @@ -357,8 +357,8 @@ case CB_TAG_GPIO: cb_parse_gpios(ptr, info); break; - case CB_TAG_VDAT: - cb_parse_vdat(ptr, info); + case CB_TAG_CHROMEOS_ACPI: + cb_parse_chromeos_acpi(ptr, info); break; case CB_TAG_VBNV: cb_parse_vbnv(ptr, info); diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 582ae8d..8dad4af 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -367,7 +367,11 @@ #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) /* SMBIOS offsets start at 1 rather than 0 */ - vboot_data->vbt10 = (u32)t->eos + (version_offset - 1); + chromeos_acpi_t *chromeos_acpi; + uint32_t *chromeos_acpi_size; + acpi_get_chromeos_acpi_info((uint64_t *)&chromeos_acpi, + (uint32_t *)&chromeos_acpi_size); + chromeos_acpi->vbt10 = (u32)t->eos + (version_offset - 1); #endif #endif /* CONFIG_CHROMEOS */ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 806dfc7..34726ab 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -290,7 +290,7 @@ struct lb_gpio gpios[0]; }; -#define LB_TAG_VDAT 0x0015 +#define LB_TAG_CHROMEOS_ACPI 0x0015 #define LB_TAG_VBNV 0x0019 #define LB_TAB_VBOOT_HANDOFF 0x0020 #define LB_TAB_DMA 0x0022 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 2d74c8e..6b0e1a0 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -195,15 +195,16 @@ } } -static void lb_vdat(struct lb_header *header) +static void lb_chromeos_acpi(struct lb_header *header) { #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - struct lb_range *vdat; + struct lb_range *chromeos_acpi; - vdat = (struct lb_range *)lb_new_record(header); - vdat->tag = LB_TAG_VDAT; - vdat->size = sizeof(*vdat); - acpi_get_vdat_info(&vdat->range_start, &vdat->range_size); + chromeos_acpi = (struct lb_range *)lb_new_record(header); + chromeos_acpi->tag = LB_TAG_CHROMEOS_ACPI; + chromeos_acpi->size = sizeof(*chromeos_acpi); + acpi_get_chromeos_acpi_info(&chromeos_acpi->range_start, + &chromeos_acpi->range_size); #endif } @@ -546,8 +547,8 @@ /* Record our GPIO settings (ChromeOS specific) */ lb_gpios(head); - /* pass along the VDAT buffer address */ - lb_vdat(head); + /* pass along the chromeos_acpi_t buffer address */ + lb_chromeos_acpi(head); /* pass along VBNV offsets in CMOS */ lb_vbnv(head); diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index a278b41..b3c71e4 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -27,40 +27,41 @@ #include "chromeos.h" #include "gnvs.h" -chromeos_acpi_t *vboot_data = NULL; +chromeos_acpi_t *chromeos_acpi = NULL; static u32 me_hash_saved[8]; -void chromeos_init_vboot(chromeos_acpi_t *chromeos) +void chromeos_init_vboot(chromeos_acpi_t *init) { - vboot_data = chromeos; + chromeos_acpi = init; /* Copy saved ME hash into NVS */ - memcpy(vboot_data->mehh, me_hash_saved, sizeof(vboot_data->mehh)); + memcpy(chromeos_acpi->mehh, me_hash_saved, sizeof(chromeos_acpi->mehh)); struct vboot_handoff *vboot_handoff; if (vboot_get_handoff_info((void **)&vboot_handoff, NULL) == 0) - memcpy(&chromeos->vdat[0], &vboot_handoff->shared_data[0], - ARRAY_SIZE(chromeos->vdat)); + memcpy(&chromeos_acpi->vdat[0], &vboot_handoff->shared_data[0], + ARRAY_SIZE(chromeos_acpi->vdat)); - chromeos_ram_oops_init(chromeos); + chromeos_ram_oops_init(chromeos_acpi); } void chromeos_set_me_hash(u32 *hash, int len) { - if ((len*sizeof(u32)) > sizeof(vboot_data->mehh)) + if ((len*sizeof(u32)) > sizeof(chromeos_acpi->mehh)) return; /* Copy to NVS or save until it is ready */ - if (vboot_data) + if (chromeos_acpi) /* This does never happen! */ - memcpy(vboot_data->mehh, hash, len*sizeof(u32)); + memcpy(chromeos_acpi->mehh, hash, len*sizeof(u32)); else memcpy(me_hash_saved, hash, len*sizeof(u32)); } -void acpi_get_vdat_info(uint64_t *vdat_addr, uint32_t *vdat_size) +void acpi_get_chromeos_acpi_info(uint64_t *chromeos_acpi_addr, + uint32_t *chromeos_acpi_size) { - *vdat_addr = (intptr_t)vboot_data; - *vdat_size = sizeof(*vboot_data); + *chromeos_acpi_addr = (intptr_t)chromeos_acpi; + *chromeos_acpi_size = sizeof(*chromeos_acpi); } diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 82cd409..346ac43 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -53,7 +53,7 @@ u32 vbt7; // 18e active main firmware type u32 vbt8; // 192 recovery reason u32 vbt9; // 196 fmap base address - u8 vdat[3072]; // 19a + u8 vdat[3072]; // 19a VDAT space filled by verified boot u32 vbt10; // d9a smbios bios version u32 mehh[8]; // d9e management engine hash u32 ramoops_base; // dbe ramoops base address @@ -61,9 +61,9 @@ u8 pad[314]; // dc6-eff } __packed chromeos_acpi_t; -extern chromeos_acpi_t *vboot_data; -void chromeos_init_vboot(chromeos_acpi_t *chromeos); +void chromeos_init_vboot(chromeos_acpi_t *init); void chromeos_set_me_hash(u32*, int); -void acpi_get_vdat_info(uint64_t *vdat_addr, uint32_t *vdat_size); +void acpi_get_chromeos_acpi_info(uint64_t *chromeos_acpi_addr, + uint32_t *chromeos_acpi_size); #endif -- To view, visit https://review.coreboot.org/27888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e Gerrit-Change-Number: 27888 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com>

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Change in coreboot[master]: security/vboot: Split fwid.region build target
by Julius Werner (Code Review) 07 Aug '18

07 Aug '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/27884 ) Change subject: security/vboot: Split fwid.region build target ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/27884/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27884/1//COMMIT_MSG@11 PS1, Line 11: objects are not invalidated when bumping the fwid. I don't believe this, actually. I also don't think your patch really makes a practical difference for incremental builts. Right now, you just have a normal (non-PHONY) rule for the $(obj)/fwid.region target. Once that file exists, it will never be remade (since it doesn't have any prerequisites). So this should never run twice unless you blow away your $(obj) directory (and that makes sense, because the contents of that file only depend on Kconfig, and when you change Kconfig you generally have to blow away everything anyway). With your change, you have the same sort of situation for the $(obj)/fwid.version target. And then $(obj)/fwid.region gets a dependency to that, so it will only be remade if $(obj)/fwid.version was updated, which will never happen unless it got deleted somehow. So, same situation, practically. Can you clarify why you believe this target creates a problem in regards to incremental builds? https://review.coreboot.org/#/c/27884/1/src/security/vboot/Makefile.inc File src/security/vboot/Makefile.inc: https://review.coreboot.org/#/c/27884/1/src/security/vboot/Makefile.inc@232 PS1, Line 232: file Uhhh... either I'm really missing something right now, or this is calling the 'file' utility and connection your firmware version file to it through stdin. So... that makes no sense. I think you meant "$(< $(obj)/fwid.version)"? -- To view, visit https://review.coreboot.org/27884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I955106efd648a75a1311f24ede46bd238d1517e0 Gerrit-Change-Number: 27884 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 06 Aug 2018 22:32:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: lib/bootmem.c:Remove unused setting of variable "begin"
by Richard Spiegel (Code Review) 07 Aug '18

07 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27886 Change subject: lib/bootmem.c:Remove unused setting of variable "begin" ...................................................................... lib/bootmem.c:Remove unused setting of variable "begin" The variable "begin" is extracted from the structure, but 4 lines below it's overwritten with "end - size". This causes a static build scan error that should be fixed. Remove the initial assignment of variable "begin". BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I0a265747e61289f045c5cac09e40478bd31e16fc Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/lib/bootmem.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/27886/1 diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index 66d4592..38fdb1b 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -278,7 +278,6 @@ return NULL; /* region now points to the highest usable region for the given size. */ - begin = range_entry_base(region); end = range_entry_end(region); if (end > max_addr) end = max_addr; -- To view, visit https://review.coreboot.org/27886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0a265747e61289f045c5cac09e40478bd31e16fc Gerrit-Change-Number: 27886 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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coreboot-gerrit August 2018