coreboot-gerrit August 2018

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Change in coreboot[master]: Makefile: Enable DELETE_ON_ERROR for all targets
by Raul Rangel (Code Review) 07 Aug '18

07 Aug '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27885 Change subject: Makefile: Enable DELETE_ON_ERROR for all targets ...................................................................... Makefile: Enable DELETE_ON_ERROR for all targets If a target is interrupted in the middle of writing an output file, the file could be left in a corrupt state. A subsequent make invocation will see the file as up to date and can cause very confusing errors. BUG=b:112267918 TEST=Made a target fail before completion and verified make deleted the output file. Change-Id: I865827ea769b4dffa638d4324fc7284f6cb2ddc0 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/27885/1 diff --git a/Makefile b/Makefile index 4aa179d..1d4a488 100644 --- a/Makefile +++ b/Makefile @@ -174,6 +174,7 @@ # must come rather early .SECONDEXPANSION: +.DELETE_ON_ERROR: $(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG) +$(MAKE) oldconfig -- To view, visit https://review.coreboot.org/27885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I865827ea769b4dffa638d4324fc7284f6cb2ddc0 Gerrit-Change-Number: 27885 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: security/vboot: Split fwid.region build target
by Raul Rangel (Code Review) 07 Aug '18

07 Aug '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27884 Change subject: security/vboot: Split fwid.region build target ...................................................................... security/vboot: Split fwid.region build target Add the ability to specify the fwid version via a file instead of via config. This makes it so when doing an incremental build all objects are not invalidated when bumping the fwid. The coreboot ebuild will create this file to pass the latest version. BUG=b:112267918 TEST=ran dmidecide -t 0 and verified version was present Change-Id: I955106efd648a75a1311f24ede46bd238d1517e0 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/security/vboot/Makefile.inc 1 file changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/27884/1 diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index b542425..7d40428 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -223,8 +223,13 @@ endif mv $@.tmp $@ -$(obj)/fwid.region: - printf "$(CONFIG_VBOOT_FWID_MODEL)$(CONFIG_VBOOT_FWID_VERSION)\0" > $@ +$(obj)/fwid.version: + echo -n "$(CONFIG_VBOOT_FWID_VERSION)" > $@ + +$(obj)/fwid.region: $(obj)/fwid.version + printf "%s%s\0" \ + "$(CONFIG_VBOOT_FWID_MODEL)" \ + "$(file < $(obj)/fwid.version)" > $@ build_complete:: $(obj)/gbb.region $(obj)/fwid.region @printf " WRITE GBB\n" -- To view, visit https://review.coreboot.org/27884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I955106efd648a75a1311f24ede46bd238d1517e0 Gerrit-Change-Number: 27884 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: libpayload/drivers/usb/xhci: Replace raw values with constants
by Raul Rangel (Code Review) 07 Aug '18

07 Aug '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27883 Change subject: libpayload/drivers/usb/xhci: Replace raw values with constants ...................................................................... libpayload/drivers/usb/xhci: Replace raw values with constants BUG=none TEST=compiled on grunt and made sure USB still works in depthcharge Change-Id: I972f4604bb5ff3838cb15f323c5a579ad890ecf5 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M payloads/libpayload/drivers/usb/xhci.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/27883/1 diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 8972ffa..3f1064a 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -304,10 +304,10 @@ u32 reg_addr; hci_t *controller; - reg_addr = pci_read_config32 (addr, 0x10) & ~0xf; - if (pci_read_config32 (addr, 0x14) > 0) { + reg_addr = pci_read_config32(addr, PCI_BASE_ADDRESS_0) & + PCI_BASE_ADDRESS_MEM_MASK; + if (pci_read_config32(addr, PCI_BASE_ADDRESS_1) > 0) fatal("We don't do 64bit addressing.\n"); - } controller = xhci_init((unsigned long)reg_addr); if (controller) { -- To view, visit https://review.coreboot.org/27883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I972f4604bb5ff3838cb15f323c5a579ad890ecf5 Gerrit-Change-Number: 27883 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: include/program_loading: Make PROG_INIT clear the entire structure
by Raul Rangel (Code Review) 07 Aug '18

07 Aug '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27882 Change subject: include/program_loading: Make PROG_INIT clear the entire structure ...................................................................... include/program_loading: Make PROG_INIT clear the entire structure Initialize all the values to prevent garbage values. BUG=none TEST=compiled grunt Change-Id: I38e424ba53c2a2df91e6187ad424caf2d5ca5e98 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/include/program_loading.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/27882/1 diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 482c8b8..8cc927c 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -72,6 +72,10 @@ { \ .type = (type_), \ .name = (name_), \ + .cbfs_type = 0, \ + .rdev = {0}, \ + .entry = NULL, \ + .arg = NULL, \ } static inline const char *prog_name(const struct prog *prog) -- To view, visit https://review.coreboot.org/27882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I38e424ba53c2a2df91e6187ad424caf2d5ca5e98 Gerrit-Change-Number: 27882 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: arm64: Turn architectural register accessors into inline functions
by build bot (Jenkins) (Code Review) 06 Aug '18

06 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27881 ) Change subject: arm64: Turn architectural register accessors into inline functions ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/27881/2/src/arch/arm64/include/armv8/arch/l… File src/arch/arm64/include/armv8/arch/lib_helpers.h: https://review.coreboot.org/#/c/27881/2/src/arch/arm64/include/armv8/arch/l… PS2, Line 162: #define MAKE_REGISTER_ACCESSORS_EL123(reg) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/27881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2c41cc3ce49ee26bf12cd34e3d0509d8e61ffc63 Gerrit-Change-Number: 27881 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Aug 2018 21:27:58 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: arm64: Turn architectural register accessors into inline functions
by build bot (Jenkins) (Code Review) 06 Aug '18

06 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27881 ) Change subject: arm64: Turn architectural register accessors into inline functions ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27881/1/src/arch/arm64/include/armv8/arch/l… File src/arch/arm64/include/armv8/arch/lib_helpers.h: https://review.coreboot.org/#/c/27881/1/src/arch/arm64/include/armv8/arch/l… PS1, Line 162: #define MAKE_REGISTER_ACCESSORS_EL123(reg) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/27881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2c41cc3ce49ee26bf12cd34e3d0509d8e61ffc63 Gerrit-Change-Number: 27881 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Aug 2018 21:27:27 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/intel/smm: Make sure SMRR base is aligned to SMRR size
by Felix Held (Code Review) 06 Aug '18

06 Aug '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/27870 ) Change subject: cpu/intel/smm: Make sure SMRR base is aligned to SMRR size ...................................................................... Patch Set 2: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/27870/2/src/cpu/intel/smm/gen1/smmrelocate.c File src/cpu/intel/smm/gen1/smmrelocate.c: https://review.coreboot.org/#/c/27870/2/src/cpu/intel/smm/gen1/smmrelocate.… PS2, Line 180: BIOS_WARNING warning or error? -- To view, visit https://review.coreboot.org/27870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315 Gerrit-Change-Number: 27870 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Aug 2018 21:00:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/*: Account for cbmem_top alignment
by Arthur Heymans (Code Review) 06 Aug '18

06 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27871 to look at the new patch set (#4). Change subject: nb/intel/*: Account for cbmem_top alignment ...................................................................... nb/intel/*: Account for cbmem_top alignment Having cbmem floating between two ram regions is a bad idea and some payloads (e.g. tianocore) even bail out on this. To overcome this issue mark the region between tom and cbmem as uma. Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/x4x/northbridge.c 4 files changed, 48 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/27871/4 -- To view, visit https://review.coreboot.org/27871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 Gerrit-Change-Number: 27871 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware
by Arthur Heymans (Code Review) 06 Aug '18

06 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27873 to look at the new patch set (#3). Change subject: nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware ...................................................................... nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware 8M was set in the assumption that at least 4M was needed for IED (Intel Enhanced Debug) , but this is not true. The SMRR MTRR's need to have TSEG aligned to its size which is easier when TSEG is only 2M. Also at most 6M of RAM more becomes available for use. Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/raminit_ddr23.c 4 files changed, 16 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/27873/3 -- To view, visit https://review.coreboot.org/27873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b Gerrit-Change-Number: 27873 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: cpu/intel/smm: Don't make assumptions on TSEG_SIZE
by Arthur Heymans (Code Review) 06 Aug '18

06 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27872 to look at the new patch set (#3). Change subject: cpu/intel/smm: Don't make assumptions on TSEG_SIZE ...................................................................... cpu/intel/smm: Don't make assumptions on TSEG_SIZE Do not assume: - TSEG is 8M - IED_REGION_SIZE is set (not needed on older platforms). Change-Id: I1aadc6f0459a8035864dcf02b0a07e00b284fe2a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/smm/gen1/smmrelocate.c 1 file changed, 21 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/27872/3 -- To view, visit https://review.coreboot.org/27872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I1aadc6f0459a8035864dcf02b0a07e00b284fe2a Gerrit-Change-Number: 27872 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit August 2018