coreboot-gerrit August 2018

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Change in coreboot[master]: cpu/intel/smm: Make sure SMRR base is aligned to SMRR size
by Felix Held (Code Review) 06 Aug '18

06 Aug '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/27870 ) Change subject: cpu/intel/smm: Make sure SMRR base is aligned to SMRR size ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27870/1/src/cpu/intel/smm/gen1/smmrelocate.c File src/cpu/intel/smm/gen1/smmrelocate.c: https://review.coreboot.org/#/c/27870/1/src/cpu/intel/smm/gen1/smmrelocate.… PS1, Line 176: (1 << 20) is it intended hat you replace tseg_size with this constant? -- To view, visit https://review.coreboot.org/27870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315 Gerrit-Change-Number: 27870 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 06 Aug 2018 14:48:49 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/*: Account for cbmem_top alignment
by build bot (Jenkins) (Code Review) 06 Aug '18

06 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27871 ) Change subject: nb/intel/*: Account for cbmem_top alignment ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/27871/1/src/northbridge/intel/gm45/northbri… File src/northbridge/intel/gm45/northbridge.c: https://review.coreboot.org/#/c/27871/1/src/northbridge/intel/gm45/northbri… PS1, Line 142: /* cbmem_top can be shifted downwards due to aligment. 'aligment' may be misspelled - perhaps 'alignment'? https://review.coreboot.org/#/c/27871/1/src/northbridge/intel/i945/northbri… File src/northbridge/intel/i945/northbridge.c: https://review.coreboot.org/#/c/27871/1/src/northbridge/intel/i945/northbri… PS1, Line 106: /* cbmem_top can be shifted downwards due to aligment. 'aligment' may be misspelled - perhaps 'alignment'? https://review.coreboot.org/#/c/27871/1/src/northbridge/intel/pineview/nort… File src/northbridge/intel/pineview/northbridge.c: https://review.coreboot.org/#/c/27871/1/src/northbridge/intel/pineview/nort… PS1, Line 106: /* cbmem_top can be shifted downwards due to aligment. 'aligment' may be misspelled - perhaps 'alignment'? https://review.coreboot.org/#/c/27871/1/src/northbridge/intel/x4x/northbrid… File src/northbridge/intel/x4x/northbridge.c: https://review.coreboot.org/#/c/27871/1/src/northbridge/intel/x4x/northbrid… PS1, Line 104: /* cbmem_top can be shifted downwards due to aligment. 'aligment' may be misspelled - perhaps 'alignment'? -- To view, visit https://review.coreboot.org/27871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 Gerrit-Change-Number: 27871 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Aug 2018 14:13:58 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/intel/smm: Don't make assumptions on TSEG_SIZE
by build bot (Jenkins) (Code Review) 06 Aug '18

06 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27872 ) Change subject: cpu/intel/smm: Don't make assumptions on TSEG_SIZE ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/27872/1/src/cpu/intel/smm/gen1/smmrelocate.c File src/cpu/intel/smm/gen1/smmrelocate.c: https://review.coreboot.org/#/c/27872/1/src/cpu/intel/smm/gen1/smmrelocate.… PS1, Line 161: ASSERT(CONFIG_IED_REGION_SIZE > params->smram_size); Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/27872/1/src/cpu/intel/smm/gen1/smmrelocate.… PS1, Line 169: ASSERT(CONFIG_SMM_RESERVED_SIZE > params->smram_size); Comparisons should place the constant on the right side of the test -- To view, visit https://review.coreboot.org/27872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1aadc6f0459a8035864dcf02b0a07e00b284fe2a Gerrit-Change-Number: 27872 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Aug 2018 14:13:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware
by Arthur Heymans (Code Review) 06 Aug '18

06 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27873 Change subject: nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware ...................................................................... nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware 8M was set in the assumption that at least 4M was needed for IED (Intel Enhanced Debug) , but this is not true. The SMRR MTRR's need to have TSEG aligned to its size which is easier when TSEG is only 2M. Also at most 6M of RAM more becomes available for use. Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/raminit_ddr23.c 4 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/27873/1 diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 08f954d..61a2b4e 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1242,12 +1242,12 @@ uma_sizem = (gms_sizek + gsm_sizek) >> 10; } - /* TSEG 8M */ + /* TSEG 2M */ u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); reg8 &= ~0x7; - reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */ + reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */ pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8); - uma_sizem += 8; + uma_sizem += 2; } const unsigned int mmio_size = get_mmio_size(); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 7de2c73..8e68af5 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -194,7 +194,7 @@ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); reg8 &= ~0x7; - reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */ + reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */ pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8); /* Set C0000-FFFFF to access RAM on both reads and writes */ diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 66f0a10..59eadc3 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -2039,7 +2039,7 @@ gttsize = ggc_to_gtt[(ggc & 0x300) >> 8]; tom = s->channel_capacity[0]; - tsegsize = 0x8; // 8MB + tsegsize = 0x2; // 2MB mmiosize = 0x400; // 1GB reclaim = false; @@ -2076,7 +2076,7 @@ u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); reg8 &= ~0x7; - reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */ + reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */ pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8); printk(BIOS_DEBUG, "GBSM (igd) = verified %08x (written %08x)\n", diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index c445cad..a788dd9 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1722,7 +1722,7 @@ ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); gfxsize = ggc2uma[(ggc & 0xf0) >> 4]; gttsize = ggc2gtt[(ggc & 0xf00) >> 8]; - tsegsize = 8; // 8MB TSEG + tsegsize = 2; // 2MB TSEG mmiosize = 0x800; // 2GB MMIO umasizem = gfxsize + gttsize + tsegsize; mmiostart = 0x1000 - mmiosize + umasizem; @@ -1759,10 +1759,10 @@ pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud); pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20); pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20); - /* Enable and set tseg size to 8M */ + /* Enable and set tseg size to 2M */ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); reg8 &= ~0x7; - reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */ + reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */ pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8); pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20); } -- To view, visit https://review.coreboot.org/27873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b Gerrit-Change-Number: 27873 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: cpu/intel/smm: Don't make assumptions on TSEG_SIZE
by Arthur Heymans (Code Review) 06 Aug '18

06 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27872 Change subject: cpu/intel/smm: Don't make assumptions on TSEG_SIZE ...................................................................... cpu/intel/smm: Don't make assumptions on TSEG_SIZE Do not assume: - TSEG is 8M - IED_REGION_SIZE is set (not needed on older platforms). Change-Id: I1aadc6f0459a8035864dcf02b0a07e00b284fe2a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/smm/gen1/smmrelocate.c 1 file changed, 21 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/27872/1 diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index a298985..aa689f0 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -16,6 +16,7 @@ /* SMM relocation with intention to work for i945-ivybridge. Right now used for sandybridge and ivybridge. */ +#include <assert.h> #include <types.h> #include <string.h> #include <compiler.h> @@ -125,10 +126,15 @@ * size * CPU num. */ save_state->smbase = relo_params->smram_base - cpu * runtime->save_state_size; - save_state->iedbase = relo_params->ied_base; + if (CONFIG_IED_REGION_SIZE != 0) { + save_state->iedbase = relo_params->ied_base; - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n", - save_state->smbase, save_state->iedbase, save_state); + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n", + save_state->smbase, save_state->iedbase, save_state); + } else { + printk(BIOS_DEBUG, "New SMBASE=0x%08x @ %p\n", + save_state->smbase, save_state); + } /* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); @@ -149,16 +155,20 @@ configuration value instead. */ const u32 tseg_size = northbridge_get_tseg_size(); - /* The SMRAM available to the handler is 4MiB - since the IEDRAM lives at TSEGMB + 4MiB. */ params->smram_base = tsegmb; - params->smram_size = 4 << 20; - params->ied_base = tsegmb + params->smram_size; - params->ied_size = tseg_size - params->smram_size; + params->smram_size = tseg_size; + if (CONFIG_IED_REGION_SIZE != 0) { + ASSERT(CONFIG_IED_REGION_SIZE > params->smram_size); + params->smram_size -= CONFIG_IED_REGION_SIZE; + params->ied_base = tsegmb + tseg_size - CONFIG_IED_REGION_SIZE; + params->ied_size = CONFIG_IED_REGION_SIZE; + } /* Adjust available SMM handler memory size. */ - if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) + if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) { + ASSERT(CONFIG_SMM_RESERVED_SIZE > params->smram_size); params->smram_size -= CONFIG_SMM_RESERVED_SIZE; + } if (IS_ALIGNED(tsegmb, tseg_size)) { /* SMRR has 32-bits of valid address aligned to 4KiB. */ @@ -264,7 +274,8 @@ /* enable the SMM memory window */ northbridge_write_smram(D_OPEN | G_SMRAME | C_BASE_SEG); - setup_ied_area(&smm_reloc_params); + if (CONFIG_IED_REGION_SIZE != 0) + setup_ied_area(&smm_reloc_params); num_cpus = cpu_get_apic_id_map(apic_id_map); if (num_cpus > CONFIG_MAX_CPUS) { -- To view, visit https://review.coreboot.org/27872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1aadc6f0459a8035864dcf02b0a07e00b284fe2a Gerrit-Change-Number: 27872 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/*: Account for cbmem_top alignment
by Arthur Heymans (Code Review) 06 Aug '18

06 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27871 Change subject: nb/intel/*: Account for cbmem_top alignment ...................................................................... nb/intel/*: Account for cbmem_top alignment Having cbmem floating between two ram regions is a bad idea and some payloads (e.g. tianocore) even bail out on this. To overcome this issue mark the region between tom and cbmem as uma. Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/x4x/northbridge.c 4 files changed, 49 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/27871/1 diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index e14f843..d946553 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <console/console.h> #include <arch/io.h> #include <stdint.h> @@ -72,7 +73,7 @@ static void mch_domain_read_resources(struct device *dev) { u64 tom, touud; - u32 tomk, tolud, uma_sizek = 0; + u32 tomk, tolud, uma_sizek = 0, delta_cbmem; u32 pcie_config_base, pcie_config_size; /* Total Memory 2GB example: @@ -138,6 +139,15 @@ tomk -= tseg_sizek; uma_sizek += tseg_sizek; + /* cbmem_top can be shifted downwards due to aligment. + Mark the region between cbmem_top and tomk as unusable */ + delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + tomk -= delta_cbmem; + uma_sizek += delta_cbmem; + + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", + delta_cbmem); + printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); /* Report the memory regions */ diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index d3539b8..b6e1515 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <console/console.h> #include <arch/io.h> #include <stdint.h> @@ -62,7 +63,7 @@ uint32_t pci_tolm, tseg_sizek; uint8_t tolud; uint16_t reg16; - unsigned long long tomk, tomk_stolen; + unsigned long long tomk, tomk_stolen, cbmem_topk, delta_cbmem; uint64_t uma_memory_base = 0, uma_memory_size = 0; uint64_t tseg_memory_base = 0, tseg_memory_size = 0; @@ -102,6 +103,17 @@ tseg_memory_base = tomk_stolen * 1024ULL; tseg_memory_size = tseg_sizek * 1024ULL; + /* cbmem_top can be shifted downwards due to aligment. + Mark the region between cbmem_top and tomk as unusable */ + cbmem_topk = ((uint32_t)cbmem_top() >> 10); + delta_cbmem = tomk_stolen - cbmem_topk; + tomk_stolen -= delta_cbmem; + uma_sizek += delta_cbmem; + + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", + delta_cbmem); + + /* The following needs to be 2 lines, otherwise the second * number is always 0 */ @@ -113,6 +125,7 @@ ram_resource(dev, 4, 768, (tomk - 768)); uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10); mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10); + uma_resource(dev, 7, cbmem_topk, delta_cbmem); assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 4775b15..0c04b35 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <console/console.h> #include <arch/io.h> #include <stdint.h> @@ -55,7 +56,7 @@ { u64 tom, touud; u32 tomk, tolud, tseg_sizek; - u32 pcie_config_base, pcie_config_size; + u32 pcie_config_base, pcie_config_size, delta_cbmem; u16 index; const u32 top32memk = 4 * (GiB / KiB); @@ -100,6 +101,17 @@ /* Subtract TSEG size */ tseg_sizek = gtt_basek - tseg_basek; tomk -= tseg_sizek; + printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek >> 10); + + /* cbmem_top can be shifted downwards due to aligment. + Mark the region between cbmem_top and tomk as unusable */ + delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + tomk -= delta_cbmem; + uma_sizek += delta_cbmem; + + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n", + delta_cbmem); + /* Report the memory regions */ ram_resource(dev, index++, 0, 640); diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index d1926b2..aba5c54 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <console/console.h> #include <arch/io.h> #include <stdint.h> @@ -35,7 +36,7 @@ { u8 index, reg8; u64 tom, touud; - u32 tomk, tseg_sizek = 0, tolud; + u32 tomk, tseg_sizek = 0, tolud, delta_cbmem; u32 pcie_config_base, pcie_config_size; u32 uma_sizek = 0; @@ -100,6 +101,15 @@ printk(BIOS_DEBUG, "%dM\n", tseg_sizek >> 10); + /* cbmem_top can be shifted downwards due to aligment. + Mark the region between cbmem_top and tomk as unusable */ + delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + tomk -= delta_cbmem; + uma_sizek += delta_cbmem; + + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", + delta_cbmem); + printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); /* Report the memory regions */ -- To view, visit https://review.coreboot.org/27871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 Gerrit-Change-Number: 27871 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: cpu/intel/smm: Make sure SMRR base is aligned to SMRR size
by Arthur Heymans (Code Review) 06 Aug '18

06 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27870 Change subject: cpu/intel/smm: Make sure SMRR base is aligned to SMRR size ...................................................................... cpu/intel/smm: Make sure SMRR base is aligned to SMRR size If TSEG_BASE is not TSEG_SIZE aligned the SMRR settings are invalid, therefore guard against this. Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/smm/gen1/smmrelocate.c 1 file changed, 19 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/27870/1 diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index b48fe00..a298985 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -160,20 +160,26 @@ if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) params->smram_size -= CONFIG_SMM_RESERVED_SIZE; - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - struct cpuinfo_x86 c; + if (IS_ALIGNED(tsegmb, tseg_size)) { + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + struct cpuinfo_x86 c; - /* On model_6fx and model_1067x bits [0:11] on smrr_base are reserved */ - get_fms(&c, cpuid_eax(1)); - if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17)) - params->smrr_base.lo = (params->smram_base & rmask); - else - params->smrr_base.lo = (params->smram_base & rmask) - | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; + /* On model_6fx and model_1067x bits [0:11] on smrr_base + are reserved */ + get_fms(&c, cpuid_eax(1)); + if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17)) + params->smrr_base.lo = (params->smram_base & rmask); + else + params->smrr_base.lo = (params->smram_base & rmask) + | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~((1 << 20) - 1) & rmask) + | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; + } else { + printk(BIOS_WARNING, + "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); + } } static int install_relocation_handler(int *apic_id_map, int num_cpus, -- To view, visit https://review.coreboot.org/27870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315 Gerrit-Change-Number: 27870 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mb: Get rid of unneeded include <cbmem.h>
by Elyes HAOUAS (Code Review) 06 Aug '18

06 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27869 Change subject: mb: Get rid of unneeded include <cbmem.h> ...................................................................... mb: Get rid of unneeded include <cbmem.h> Change-Id: I80dd65484fd52e9048635091fb20a123e959e999 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/adi/rcc-dff/acpi_tables.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/esd/atom15/acpi_tables.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/google/beltino/acpi_tables.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/daisy/mainboard.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/acpi_tables.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/peach_pit/mainboard.c M src/mainboard/google/rambi/acpi_tables.c M src/mainboard/google/stout/acpi_tables.c M src/mainboard/google/stout/romstage.c M src/mainboard/intel/baskingridge/acpi_tables.c M src/mainboard/intel/bayleybay_fsp/acpi_tables.c M src/mainboard/intel/bayleybay_fsp/romstage.c M src/mainboard/intel/cougar_canyon2/acpi_tables.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/intel/emeraldlake2/acpi_tables.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/intel/harcuvar/acpi_tables.c M src/mainboard/intel/littleplains/acpi_tables.c M src/mainboard/intel/minnowmax/acpi_tables.c M src/mainboard/intel/mohonpeak/acpi_tables.c M src/mainboard/intel/stargo2/acpi_tables.c M src/mainboard/intel/stargo2/romstage.c M src/mainboard/intel/strago/acpi_tables.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x230/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/mainboard/samsung/lumpy/acpi_tables.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/acpi_tables.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/scaleway/tagada/acpi_tables.c M src/mainboard/siemens/mc_tcu3/acpi_tables.c M src/mainboard/siemens/mc_tcu3/romstage.c 52 files changed, 0 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27869/1 diff --git a/src/mainboard/adi/rcc-dff/acpi_tables.c b/src/mainboard/adi/rcc-dff/acpi_tables.c index 0f99d9b..fc1f5e4 100644 --- a/src/mainboard/adi/rcc-dff/acpi_tables.c +++ b/src/mainboard/adi/rcc-dff/acpi_tables.c @@ -16,7 +16,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index bbd5ad0..d8930c3 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/lapic.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include "cbmem.h" #include "superio/fintek/f81216h/f81216h.h" #define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1) diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 79cc35d..19e62d3 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -25,7 +25,6 @@ #include <cpu/intel/romstage.h> #include <cpu/x86/lapic.h> #include <lib.h> -#include <cbmem.h> #include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 49a44d9..90df5390 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -27,7 +27,6 @@ #include <superio/nuvoton/common/nuvoton.h> #include <lib.h> #include <arch/stages.h> -#include <cbmem.h> #include <northbridge/intel/x4x/iomap.h> #include <device/pnp_def.h> #include <timestamp.h> diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index e1725d0..35f7208 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -25,7 +25,6 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <arch/acpi.h> -#include <cbmem.h> #include <timestamp.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> diff --git a/src/mainboard/esd/atom15/acpi_tables.c b/src/mainboard/esd/atom15/acpi_tables.c index 6b97660..f66dace 100644 --- a/src/mainboard/esd/atom15/acpi_tables.c +++ b/src/mainboard/esd/atom15/acpi_tables.c @@ -16,7 +16,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <lib.h> // hexdump #include <console/console.h> #include <arch/acpi.h> diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index e58ef1b..7498247 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -22,7 +22,6 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <arch/acpi.h> -#include <cbmem.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 926a5a7..56ef561 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -24,7 +24,6 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <arch/acpi.h> -#include <cbmem.h> #include <timestamp.h> #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index ac336e4..13c888e 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -29,7 +29,6 @@ #include <superio/ite/common/ite.h> #include <lib.h> #include <arch/stages.h> -#include <cbmem.h> #include <northbridge/intel/x4x/iomap.h> #include <timestamp.h> diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index 86a25fc..3e9f2ad 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <cbmem.h> #include <string.h> #include <types.h> #include <arch/acpi.h> diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 3ef4659..b6f9263 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -24,7 +24,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index b6c5518..52cb329 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -16,7 +16,6 @@ #include <arch/cache.h> #include <boot/coreboot_tables.h> #include <console/console.h> -#include <cbmem.h> #include <delay.h> #include <device/device.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 0c6a372..cbea4c2 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -15,7 +15,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index d7bf7c1..e095254 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -25,7 +25,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index ae36ba0..9330bd1 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -15,7 +15,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 782d6e5..b5b084b 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -24,7 +24,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index d94b8c6..10f1506 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -15,7 +15,6 @@ #include <arch/cache.h> #include <boot/coreboot_tables.h> -#include <cbmem.h> #include <console/console.h> #include <delay.h> #include <device/device.h> diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index 9abdbf5..f062a3d 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -15,7 +15,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 078cba2..eb48cac 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -15,7 +15,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index f64e012..20914ec 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -24,7 +24,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index e3a52fa..b9dd015 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -15,7 +15,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> diff --git a/src/mainboard/intel/bayleybay_fsp/acpi_tables.c b/src/mainboard/intel/bayleybay_fsp/acpi_tables.c index df7338b..afc50a0 100644 --- a/src/mainboard/intel/bayleybay_fsp/acpi_tables.c +++ b/src/mainboard/intel/bayleybay_fsp/acpi_tables.c @@ -16,7 +16,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c index 56ca33a..d988023 100644 --- a/src/mainboard/intel/bayleybay_fsp/romstage.c +++ b/src/mainboard/intel/bayleybay_fsp/romstage.c @@ -21,7 +21,6 @@ #include <arch/cbfs.h> #include <arch/stages.h> #include <console/console.h> -#include <cbmem.h> #include <cpu/x86/mtrr.h> #include <romstage_handoff.h> #include <timestamp.h> diff --git a/src/mainboard/intel/cougar_canyon2/acpi_tables.c b/src/mainboard/intel/cougar_canyon2/acpi_tables.c index 406184f..40771df 100644 --- a/src/mainboard/intel/cougar_canyon2/acpi_tables.c +++ b/src/mainboard/intel/cougar_canyon2/acpi_tables.c @@ -15,7 +15,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <arch/acpi.h> #include <arch/ioapic.h> #include <arch/acpigen.h> diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index ed2a234..b1df349 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -25,7 +25,6 @@ #include <superio/winbond/common/winbond.h> #include <lib.h> #include <arch/stages.h> -#include <cbmem.h> #include <northbridge/intel/x4x/iomap.h> #include <device/pnp_def.h> #include <timestamp.h> diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 92ded3c..b48e12b 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -15,7 +15,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <arch/acpi.h> #include <arch/ioapic.h> #include <arch/acpigen.h> diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index bdda191..fcb2b2c 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -24,7 +24,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <superio/smsc/sio1007/chip.h> #include <northbridge/intel/sandybridge/sandybridge.h> diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index acbdb30..4abde90 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> diff --git a/src/mainboard/intel/littleplains/acpi_tables.c b/src/mainboard/intel/littleplains/acpi_tables.c index 0f99d9b..fc1f5e4 100644 --- a/src/mainboard/intel/littleplains/acpi_tables.c +++ b/src/mainboard/intel/littleplains/acpi_tables.c @@ -16,7 +16,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> diff --git a/src/mainboard/intel/minnowmax/acpi_tables.c b/src/mainboard/intel/minnowmax/acpi_tables.c index 6b97660..f66dace 100644 --- a/src/mainboard/intel/minnowmax/acpi_tables.c +++ b/src/mainboard/intel/minnowmax/acpi_tables.c @@ -16,7 +16,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <lib.h> // hexdump #include <console/console.h> #include <arch/acpi.h> diff --git a/src/mainboard/intel/mohonpeak/acpi_tables.c b/src/mainboard/intel/mohonpeak/acpi_tables.c index 0f99d9b..fc1f5e4 100644 --- a/src/mainboard/intel/mohonpeak/acpi_tables.c +++ b/src/mainboard/intel/mohonpeak/acpi_tables.c @@ -16,7 +16,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> diff --git a/src/mainboard/intel/stargo2/acpi_tables.c b/src/mainboard/intel/stargo2/acpi_tables.c index c2c729b..54debd7 100644 --- a/src/mainboard/intel/stargo2/acpi_tables.c +++ b/src/mainboard/intel/stargo2/acpi_tables.c @@ -15,7 +15,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> diff --git a/src/mainboard/intel/stargo2/romstage.c b/src/mainboard/intel/stargo2/romstage.c index ff90e2e..b873aca 100644 --- a/src/mainboard/intel/stargo2/romstage.c +++ b/src/mainboard/intel/stargo2/romstage.c @@ -26,7 +26,6 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <pc80/mc146818rtc.h> -#include <cbmem.h> #include <console/console.h> #include <halt.h> #include <reset.h> diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index c6c9b52..f8dc821 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -18,7 +18,6 @@ #include <arch/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 35ba78e..a06a6e8 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -15,7 +15,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 2a674a5..32575c8 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -24,7 +24,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index d752840..9f0c4d9 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -26,7 +26,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 18470ea..af79980 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -25,7 +25,6 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <arch/acpi.h> -#include <cbmem.h> #include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index 029d867..49ed6b2 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -27,7 +27,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index d4c60dd..1b49eb8 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -34,7 +34,6 @@ #include <delay.h> #include <timestamp.h> #include <arch/acpi.h> -#include <cbmem.h> #include "dock.h" #include "arch/early_variables.h" diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 1a7decc..fb0494c 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -26,7 +26,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 0eac15a..1cdce8c 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -25,7 +25,6 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <arch/acpi.h> -#include <cbmem.h> #include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index ffb72e3..cd5b25b 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -25,7 +25,6 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <arch/acpi.h> -#include <cbmem.h> #include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 3538647..676c051 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -34,7 +34,6 @@ #include <delay.h> #include <timestamp.h> #include <arch/acpi.h> -#include <cbmem.h> #include "arch/early_variables.h" #include <southbridge/intel/ibexpeak/pch.h> diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index b4611f5..7f233e8 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -24,7 +24,6 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <arch/acpi.h> -#include <cbmem.h> #include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 06fa0fd..62284f1 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -15,7 +15,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <arch/acpi.h> #include <arch/ioapic.h> #include <arch/acpigen.h> diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 3f655da..ba25d54 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -25,7 +25,6 @@ #include <pc80/mc146818rtc.h> #include <cbfs.h> #include <arch/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <bootmode.h> #include <northbridge/intel/sandybridge/sandybridge.h> diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index a518d18..d57ec9d 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -15,7 +15,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <arch/acpi.h> #include <arch/ioapic.h> #include <arch/acpigen.h> diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index ffaff42..5f56a3e 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -24,7 +24,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <bootmode.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index acbdb30..4abde90 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> diff --git a/src/mainboard/siemens/mc_tcu3/acpi_tables.c b/src/mainboard/siemens/mc_tcu3/acpi_tables.c index df7338b..afc50a0 100644 --- a/src/mainboard/siemens/mc_tcu3/acpi_tables.c +++ b/src/mainboard/siemens/mc_tcu3/acpi_tables.c @@ -16,7 +16,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c index 15d949e..628e88b 100644 --- a/src/mainboard/siemens/mc_tcu3/romstage.c +++ b/src/mainboard/siemens/mc_tcu3/romstage.c @@ -21,7 +21,6 @@ #include <arch/cbfs.h> #include <arch/stages.h> #include <console/console.h> -#include <cbmem.h> #include <cpu/x86/mtrr.h> #include <romstage_handoff.h> #include <timestamp.h> -- To view, visit https://review.coreboot.org/27869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I80dd65484fd52e9048635091fb20a123e959e999 Gerrit-Change-Number: 27869 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/kontron/ktqm77: Use common pnp_{enter, exit} functions
by Elyes HAOUAS (Code Review) 06 Aug '18

06 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27868 Change subject: mb/kontron/ktqm77: Use common pnp_{enter,exit} functions ...................................................................... mb/kontron/ktqm77: Use common pnp_{enter,exit} functions Change-Id: Ib5799cceacefa89385a7615ef1c4b4d06157044f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/kontron/ktqm77/romstage.c 1 file changed, 3 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27868/1 diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 2a674a5..4afcebb 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -18,7 +18,6 @@ #include <string.h> #include <lib.h> #include <timestamp.h> -#include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> @@ -34,6 +33,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> +#include <superio/winbond/common/winbond.h> void pch_enable_lpc(void) { @@ -62,25 +62,12 @@ RCBA32(FD) = reg32; } -static void pnp_enter_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - void mainboard_config_superio(void) { int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */ int dis_bl_inv = 1; /* backlight inversion: 1 = disabled, 0 = enabled */ pnp_devfn_t dev = PNP_DEV(0x2e, 0x9); - pnp_enter_ext_func_mode(dev); + pnp_enter_conf_state(dev); pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */ pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */ pnp_write_config(dev, 0x2a, 0x01); /* Pins 62, 63, 65, 66 are @@ -94,7 +81,7 @@ pnp_write_config(dev, 0xe3, 0xdd); /* GPIO2 bits 1, 5 are output */ pnp_write_config(dev, 0xe4, (dis_bl_inv << 5) | (lvds_3v << 1)); /* GPIO2 bits 1, 5 */ pnp_write_config(dev, 0xf3, 0x40); /* Disable suspend LED during normal operation */ - pnp_exit_ext_func_mode(dev); + pnp_exit_conf_state(dev); } void mainboard_fill_pei_data(struct pei_data *pei_data) -- To view, visit https://review.coreboot.org/27868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib5799cceacefa89385a7615ef1c4b4d06157044f Gerrit-Change-Number: 27868 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: mb/asus/kfsn4-dre: Use common pnp_{enter, exit} functions
by Elyes HAOUAS (Code Review) 06 Aug '18

06 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27867 Change subject: mb/asus/kfsn4-dre: Use common pnp_{enter,exit} functions ...................................................................... mb/asus/kfsn4-dre: Use common pnp_{enter,exit} functions Change-Id: I4b0577bf3c00307733a1096749c1835d86764f29 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asus/kfsn4-dre/romstage.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/27867/1 diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 2809f0f..cc198c6 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -343,9 +343,7 @@ /* Initialize GPIO */ /* Access SuperIO GPI03 logical device */ - uint16_t port = GPIO3_DEV >> 8; - outb(0x87, port); - outb(0x87, port); + pnp_enter_conf_state(GPIO3_DEV); pnp_set_logical_device(GPIO3_DEV); /* Set GP37 (power LED) to output */ pnp_write_config(GPIO3_DEV, 0xf0, 0x7f); @@ -355,7 +353,7 @@ uint8_t cr2c = pnp_read_config(GPIO3_DEV, 0x2c); pnp_write_config(GPIO3_DEV, 0x2c, (cr2c & 0xf3) | 0x04); /* Restore default SuperIO access */ - outb(0xaa, port); + pnp_exit_conf_state(GPIO3_DEV); } /** -- To view, visit https://review.coreboot.org/27867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4b0577bf3c00307733a1096749c1835d86764f29 Gerrit-Change-Number: 27867 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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coreboot-gerrit August 2018