coreboot-gerrit August 2018

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Change in coreboot[master]: soc/amd/stoneyridge: Prevent reboot in romstage
by Raul Rangel (Code Review) 06 Aug '18

06 Aug '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/27876 ) Change subject: soc/amd/stoneyridge: Prevent reboot in romstage ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/#/c/27876/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27876/1//COMMIT_MSG@7 PS1, Line 7: Prevent reboot in romstage > Maybe change this to what it does? This description is just ASKING for trouble. […] Done https://review.coreboot.org/#/c/27876/1/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/27876/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 609: = > You don't really need to or the bit in either here or below, do you? Done https://review.coreboot.org/#/c/27876/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 614: // Undocumented register > This might be the spot to mention that it's an undocumented register. Done https://review.coreboot.org/#/c/27876/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 615: = misc_r > use BIT(16) from types. […] Done -- To view, visit https://review.coreboot.org/27876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e Gerrit-Change-Number: 27876 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Aug 2018 16:38:49 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Prevent reboot in romstage
by Raul Rangel (Code Review) 06 Aug '18

06 Aug '18

Hello Garrett Kirkendall, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27876 to look at the new patch set (#2). Change subject: soc/amd/stoneyridge: Prevent reboot in romstage ...................................................................... soc/amd/stoneyridge: Prevent reboot in romstage By setting this register in bootblock AmdInitEnv will no longer trigger a reset in romstage. This fixes a few vboot test failures and also speeds up boot time. BUG=b:111610455 TEST=Built grunt and made sure bootblock only happens once on cold boot, and S3 resume. Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/soc/amd/stoneyridge/southbridge.c 1 file changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/27876/2 -- To view, visit https://review.coreboot.org/27876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e Gerrit-Change-Number: 27876 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge: Set undocumented misc register
by Martin Roth (Code Review) 06 Aug '18

06 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27876 ) Change subject: soc/amd/stoneyridge: Set undocumented misc register ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/27876/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27876/1//COMMIT_MSG@7 PS1, Line 7: Set undocumented misc register Maybe change this to what it does? This description is just ASKING for trouble. soc/amd/stoneyridge: Prevent reboot in romstage https://review.coreboot.org/#/c/27876/1/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/27876/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 609: | You don't really need to or the bit in either here or below, do you? https://review.coreboot.org/#/c/27876/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 614: uint32_t reg = misc_read32(0x50); This might be the spot to mention that it's an undocumented register. https://review.coreboot.org/#/c/27876/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 615: (1 << 16) use BIT(16) from types.h? -- To view, visit https://review.coreboot.org/27876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e Gerrit-Change-Number: 27876 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Aug 2018 16:32:11 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Set undocumented misc register
by Raul Rangel (Code Review) 06 Aug '18

06 Aug '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27876 Change subject: soc/amd/stoneyridge: Set undocumented misc register ...................................................................... soc/amd/stoneyridge: Set undocumented misc register By setting this register in bootblock AmdInitEnv will no longer trigger a reset in romstage. This fixes a few vboot test failures and also speeds up boot time. BUG=b:111610455 TEST=Built grunt and made sure bootblock only happens once on cold boot, and S3 resume. Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/soc/amd/stoneyridge/southbridge.c 1 file changed, 21 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/27876/1 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 348d5f1..c75aefd 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -556,7 +556,7 @@ } } -static void setup_spread_spectrum(void) +static void setup_spread_spectrum(int *reboot) { uint16_t rstcfg = pm_read16(PWR_RESET_CFG); @@ -606,11 +606,24 @@ cntl1 |= CG1PLL_FBDIV_TEST; misc_write32(MISC_CLK_CNTL1, cntl1); - soft_reset(); + *reboot |= 1; +} + +static void setup_misc(int *reboot) +{ + uint32_t reg = misc_read32(0x50); + if (!(reg & (1 << 16))) { + reg |= 1 << 16; + + misc_write32(0x50, reg); + *reboot |= 1; + } } void bootblock_fch_early_init(void) { + int reboot = 0; + sb_enable_rom(); sb_lpc_port80(); sb_lpc_decode(); @@ -619,7 +632,12 @@ sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ sb_acpi_mmio_decode(); sb_enable_cf9_io(); - setup_spread_spectrum(); + setup_spread_spectrum(&reboot); + setup_misc(&reboot); + + if (reboot) + soft_reset(); + sb_enable_legacy_io(); enable_aoac_devices(); } -- To view, visit https://review.coreboot.org/27876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e Gerrit-Change-Number: 27876 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: src: Fix typo
by Martin Roth (Code Review) 06 Aug '18

06 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27875 ) Change subject: src: Fix typo ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882 Gerrit-Change-Number: 27875 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 06 Aug 2018 15:50:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src: Fix typo
by Elyes HAOUAS (Code Review) 06 Aug '18

06 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27875 Change subject: src: Fix typo ...................................................................... src: Fix typo Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/google/chromeec/ec_commands.h M src/northbridge/intel/gm45/ram_calc.c M src/northbridge/intel/i945/ram_calc.c M src/northbridge/intel/pineview/ram_calc.c M src/northbridge/intel/x4x/ram_calc.c 5 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/27875/1 diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 730be09..bafaa89 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -426,7 +426,7 @@ * parent structure that the alignment will still be true given the packing of * the parent structure. This is particularly important if the sub-structure * will be passed as a pointer to another function, since that function will - * not know about the misaligment caused by the parent structure's packing. + * not know about the misalignment caused by the parent structure's packing. * * Also be very careful using __packed - particularly when nesting non-packed * structures inside packed ones. In fact, DO NOT use __packed directly; diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 0e95341..5af3e16 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -107,7 +107,7 @@ } /* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 15ba7f4..7ee7198 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -59,7 +59,7 @@ } /* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index d116709..62855c2 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -95,7 +95,7 @@ } /* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 49afdc3..1f1c13f 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -93,7 +93,7 @@ } /* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) -- To view, visit https://review.coreboot.org/27875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882 Gerrit-Change-Number: 27875 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: docker/coreboot.org-status: provide html/head/body frame
by Jonathan Neuschäfer (Code Review) 06 Aug '18

06 Aug '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/27874 ) Change subject: docker/coreboot.org-status: provide html/head/body frame ...................................................................... Patch Set 1: Code-Review+1 Thanks! -- To view, visit https://review.coreboot.org/27874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic9a12a13f11fd22eeec96fbcca6b706312876b07 Gerrit-Change-Number: 27874 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Comment-Date: Mon, 06 Aug 2018 15:34:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Add support for LPDDR4 nWR setting
by build bot (Jenkins) (Code Review) 06 Aug '18

06 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27850 ) Change subject: soc/intel/apollolake: Add support for LPDDR4 nWR setting ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/27850/2/src/soc/intel/apollolake/meminit.c File src/soc/intel/apollolake/meminit.c: https://review.coreboot.org/#/c/27850/2/src/soc/intel/apollolake/meminit.c@… PS2, Line 361: */ code indent should use tabs where possible https://review.coreboot.org/#/c/27850/2/src/soc/intel/apollolake/meminit.c@… PS2, Line 361: */ please, no space before tabs -- To view, visit https://review.coreboot.org/27850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1147538f72f4e2f14e32f3657c05f1f505a56fbf Gerrit-Change-Number: 27850 Gerrit-PatchSet: 2 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Aug 2018 15:32:59 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: docker/coreboot.org-status: provide html/head/body frame
by Patrick Georgi (Code Review) 06 Aug '18

06 Aug '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/27874 Change subject: docker/coreboot.org-status: provide html/head/body frame ...................................................................... docker/coreboot.org-status: provide html/head/body frame This allows us to add encoding information. Change-Id: Ic9a12a13f11fd22eeec96fbcca6b706312876b07 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- M util/docker/coreboot.org-status/board-status.html/tohtml.sh 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/27874/1 diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index b1a7ccd..f786c33 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -3,6 +3,16 @@ export GIT_DIR="$COREBOOT_DIR/.git" CODE_GITWEB="https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=" STATUS_GITWEB="https://review.coreboot.org/gitweb/cgit/board-status.git/tree/" + +cat <<EOF +<html> +<head> + <meta charset="utf-8"> + <title>status report for coreboot boards</title> +</head> +<body> +EOF + if [ -f `dirname $0`/foreword.html ]; then cat `dirname $0`/foreword.html fi @@ -519,3 +529,7 @@ echo "$detailed" +cat <<EOF +</body> +</html> +EOF -- To view, visit https://review.coreboot.org/27874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic9a12a13f11fd22eeec96fbcca6b706312876b07 Gerrit-Change-Number: 27874 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: cpu/intel/smm: Make sure SMRR base is aligned to SMRR size
by Arthur Heymans (Code Review) 06 Aug '18

06 Aug '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27870 ) Change subject: cpu/intel/smm: Make sure SMRR base is aligned to SMRR size ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27870/1/src/cpu/intel/smm/gen1/smmrelocate.c File src/cpu/intel/smm/gen1/smmrelocate.c: https://review.coreboot.org/#/c/27870/1/src/cpu/intel/smm/gen1/smmrelocate.… PS1, Line 176: (1 << 20) > is it intended hat you replace tseg_size with this constant? oh this accidentally entered. thx for spotting. -- To view, visit https://review.coreboot.org/27870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315 Gerrit-Change-Number: 27870 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 06 Aug 2018 14:51:27 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit August 2018