coreboot-gerrit August 2018

coreboot-gerrit@coreboot.org

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1120 discussions

Change in coreboot[master]: mb/google/poppy/variants/nautilus: Add SKU info to SMBIOS
by Furquan Shaikh (Code Review) 04 Aug '18

04 Aug '18

Furquan Shaikh has abandoned this change. ( https://review.coreboot.org/27826 ) Change subject: mb/google/poppy/variants/nautilus: Add SKU info to SMBIOS ...................................................................... Abandoned Seems like this CL got uploaded twice. -- To view, visit https://review.coreboot.org/27826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I48d26a112da20149876cc2e2e1538de901982818 Gerrit-Change-Number: 27826 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mb/google/kahlee: Disable SATA in all boards
by Richard Spiegel (Code Review) 03 Aug '18

03 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27849 Change subject: mb/google/kahlee: Disable SATA in all boards ...................................................................... mb/google/kahlee: Disable SATA in all boards Kahlee based boards don't use SATA, so disable SATA on all boards to save power. BUG=b:112139043 TEST=Buil and boot grunt, checked the absence of SATA PCI. Change-Id: I6a12c03a5a95b1c8b40609a3fe656df92548b80b Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/variants/aleena/devicetree.cb M src/mainboard/google/kahlee/variants/careena/devicetree.cb M src/mainboard/google/kahlee/variants/grunt/devicetree.cb M src/mainboard/google/kahlee/variants/liara/devicetree.cb 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/27849/1 diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb index 3863100..b330ec5 100644 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb @@ -73,7 +73,7 @@ device pci 9.0 on end # PCIe Host Bridge device pci 9.2 on end # HDA device pci 10.0 on end # xHCI - device pci 11.0 on end # SATA + device pci 11.0 off end # SATA device pci 12.0 on end # EHCI device pci 14.0 on # SMbus end # SMbus diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index 2b6041f..61476a2 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -73,7 +73,7 @@ device pci 9.0 on end # PCIe Host Bridge device pci 9.2 on end # HDA device pci 10.0 on end # xHCI - device pci 11.0 on end # SATA + device pci 11.0 off end # SATA device pci 12.0 on end # EHCI device pci 14.0 on # SMbus end # SMbus diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index a5229b4..0a173ac 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -73,7 +73,7 @@ device pci 9.0 on end # PCIe Host Bridge device pci 9.2 on end # HDA device pci 10.0 on end # xHCI - device pci 11.0 on end # SATA + device pci 11.0 off end # SATA device pci 12.0 on end # EHCI device pci 14.0 on # SMbus end # SMbus diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index 3863100..b330ec5 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -73,7 +73,7 @@ device pci 9.0 on end # PCIe Host Bridge device pci 9.2 on end # HDA device pci 10.0 on end # xHCI - device pci 11.0 on end # SATA + device pci 11.0 off end # SATA device pci 12.0 on end # EHCI device pci 14.0 on # SMbus end # SMbus -- To view, visit https://review.coreboot.org/27849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6a12c03a5a95b1c8b40609a3fe656df92548b80b Gerrit-Change-Number: 27849 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Enable GbE support
by Lijian Zhao (Code Review) 03 Aug '18

03 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27848 to look at the new patch set (#3). Change subject: mb/intel/coffeelake_rvp: Enable GbE support ...................................................................... mb/intel/coffeelake_rvp: Enable GbE support Enable Gigabit Ethernet network controller on whiskey lake rvp platform, add NVM bin file as well. BUG=N/A TEST=Build and boot up into chromeos on whiskey lake rvp platform, and check eth0 can get IP address assigned, Change-Id: Ia299a2aa78108175074e084cc34a7d2b38cf1c72 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/27848/3 -- To view, visit https://review.coreboot.org/27848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia299a2aa78108175074e084cc34a7d2b38cf1c72 Gerrit-Change-Number: 27848 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Enable Gbe support
by Lijian Zhao (Code Review) 03 Aug '18

03 Aug '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/27848 Change subject: mb/intel/coffeelake_rvp: Enable Gbe support ...................................................................... mb/intel/coffeelake_rvp: Enable Gbe support Enable Gigabit Ethernet network controller on whiskey lake rvp platform, add NVM bin file as well. BUG=N/A TEST=Build and boot up into chromeos on whiskey lake rvp platform, and check eth0 can get IP address assigned, Change-Id: Ia299a2aa78108175074e084cc34a7d2b38cf1c72 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/27848/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index ef5b3bd..a1f79b1 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -75,6 +75,11 @@ depends on HAVE_EC_BIN default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ec.bin" +config GBE_BIN_PATH + string + depends on HAVE_GBE_BIN + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/gbe.bin" + config DIMM_SPD_SIZE int default 512 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb index 34270cd..dbf358e 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb @@ -130,6 +130,6 @@ device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device pci 1f.6 on end # GbE end end -- To view, visit https://review.coreboot.org/27848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia299a2aa78108175074e084cc34a7d2b38cf1c72 Gerrit-Change-Number: 27848 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Update UPD from device switch
by build bot (Jenkins) (Code Review) 03 Aug '18

03 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27766 ) Change subject: soc/intel/cannonlake: Update UPD from device switch ...................................................................... Patch Set 4: (5 comments) https://review.coreboot.org/#/c/27766/4/src/soc/intel/cannonlake/chip.c File src/soc/intel/cannonlake/chip.c: https://review.coreboot.org/#/c/27766/4/src/soc/intel/cannonlake/chip.c@253 PS4, Line 253: params->Usb2AfePredeemp[i] = config->usb2_ports[i].tx_emp_enable; line over 80 characters https://review.coreboot.org/#/c/27766/4/src/soc/intel/cannonlake/chip.c@262 PS4, Line 262: params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; line over 80 characters https://review.coreboot.org/#/c/27766/4/src/soc/intel/cannonlake/chip.c@266 PS4, Line 266: params->Usb3HsioTxDownscaleAmp[i] = config->usb3_ports[i].tx_downscale_amp; line over 80 characters https://review.coreboot.org/#/c/27766/4/src/soc/intel/cannonlake/chip.c@295 PS4, Line 295: params->PchScsEmmcHs400RxStrobeDll1 = config->EmmcHs400RxStrobeDll1; line over 80 characters https://review.coreboot.org/#/c/27766/4/src/soc/intel/cannonlake/chip.c@296 PS4, Line 296: params->PchScsEmmcHs400TxDataDll = config->EmmcHs400TxDataDll; line over 80 characters -- To view, visit https://review.coreboot.org/27766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9 Gerrit-Change-Number: 27766 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Aug 2018 20:22:08 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: security/tpm: Improve TCPA log generation
by Philipp Deppenwiese (Code Review) 03 Aug '18

03 Aug '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27769 ) Change subject: security/tpm: Improve TCPA log generation ...................................................................... Patch Set 7: @Julius done -- To view, visit https://review.coreboot.org/27769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I215d79eed7ad17c6ab87f0c4b14a282e519ef07d Gerrit-Change-Number: 27769 Gerrit-PatchSet: 7 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Aug 2018 19:35:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src/soc/intel: Add AML IGD in platform reporting
by Furquan Shaikh (Code Review) 03 Aug '18

03 Aug '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27846 ) Change subject: src/soc/intel: Add AML IGD in platform reporting ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id8f8379703abdaa5b14a4337a4fca04b370f3a2a Gerrit-Change-Number: 27846 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Aug 2018 19:12:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: fsp_broadwell_de: Increase CONFIG_MAX_CPUS to 32
by Samuel Jimenez (Code Review) 03 Aug '18

03 Aug '18

Samuel Jimenez has uploaded this change for review. ( https://review.coreboot.org/27847 Change subject: fsp_broadwell_de: Increase CONFIG_MAX_CPUS to 32 ...................................................................... fsp_broadwell_de: Increase CONFIG_MAX_CPUS to 32 Fix to accomodate for boards with more than 16 cores. Change-Id: I35b61d94491c21ef76717f761e566ca815880f27 Signed-off-by: Samuel Jimenez <aerojsam(a)gmail.com> --- M src/mainboard/intel/camelbackmountain_fsp/acpi_tables.c M src/soc/intel/fsp_broadwell_de/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/27847/1 diff --git a/src/mainboard/intel/camelbackmountain_fsp/acpi_tables.c b/src/mainboard/intel/camelbackmountain_fsp/acpi_tables.c index 0197def..3c8d2e8 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/acpi_tables.c +++ b/src/mainboard/intel/camelbackmountain_fsp/acpi_tables.c @@ -36,7 +36,7 @@ current = acpi_madt_irq_overrides(current); - for (i = 0; i < 16; i++) + for (i = 0; i < CONFIG_MAX_CPUS; i++) current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, i, 0xD, 1); return current; diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index cb0228e..cc3e6e2 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -49,7 +49,7 @@ config MAX_CPUS int - default 16 + default 32 config CPU_ADDR_BITS int -- To view, visit https://review.coreboot.org/27847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I35b61d94491c21ef76717f761e566ca815880f27 Gerrit-Change-Number: 27847 Gerrit-PatchSet: 1 Gerrit-Owner: Samuel Jimenez <aerojsam(a)gmail.com>

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Change in coreboot[master]: src/soc/intel: Add AML IGD in platform reporting
by Subrata Banik (Code Review) 03 Aug '18

03 Aug '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/27846 ) Change subject: src/soc/intel: Add AML IGD in platform reporting ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id8f8379703abdaa5b14a4337a4fca04b370f3a2a Gerrit-Change-Number: 27846 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Aug 2018 18:56:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/soc/intel: Add AML IGD in platform reporting
by Gaggery Tsai (Code Review) 03 Aug '18

03 Aug '18

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/27846 Change subject: src/soc/intel: Add AML IGD in platform reporting ...................................................................... src/soc/intel: Add AML IGD in platform reporting This patch revises IGD naming and adds AML IGD in platform reporting. BUG=None BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage & Ensure AML IGD is shown in platform reporting. Change-Id: Id8f8379703abdaa5b14a4337a4fca04b370f3a2a Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/vr_config.c 4 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/27846/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 40f2ea4..56e70ab 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2868,7 +2868,7 @@ #define PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM 0x5916 #define PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR 0x5917 #define PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM 0x591B -#define PCI_DEVICE_ID_INTEL_KBL_GT2_ULX_R 0x591C +#define PCI_DEVICE_ID_INTEL_AML_GT2_ULX 0x591C #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_505 0x5a84 #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_500 0x5a85 #define PCI_DEVICE_ID_INTEL_GLK_IGD 0x3184 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index c754509..d1023ee 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -123,7 +123,7 @@ PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR, PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, - PCI_DEVICE_ID_INTEL_KBL_GT2_ULX_R, + PCI_DEVICE_ID_INTEL_AML_GT2_ULX, PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM, PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM, PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM, diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 7d5bc3f..a652b52 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -102,6 +102,7 @@ { PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR, "Kabylake-R ULT GT2"}, { PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, "Kabylake HALO GT2" }, { PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, "Kabylake DT GT2" }, + { PCI_DEVICE_ID_INTEL_AML_GT2_ULX, "Amberlake ULX GT2" }, }; static uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index ce40e35..4508fda 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -186,7 +186,7 @@ sku = KBL_R_SKU; else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_Y) { id = get_dev_id(SA_DEV_IGD); - if (id == PCI_DEVICE_ID_INTEL_KBL_GT2_ULX_R) + if (id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) sku = AML_Y_SKU; else sku = KBL_Y_SKU; -- To view, visit https://review.coreboot.org/27846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id8f8379703abdaa5b14a4337a4fca04b370f3a2a Gerrit-Change-Number: 27846 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com>

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coreboot-gerrit August 2018