coreboot-gerrit August 2018

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Change in coreboot[master]: soc/amd/stoneyridge: Disable SATA if not in devicetree
by Richard Spiegel (Code Review) 03 Aug '18

03 Aug '18

Richard Spiegel has abandoned this change. ( https://review.coreboot.org/27821 ) Change subject: soc/amd/stoneyridge: Disable SATA if not in devicetree ...................................................................... Abandoned Duplicated multiple times due to server error. -- To view, visit https://review.coreboot.org/27821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I8a3655f2a9f6ea4e2ecf36961c942c9d163d80f7 Gerrit-Change-Number: 27821 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Disable SATA if not in devicetree
by Richard Spiegel (Code Review) 03 Aug '18

03 Aug '18

Richard Spiegel has abandoned this change. ( https://review.coreboot.org/27820 ) Change subject: soc/amd/stoneyridge: Disable SATA if not in devicetree ...................................................................... Abandoned Duplicated multiple times due to server error. -- To view, visit https://review.coreboot.org/27820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: If5cefe5e34fe4cb3248b4694f1a5edbcc97d831a Gerrit-Change-Number: 27820 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Disable SATA if not in devicetree
by Richard Spiegel (Code Review) 03 Aug '18

03 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27845 Change subject: soc/amd/stoneyridge: Disable SATA if not in devicetree ...................................................................... soc/amd/stoneyridge: Disable SATA if not in devicetree Grunt boards don't use SATA, so it should be disabled to save power. Create a way to check if SATA is present in devicetree, and if not then disable SATA. Use it to disable grunt SATA. BUG=b:112139043 TEST=Buil and boot grunt, checked the absence of SATA PCI. Change-Id: I4a3b5f65e612e8da5bedff0c557a0850f350dfa8 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/variants/grunt/devicetree.cb M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 35 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/27845/1 diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index a5229b4..286f8a5 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -73,7 +73,6 @@ device pci 9.0 on end # PCIe Host Bridge device pci 9.2 on end # HDA device pci 10.0 on end # xHCI - device pci 11.0 on end # SATA device pci 12.0 on end # EHCI device pci 14.0 on # SMbus end # SMbus diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index 430dc45..9b204f0 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -53,6 +53,7 @@ AGESA_STATUS agesa_fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr) { AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; + const struct device *dev = dev_find_slot(0, SATA_DEVFN); if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; @@ -67,19 +68,22 @@ /* SATA configuration */ FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE; - switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { - case SataRaid: - case SataAhci: - case SataAhci7804: - case SataLegacyIde: + if (dev) { + switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { + case SataRaid: + case SataAhci: + case SataAhci7804: + case SataLegacyIde: + FchParams_env->Sata.SataIdeMode = FALSE; + break; + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams_env->Sata.SataIdeMode = TRUE; + break; + } + } else FchParams_env->Sata.SataIdeMode = FALSE; - break; - case SataIde2Ahci: - case SataIde2Ahci7804: - default: /* SataNativeIde */ - FchParams_env->Sata.SataIdeMode = TRUE; - break; - } /* Platform updates */ platform_FchParams_env(FchParams_env); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 63d8806..585321a 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -72,18 +72,32 @@ void SetFchResetParams(FCH_RESET_INTERFACE *params) { + const struct device *dev = dev_find_slot(0, SATA_DEVFN); params->Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE); - params->SataEnable = sb_sata_enable(); - params->IdeEnable = sb_ide_enable(); + if (dev) { + params->SataEnable = sb_sata_enable(); + params->IdeEnable = sb_ide_enable(); + } else { + params->SataEnable = FALSE; + params->IdeEnable = FALSE; + } } void SetFchEnvParams(FCH_INTERFACE *params) { + const struct device *dev = dev_find_slot(0, SATA_DEVFN); params->AzaliaController = AzEnable; params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; - params->SataEnable = is_sata_config(); - params->IdeEnable = !params->SataEnable; - params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == SataLegacyIde); + if (dev) { + params->SataEnable = is_sata_config(); + params->IdeEnable = !params->SataEnable; + params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == + SataLegacyIde); + } else { + params->SataEnable = FALSE; + params->IdeEnable = FALSE; + params->SataIdeMode = FALSE; + } } void SetFchMidParams(FCH_INTERFACE *params) -- To view, visit https://review.coreboot.org/27845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4a3b5f65e612e8da5bedff0c557a0850f350dfa8 Gerrit-Change-Number: 27845 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge/Kconfig: Move selection of SOC_AMD_PSP_SELECTABLE...
by Richard Spiegel (Code Review) 03 Aug '18

03 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27844 Change subject: soc/amd/stoneyridge/Kconfig: Move selection of SOC_AMD_PSP_SELECTABLE_SMU_FW ...................................................................... soc/amd/stoneyridge/Kconfig: Move selection of SOC_AMD_PSP_SELECTABLE_SMU_FW Now that google's modified PSP boot loader is available in coreboot's repository, all stoneyridge boards should use it. Move the selection of SOC_AMD_PSP_SELECTABLE_SMU_FW from mb/google/kahlee to soc/amd/stoneyridge. BUG=b:111428800 TEST=Build and boot grunt. Change-Id: Idf8e348efbc85569aa1163125f412c5242c46eb4 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/Kconfig M src/soc/amd/stoneyridge/Kconfig 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/27844/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index dfae548..5565d57 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -30,7 +30,6 @@ select MAINBOARD_HAS_CHROMEOS select SERIRQ_CONTINUOUS_MODE select STONEYRIDGE_UART - select SOC_AMD_PSP_SELECTABLE_SMU_FW select SOC_AMD_SMU_FANLESS select HAVE_ACPI_RESUME select DRIVERS_GENERIC_BH720 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 7675bce..594d22c 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -66,6 +66,7 @@ select SSE select SSE2 select RTC + select SOC_AMD_PSP_SELECTABLE_SMU_FW config VBOOT select VBOOT_SEPARATE_VERSTAGE -- To view, visit https://review.coreboot.org/27844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idf8e348efbc85569aa1163125f412c5242c46eb4 Gerrit-Change-Number: 27844 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/google/octopus/variants/baseboard: Update Power Limit1
by Sumeet R Pawnikar (Code Review) 03 Aug '18

03 Aug '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/27819 Change subject: mb/google/octopus/variants/baseboard: Update Power Limit1 ...................................................................... mb/google/octopus/variants/baseboard: Update Power Limit1 Update power limit1 value from 8W to 10W. There is an error in the energy calculation for current VR solution on GLK. Experiments show that when power limit1 set to 10W, gained performance improvement with SoC TDP reaches max (6W) power. BUG=b:79779737 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Ic320d442e7401e4be2e8e16d691db4c803f0fdc1 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl 2 files changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/27819/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 9cab69c..b7c7ad2 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -42,11 +42,10 @@ register "gpe0_dw2" = "PMC_GPE_N_95_64" register "gpe0_dw3" = "PMC_GPE_N_63_32" - # PL1 override 8000 mW: Due to error in the energy calculation for + # PL1 override 10000 mW: Due to error in the energy calculation for # current VR solution. Experiments show that SoC TDP max (6W) can - # be reached when RAPL PL1 is set to 8W. - # TODO: Need to tune this value on closed chassis system. - register "tdp_pl1_override_mw" = "8000" + # be reached when RAPL PL1 is set to 10W. + register "tdp_pl1_override_mw" = "10000" # Set RAPL PL2 to 15W. register "tdp_pl2_override_mw" = "15000" diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl index fb5b590..0b26129 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -69,8 +69,7 @@ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 3000, /* PowerLimitMinimum */ - /* TODO: Need to tune this value on closed chassis system. */ - 8000, /* PowerLimitMaximum */ + 10000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ 200 /* StepSize */ -- To view, visit https://review.coreboot.org/27819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic320d442e7401e4be2e8e16d691db4c803f0fdc1 Gerrit-Change-Number: 27819 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Enable spread spectrum in bootblock
by Martin Roth (Code Review) 03 Aug '18

03 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27813 ) Change subject: soc/amd/stoneyridge: Enable spread spectrum in bootblock ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/27813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 Gerrit-Change-Number: 27813 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Aug 2018 14:35:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/grunt: Override BayHub EMMC driving strength
by Martin Roth (Code Review) 03 Aug '18

03 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27816 ) Change subject: google/grunt: Override BayHub EMMC driving strength ...................................................................... Patch Set 2: (1 comment) Did this help for you? When I was testing, it didn't seem to make any difference. https://review.coreboot.org/#/c/27816/2/src/mainboard/google/kahlee/variant… File src/mainboard/google/kahlee/variants/baseboard/mainboard.c: https://review.coreboot.org/#/c/27816/2/src/mainboard/google/kahlee/variant… PS2, Line 43: u32 SDBAR; : u32 BH720_PCR_DATA; lowercase? -- To view, visit https://review.coreboot.org/27816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3db38ff12c566c258895c6643008a0472ca528bb Gerrit-Change-Number: 27816 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Aug 2018 14:27:27 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/amd/gardenia/Kconfig: Enable SATA
by Richard Spiegel (Code Review) 03 Aug '18

03 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27818 Change subject: mb/amd/gardenia/Kconfig: Enable SATA ...................................................................... mb/amd/gardenia/Kconfig: Enable SATA Gardenia was created with SATA enabled, so unless AMD wants to disable it, it needs to be enabled now that soc code disables it by default. BUG=b:112139043 TEST=Tested on grunt by selecting STONEYRIDGE_SATA_ENABLE, build and boot grunt. Verified SATA present, removed code from grunt and pasted it to gardenia. Change-Id: I34dee13079f3194546dc75f8cdcdb0696854b59d Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/amd/gardenia/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/27818/1 diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index f4512f7..d46d1c8 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -23,6 +23,7 @@ select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA + select STONEYRIDGE_SATA_ENABLE config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/27818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I34dee13079f3194546dc75f8cdcdb0696854b59d Gerrit-Change-Number: 27818 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Disable SATA by default
by Richard Spiegel (Code Review) 03 Aug '18

03 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27817 Change subject: soc/amd/stoneyridge: Disable SATA by default ...................................................................... soc/amd/stoneyridge: Disable SATA by default Grunt based boards don't use SATA, so it should be disabled to save power. However, other boards might use, so the change has to be configurable. Create a config parameter that if selected will enable SATA, but if not selected SATA will be disabled. BUG=b:112139043 TEST=Buil and boot grunt, checked the absence of SATA PCI. Change-Id: I33015baff5bbb869c40aa53d3ef316dcec377734 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 38 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/27817/1 diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index 430dc45..bda5367 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -67,19 +67,22 @@ /* SATA configuration */ FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE; - switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { - case SataRaid: - case SataAhci: - case SataAhci7804: - case SataLegacyIde: + if (IS_ENABLED(CONFIG_STONEYRIDGE_SATA_ENABLE)) { + switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { + case SataRaid: + case SataAhci: + case SataAhci7804: + case SataLegacyIde: + FchParams_env->Sata.SataIdeMode = FALSE; + break; + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams_env->Sata.SataIdeMode = TRUE; + break; + } + } else FchParams_env->Sata.SataIdeMode = FALSE; - break; - case SataIde2Ahci: - case SataIde2Ahci7804: - default: /* SataNativeIde */ - FchParams_env->Sata.SataIdeMode = TRUE; - break; - } /* Platform updates */ platform_FchParams_env(FchParams_env); diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 7675bce..305aa83 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -191,6 +191,12 @@ string "AMD public Key" default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin" +config STONEYRIDGE_SATA_ENABLE + bool "Enable Stoney Ridge SATA Controller" + default n + help + Select this option if your board uses SATA. + config STONEYRIDGE_SATA_MODE int "SATA Mode" default 0 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 63d8806..36cfc2b 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -73,17 +73,29 @@ void SetFchResetParams(FCH_RESET_INTERFACE *params) { params->Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE); - params->SataEnable = sb_sata_enable(); - params->IdeEnable = sb_ide_enable(); + if (IS_ENABLED(CONFIG_STONEYRIDGE_SATA_ENABLE)) { + params->SataEnable = sb_sata_enable(); + params->IdeEnable = sb_ide_enable(); + } else { + params->SataEnable = FALSE; + params->IdeEnable = FALSE; + } } void SetFchEnvParams(FCH_INTERFACE *params) { params->AzaliaController = AzEnable; params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; - params->SataEnable = is_sata_config(); - params->IdeEnable = !params->SataEnable; - params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == SataLegacyIde); + if (IS_ENABLED(CONFIG_STONEYRIDGE_SATA_ENABLE)) { + params->SataEnable = is_sata_config(); + params->IdeEnable = !params->SataEnable; + params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == + SataLegacyIde); + } else { + params->SataEnable = FALSE; + params->IdeEnable = FALSE; + params->SataIdeMode = FALSE; + } } void SetFchMidParams(FCH_INTERFACE *params) -- To view, visit https://review.coreboot.org/27817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I33015baff5bbb869c40aa53d3ef316dcec377734 Gerrit-Change-Number: 27817 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/pcengines/apu2: change GPIO setting
by build bot (Jenkins) (Code Review) 03 Aug '18

03 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27665 ) Change subject: mb/pcengines/apu2: change GPIO setting ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/27665/9/src/mainboard/pcengines/apu2/romsta… File src/mainboard/pcengines/apu2/romstage.c: https://review.coreboot.org/#/c/27665/9/src/mainboard/pcengines/apu2/romsta… PS9, Line 116: if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/27665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196 Gerrit-Change-Number: 27665 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: kamran javed <kamrangulhaji315a(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Aug 2018 11:02:41 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit August 2018