coreboot-gerrit August 2018

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Change in coreboot[master]: mb/google/poppy/variants/rammus: add rammus devicetree.cb
by Zhuohao Lee (Code Review) 03 Aug '18

03 Aug '18

Hello build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27808 to look at the new patch set (#2). Change subject: mb/google/poppy/variants/rammus: add rammus devicetree.cb ...................................................................... mb/google/poppy/variants/rammus: add rammus devicetree.cb Use the default value for Iccmax which is specified in vr_config.c. The AcLoadline and DcLoadline keep the poppy value. Besides, the USB 2.0 ports located on the mainboard are set to USB2_PORT_SHORT and the others on the daughterboard are set to USB2_PORT_LONG. Those setting need to be fine tuned later. BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: Icabfac04c94b3d480872c243d811509e274ef122 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> --- M src/mainboard/google/poppy/Kconfig A src/mainboard/google/poppy/variants/rammus/devicetree.cb 2 files changed, 337 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/27808/2 -- To view, visit https://review.coreboot.org/27808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icabfac04c94b3d480872c243d811509e274ef122 Gerrit-Change-Number: 27808 Gerrit-PatchSet: 2 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variants/rammus: add rammus devicetree.cb
by Zhuohao Lee (Code Review) 03 Aug '18

03 Aug '18

Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/27808 ) Change subject: mb/google/poppy/variants/rammus: add rammus devicetree.cb ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/27808/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/rammus/devicetree.cb: https://review.coreboot.org/#/c/27808/1/src/mainboard/google/poppy/variants… PS1, Line 47: 2 > 0? Rammus will use SOC SDIO, so we need to enable this. https://review.coreboot.org/#/c/27808/1/src/mainboard/google/poppy/variants… PS1, Line 82: #| IccMax | 4A | 28A | 24A | 24A | > This is already being set here: https://review.coreboot. […] Thanks for point it out. i will remove the IccMax setting. -- To view, visit https://review.coreboot.org/27808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icabfac04c94b3d480872c243d811509e274ef122 Gerrit-Change-Number: 27808 Gerrit-PatchSet: 1 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Aug 2018 00:03:35 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Enable spread spectrum in bootblock
by Raul Rangel (Code Review) 02 Aug '18

02 Aug '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/27813 ) Change subject: soc/amd/stoneyridge: Enable spread spectrum in bootblock ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/27813/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27813/1//COMMIT_MSG@7 PS1, Line 7: soc/amd/sto > soc/amd/stoneyridge Done https://review.coreboot.org/#/c/27813/1/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/27813/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 610: enable_aoac_devices() > Can this go earlier in this list? I can move it up a bit. Needs to come after ACPI MMIO and CF9 since they are used to setup spread spectrum. -- To view, visit https://review.coreboot.org/27813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 Gerrit-Change-Number: 27813 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 02 Aug 2018 21:58:12 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Enable spread spectrum in bootblock
by build bot (Jenkins) (Code Review) 02 Aug '18

02 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27813 ) Change subject: soc/amd/stoneyridge: Enable spread spectrum in bootblock ...................................................................... Patch Set 2: (6 comments) https://review.coreboot.org/#/c/27813/2/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/27813/2/src/soc/amd/stoneyridge/include/soc… PS2, Line 380: #define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xFFFF << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) line over 80 characters https://review.coreboot.org/#/c/27813/2/src/soc/amd/stoneyridge/include/soc… PS2, Line 382: #define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xFFFF << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) line over 80 characters https://review.coreboot.org/#/c/27813/2/src/soc/amd/stoneyridge/include/soc… PS2, Line 385: #define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xF << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) line over 80 characters https://review.coreboot.org/#/c/27813/2/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/27813/2/src/soc/amd/stoneyridge/southbridge… PS2, Line 579: cfg5 |= (0x2 << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) & CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK; line over 80 characters https://review.coreboot.org/#/c/27813/2/src/soc/amd/stoneyridge/southbridge… PS2, Line 584: cfg4 |= (0xD000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK; line over 80 characters https://review.coreboot.org/#/c/27813/2/src/soc/amd/stoneyridge/southbridge… PS2, Line 586: cfg4 |= (0x02D5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK; line over 80 characters -- To view, visit https://review.coreboot.org/27813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 Gerrit-Change-Number: 27813 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 02 Aug 2018 21:57:11 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Enable spread spectrum in bootblock
by Raul Rangel (Code Review) 02 Aug '18

02 Aug '18

Hello Garrett Kirkendall, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27813 to look at the new patch set (#2). Change subject: soc/amd/stoneyridge: Enable spread spectrum in bootblock ...................................................................... soc/amd/stoneyridge: Enable spread spectrum in bootblock setup_spread_spectrum is called in early_init, meaning the console is not initialized yet. So you won't see boot block booting twice. BUG=b:111610455 TEST=booted grunt and verified that AmdInitReset does not reboot. I had AGESA patched to skip the JTAG check. Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 89 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/27813/2 -- To view, visit https://review.coreboot.org/27813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 Gerrit-Change-Number: 27813 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: exception: Fix segment error code mask
by Martin Roth (Code Review) 02 Aug '18

02 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27812 ) Change subject: exception: Fix segment error code mask ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3439f9ce1e8cf0c472c4eb82d74a787718c9609f Gerrit-Change-Number: 27812 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 02 Aug 2018 21:43:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: stoneyridge: Enable spread spectrum in bootblock
by Martin Roth (Code Review) 02 Aug '18

02 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27813 ) Change subject: stoneyridge: Enable spread spectrum in bootblock ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/27813/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27813/1//COMMIT_MSG@7 PS1, Line 7: stoneyridge soc/amd/stoneyridge https://review.coreboot.org/#/c/27813/1/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/27813/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 610: setup_spread_spectrum Can this go earlier in this list? -- To view, visit https://review.coreboot.org/27813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 Gerrit-Change-Number: 27813 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 02 Aug 2018 21:40:56 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: stoneyridge: Enable spread spectrum in bootblock
by build bot (Jenkins) (Code Review) 02 Aug '18

02 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27813 ) Change subject: stoneyridge: Enable spread spectrum in bootblock ...................................................................... Patch Set 1: (6 comments) https://review.coreboot.org/#/c/27813/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/27813/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 380: #define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xFFFF << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) line over 80 characters https://review.coreboot.org/#/c/27813/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 382: #define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xFFFF << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) line over 80 characters https://review.coreboot.org/#/c/27813/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 385: #define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xF << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) line over 80 characters https://review.coreboot.org/#/c/27813/1/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/27813/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 579: cfg5 |= (0x2 << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) & CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK; line over 80 characters https://review.coreboot.org/#/c/27813/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 584: cfg4 |= (0xD000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK; line over 80 characters https://review.coreboot.org/#/c/27813/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 586: cfg4 |= (0x02D5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK; line over 80 characters -- To view, visit https://review.coreboot.org/27813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 Gerrit-Change-Number: 27813 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 02 Aug 2018 21:30:11 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: stoneyridge: Enable spread spectrum in bootblock
by Raul Rangel (Code Review) 02 Aug '18

02 Aug '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27813 Change subject: stoneyridge: Enable spread spectrum in bootblock ...................................................................... stoneyridge: Enable spread spectrum in bootblock setup_spread_spectrum is called in early_init, meaning the console is not initialized yet. So you won't see boot block booting twice. BUG=b:111610455 TEST=booted grunt and verified that AmdInitReset does not reboot. I had AGESA patched to skip the JTAG check. Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 89 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/27813/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 15c9581..64b4b46 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -367,6 +367,28 @@ #define GPP_CLK0_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT) #define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 1 +/* Bit definitions for MISC_MMIO_BASE register MiscClkCntl1 */ +#define MISC_CGPLL_CONFIG1 0x08 +#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) +#define MISC_CGPLL_CONFIG3 0x10 +#define CG1PLL_REFDIV_SHIFT 0 +#define CG1PLL_REFDIV_MASK (0x3FF << CG1PLL_REFDIV_SHIFT) +#define CG1PLL_FBDIV_SHIFT 10 +#define CG1PLL_FBDIV_MASK (0xFFF << CG1PLL_FBDIV_SHIFT) +#define MISC_CGPLL_CONFIG4 0x14 +#define CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT 0 +#define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xFFFF << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) +#define CG1PLL_SS_AMOUNT_DSFRAC_SHIFT 16 +#define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xFFFF << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) +#define MISC_CGPLL_CONFIG5 0x18 +#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT 8 +#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xF << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) +#define MISC_CGPLL_CONFIG6 0x1C +#define CG1PLL_LF_MODE_SHIFT 9 +#define CG1PLL_LF_MODE_MASK (0x1FF << CG1PLL_LF_MODE_SHIFT) +#define MISC_CLK_CNTL1 0x40 +#define CG1PLL_FBDIV_TEST BIT(26) + struct stoneyridge_aoac { int enable; int status; @@ -404,6 +426,8 @@ void pm_write8(u8 reg, u8 value); void pm_write16(u8 reg, u16 value); void pm_write32(u8 reg, u32 value); +u32 misc_read32(u8 reg); +void misc_write32(u8 reg, u32 value); uint8_t smi_read8(uint8_t offset); uint16_t smi_read16(uint8_t offset); uint32_t smi_read32(uint8_t offset); diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index 26c86e8..9daf0bb 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -36,6 +36,16 @@ return read16((void *)(PM_MMIO_BASE + reg)); } +void misc_write32(u8 reg, u32 value) +{ + write32((void *)(MISC_MMIO_BASE + reg), value); +} + +u32 misc_read32(u8 reg) +{ + return read32((void *)(MISC_MMIO_BASE + reg)); +} + void pm_write32(u8 reg, u32 value) { write32((void *)(PM_MMIO_BASE + reg), value); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 63d8806..0040de3 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -33,6 +33,7 @@ #include <soc/pci_devs.h> #include <agesa_headers.h> #include <soc/nvs.h> +#include <reset.h> /* * Table of devices that need their AOAC registers enabled and waited @@ -541,6 +542,59 @@ } } +static void setup_spread_spectrum(void) +{ + uint16_t rstcfg = pm_read16(PWR_RESET_CFG); + + rstcfg &= ~TOGGLE_ALL_PWR_GOOD; + pm_write16(PWR_RESET_CFG, rstcfg); + + uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1); + + if (cntl1 & CG1PLL_FBDIV_TEST) { + printk(BIOS_DEBUG, "Spread spectrum is ready\n"); + misc_write32(MISC_CGPLL_CONFIG1, + misc_read32(MISC_CGPLL_CONFIG1) | + CG1PLL_SPREAD_SPECTRUM_ENABLE); + + return; + } + + printk(BIOS_DEBUG, "Setting up spread spectrum\n"); + + uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6); + cfg6 &= ~CG1PLL_LF_MODE_MASK; + cfg6 |= (0x0F8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK; + misc_write32(MISC_CGPLL_CONFIG6, cfg6); + + uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3); + cfg3 &= ~CG1PLL_REFDIV_MASK; + cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK; + cfg3 &= ~CG1PLL_FBDIV_MASK; + cfg3 |= (0x04B << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK; + misc_write32(MISC_CGPLL_CONFIG3, cfg3); + + uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5); + cfg5 &= ~CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK; + cfg5 |= (0x2 << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) & CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK; + misc_write32(MISC_CGPLL_CONFIG5, cfg5); + + uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4); + cfg4 &= ~CG1PLL_SS_AMOUNT_DSFRAC_MASK; + cfg4 |= (0xD000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK; + cfg4 &= ~CG1PLL_SS_STEP_SIZE_DSFRAC_MASK; + cfg4 |= (0x02D5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK; + misc_write32(MISC_CGPLL_CONFIG4, cfg4); + + rstcfg |= TOGGLE_ALL_PWR_GOOD; + pm_write16(PWR_RESET_CFG, rstcfg); + + cntl1 |= CG1PLL_FBDIV_TEST; + misc_write32(MISC_CLK_CNTL1, cntl1); + + soft_reset(); +} + void bootblock_fch_early_init(void) { sb_enable_rom(); @@ -553,6 +607,7 @@ sb_enable_cf9_io(); sb_enable_legacy_io(); enable_aoac_devices(); + setup_spread_spectrum(); } void sb_enable(device_t dev) -- To view, visit https://review.coreboot.org/27813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 Gerrit-Change-Number: 27813 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: mp_init: fix typo
by Martin Roth (Code Review) 02 Aug '18

02 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27811 ) Change subject: mp_init: fix typo ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic2d7bf5f5335894ede98dc7e6cc6a65e4897e487 Gerrit-Change-Number: 27811 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 02 Aug 2018 21:21:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit August 2018