coreboot-gerrit August 2018

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Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
by Richard Spiegel (Code Review) 25 Aug '18

25 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28344 Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() ...................................................................... soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL, which was deprecated in favor of a public PCI register (though only the bits to enable debug port became public) 0x90. Therefor code needs to be updated. BUG=b:69231009 TEST=Build and boot grunt. Change-Id: Ibb25992729d984b8570712f91a03a7cd1e9b8643 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/enable_usbdebug.c M src/soc/amd/stoneyridge/include/soc/southbridge.h 2 files changed, 20 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/28344/1 diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index efe34e5..a2b5dd5 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -22,8 +22,6 @@ #include <device/pci_def.h> #include <soc/southbridge.h> -#define DEBUGPORT_MISC_CONTROL 0x80 - pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { /* Enable all of the USB controllers */ @@ -38,15 +36,22 @@ return PCI_DEV(0, 0x12, 0); } +/* + * Stoneyridge selects port 1 as the debug port by default, and coreboot + * function usbdebug_init_() also selects port 1 if USBDEBUG_DEFAULT_PORT + * is not selected or set to 0. So if port 1 is used, no change is needed. + * For ports 2 and 3, value of USBDEBUG_DEFAULT_PORT is the port itself, + * but to work around usbdebug_init_(), if port 0 is desired set + * USBDEBUG_DEFAULT_PORT to 4. + */ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { - u8 *base_regs = pci_ehci_base_regs(dev); - u32 reg32; + u32 reg32, value; - /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ - reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL); - reg32 &= ~(0xf << 28); - reg32 |= (port << 28); - reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ - write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); + value = (port & 0x00000003) << DEBUG_PORT_SELECT_SHIFT; + value |= DEBUG_PORT_ENABLE; + reg32 = pci_read_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4); + reg32 &= ~DEBUG_PORT_MASK; + reg32 |= value; + pci_write_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4, reg32); } diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 530b93a..f054b3b 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -305,6 +305,11 @@ #define OC_PORT2_SHIFT 8 #define OC_PORT3_SHIFT 12 +#define EHCI_HUB_CONFIG4 0x90 +#define DEBUG_PORT_SELECT_SHIFT 16 +#define DEBUG_PORT_ENABLE BIT(18) +#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18)) + #define WIDEIO_RANGE_ERROR -1 #define TOTAL_WIDEIO_PORTS 3 -- To view, visit https://review.coreboot.org/28344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibb25992729d984b8570712f91a03a7cd1e9b8643 Gerrit-Change-Number: 28344 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
by Richard Spiegel (Code Review) 25 Aug '18

25 Aug '18

Richard Spiegel has abandoned this change. ( https://review.coreboot.org/28343 ) Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() ...................................................................... Abandoned Missing a file, wrong change id -- To view, visit https://review.coreboot.org/28343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I0aa49d567d24c10a2273c5e748cd0c89e83dfd70 Gerrit-Change-Number: 28343 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
by Richard Spiegel (Code Review) 25 Aug '18

25 Aug '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28343 ) Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() ...................................................................... Patch Set 1: (1 comment) Missing a file! https://review.coreboot.org/#/c/28343/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/28343/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 311: #define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18)) > Macros with complex values should be enclosed in parentheses I don't understand... it is enclosed by parenthesis. -- To view, visit https://review.coreboot.org/28343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0aa49d567d24c10a2273c5e748cd0c89e83dfd70 Gerrit-Change-Number: 28343 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Aug 2018 23:41:44 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
by Richard Spiegel (Code Review) 25 Aug '18

25 Aug '18

Richard Spiegel has abandoned this change. ( https://review.coreboot.org/28342 ) Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() ...................................................................... Abandoned duplicated -- To view, visit https://review.coreboot.org/28342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I5938ada96999774bd998998d47686427ec34d4d1 Gerrit-Change-Number: 28342 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
by Richard Spiegel (Code Review) 25 Aug '18

25 Aug '18

Richard Spiegel has abandoned this change. ( https://review.coreboot.org/28341 ) Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() ...................................................................... Abandoned duplicated -- To view, visit https://review.coreboot.org/28341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I47b0e4450f96399fc3066d0a974e7a9324d82f90 Gerrit-Change-Number: 28341 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
by Richard Spiegel (Code Review) 25 Aug '18

25 Aug '18

Richard Spiegel has abandoned this change. ( https://review.coreboot.org/28340 ) Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() ...................................................................... Abandoned duplicated -- To view, visit https://review.coreboot.org/28340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ic10c43cb6e5a9e8fe3bccf79a8ed69a6a0b49fce Gerrit-Change-Number: 28340 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
by build bot (Jenkins) (Code Review) 25 Aug '18

25 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28340 ) Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28340/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/28340/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 311: #define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18)) Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/28340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic10c43cb6e5a9e8fe3bccf79a8ed69a6a0b49fce Gerrit-Change-Number: 28340 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Aug 2018 23:37:58 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
by build bot (Jenkins) (Code Review) 25 Aug '18

25 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28343 ) Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28343/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/28343/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 311: #define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18)) Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/28343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0aa49d567d24c10a2273c5e748cd0c89e83dfd70 Gerrit-Change-Number: 28343 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Aug 2018 23:37:53 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
by build bot (Jenkins) (Code Review) 25 Aug '18

25 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28342 ) Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28342/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/28342/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 311: #define DEBUG_PORT_MASK ((BIT(16) | BIT(17) | (BIT(18))) Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/28342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5938ada96999774bd998998d47686427ec34d4d1 Gerrit-Change-Number: 28342 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Aug 2018 23:37:41 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
by build bot (Jenkins) (Code Review) 25 Aug '18

25 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28341 ) Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/28341/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/28341/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 311: #define DEBUG_PORT_MASK ( BIT(16) | BIT(17) | (BIT(18) ) space prohibited after that open parenthesis '(' https://review.coreboot.org/#/c/28341/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 311: #define DEBUG_PORT_MASK ( BIT(16) | BIT(17) | (BIT(18) ) space prohibited before that close parenthesis ')' https://review.coreboot.org/#/c/28341/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 311: #define DEBUG_PORT_MASK ( BIT(16) | BIT(17) | (BIT(18) ) Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/28341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I47b0e4450f96399fc3066d0a974e7a9324d82f90 Gerrit-Change-Number: 28341 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Aug 2018 23:37:28 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit August 2018