coreboot-gerrit August 2018

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Change in coreboot[master]: riscv: update delegate
by Xiang Wang (Code Review) 27 Aug '18

27 Aug '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/28356 Change subject: riscv: update delegate ...................................................................... riscv: update delegate PMP may trigger an access fault. PMP operations must be in m-mode. So access fault can't be delegate to s-mode. Change-Id: If08220fdbb483ebf323f481ab0c7b012ac7a196c Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/virtual_memory.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/28356/1 diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 3bee868..71e2ac9 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -26,11 +26,8 @@ * the spec so for now we enumerate and set them all. */ static int delegate = 0 | (1 << CAUSE_MISALIGNED_FETCH) - | (1 << CAUSE_FETCH_ACCESS) | (1 << CAUSE_ILLEGAL_INSTRUCTION) | (1 << CAUSE_BREAKPOINT) - | (1 << CAUSE_LOAD_ACCESS) - | (1 << CAUSE_STORE_ACCESS) | (1 << CAUSE_USER_ECALL) | (1 << CAUSE_FETCH_PAGE_FAULT) | (1 << CAUSE_LOAD_PAGE_FAULT) -- To view, visit https://review.coreboot.org/28356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If08220fdbb483ebf323f481ab0c7b012ac7a196c Gerrit-Change-Number: 28356 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: HiFive-Unleashed: add support clint
by Xiang Wang (Code Review) 27 Aug '18

27 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28355 to look at the new patch set (#2). Change subject: HiFive-Unleashed: add support clint ...................................................................... HiFive-Unleashed: add support clint Change-Id: Ibc3a8644dcb83d5697d9d6e551c7682377285116 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- A src/soc/sifive/fu540/clint.c A src/soc/sifive/fu540/include/soc/clint.h 2 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/28355/2 -- To view, visit https://review.coreboot.org/28355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibc3a8644dcb83d5697d9d6e551c7682377285116 Gerrit-Change-Number: 28355 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: HiFive-Unleashed: add support clint
by Xiang Wang (Code Review) 27 Aug '18

27 Aug '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/28355 Change subject: HiFive-Unleashed: add support clint ...................................................................... HiFive-Unleashed: add support clint Change-Id: Ibc3a8644dcb83d5697d9d6e551c7682377285116 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- A src/soc/sifive/fu540/clint.c A src/soc/sifive/fu540/include/soc/clint.h 2 files changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/28355/1 diff --git a/src/soc/sifive/fu540/clint.c b/src/soc/sifive/fu540/clint.c new file mode 100644 index 0000000..463c22b --- /dev/null +++ b/src/soc/sifive/fu540/clint.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mcall.h> +#include <arch/io.h> +#include <soc/clint.h> + +void mtime_init(void) +{ + long hart_id = read_csr(mhartid); + HLS()->time = (uint64_t *)0x20bff8; + HLS()->timecmp = (uint64_t *)(0x204000 + 8 * hart_id); +} + +void set_msip(int hartid, int val) +{ + long hart_id = read_csr(mhartid); + write32((void *)(0x200000 + 4 * hart_id), !!val); +} + diff --git a/src/soc/sifive/fu540/include/soc/clint.h b/src/soc/sifive/fu540/include/soc/clint.h new file mode 100644 index 0000000..f120514 --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/clint.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_SIFIVE_HIFIVE_U_CLOCK_H__ +#define __SOC_SIFIVE_HIFIVE_U_CLOCK_H__ + +/* This function is used to initialize the hart-local storage field + * associated with mtime */ +void mtime_init(void); + +/* This function is used to operate msip. Used to send interrupt + * signals between with cores. */ +void set_msip(int hartid, int val); + +#endif + -- To view, visit https://review.coreboot.org/28355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibc3a8644dcb83d5697d9d6e551c7682377285116 Gerrit-Change-Number: 28355 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: vendorcode/facebook: Add vendorcode
by Werner Zeh (Code Review) 27 Aug '18

27 Aug '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/28351 ) Change subject: vendorcode/facebook: Add vendorcode ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28351/1/src/vendorcode/facebook/Kconfig File src/vendorcode/facebook/Kconfig: https://review.coreboot.org/#/c/28351/1/src/vendorcode/facebook/Kconfig@24 PS1, Line 24: Celluar Cellular seems to be the right spelling, or? -- To view, visit https://review.coreboot.org/28351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I761ac3d1dcbab9dceb7a4c4f835ca8363680eb03 Gerrit-Change-Number: 28351 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 27 Aug 2018 05:29:13 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Documentation: fix sphinx warnings
by Tom Hiller (Code Review) 27 Aug '18

27 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28354 to look at the new patch set (#2). Change subject: Documentation: fix sphinx warnings ...................................................................... Documentation: fix sphinx warnings Fix warning from list in table cells for nri_registers.md Change-Id: I2b77ad266d1c5f693536e161f96f3db19832989c Signed-off-by: Tom Hiller <thrilleratplay(a)gmail.com> --- M Documentation/northbridge/intel/sandybridge/nri_registers.md 1 file changed, 43 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/28354/2 -- To view, visit https://review.coreboot.org/28354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2b77ad266d1c5f693536e161f96f3db19832989c Gerrit-Change-Number: 28354 Gerrit-PatchSet: 2 Gerrit-Owner: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHz
by Kevin Chiu (Code Review) 27 Aug '18

27 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28353 to look at the new patch set (#3). Change subject: google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHz ...................................................................... google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHz Bayhub eMMC controller default runs SD base 50MHz at the first power on. After boot into OS, mmc kernel driver will config controller to HS200/208MHz and send MMC CMD21 (tuning block). But Bayhub PCR register 0x3E4[22] (eMMC MODE select) is not clear after system warn reset. So eMMC will still run 208Mhz but there is no block tuning cmd in depthcharge. It will cause two Sandisk eMMC (SDINBDA4-64G-V/SDINBDA4-32G-V) failing to load kernel and trap in 0x5B error (No bootable kernel found on disk). BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: Ic080682e67323577c7f0ba4ed08f8adafca620cc Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/drivers/generic/bayhub/bh720.c M src/drivers/generic/bayhub/bh720.h M src/mainboard/google/kahlee/variants/baseboard/mainboard.c 3 files changed, 49 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/28353/3 -- To view, visit https://review.coreboot.org/28353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic080682e67323577c7f0ba4ed08f8adafca620cc Gerrit-Change-Number: 28353 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHz
by build bot (Jenkins) (Code Review) 27 Aug '18

27 Aug '18

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Change in coreboot[master]: google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHz
by Kevin Chiu (Code Review) 27 Aug '18

27 Aug '18

Kevin Chiu has uploaded a new patch set (#2). ( https://review.coreboot.org/28353 ) Change subject: google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHz ...................................................................... google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHz Bayhub eMMC controller default runs SD base 50MHz at the first power on. After boot into OS, mmc kernel driver will config controller to HS200/208MHz and send MMC CMD21 (tuning block). But Bayhub PCR register 0x3E4[22] (eMMC MODE select) is not clear after system warn reset. So eMMC will still run 208Mhz but there is no block tuning cmd in depthcharge. It will cause two Sandisk eMMC (SDINBDA4-64G-V/SDINBDA4-32G-V) failing to load kernel and trap in 0x5B error (No bootable kernel found on disk). BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: Ic080682e67323577c7f0ba4ed08f8adafca620cc Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/drivers/generic/bayhub/bh720.c M src/drivers/generic/bayhub/bh720.h M src/mainboard/google/kahlee/variants/baseboard/mainboard.c 3 files changed, 49 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/28353/2 -- To view, visit https://review.coreboot.org/28353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic080682e67323577c7f0ba4ed08f8adafca620cc Gerrit-Change-Number: 28353 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Documentation: fix sphinx warnings
by Tom Hiller (Code Review) 27 Aug '18

27 Aug '18

Tom Hiller has uploaded this change for review. ( https://review.coreboot.org/28354 Change subject: Documentation: fix sphinx warnings ...................................................................... Documentation: fix sphinx warnings Fix warning from list in table cells for nri_registers.md Change-Id: I2b77ad266d1c5f693536e161f96f3db19832989c Signed-off-by: Tom Hiller <thrilleratplay(a)gmail.com> --- M Documentation/northbridge/intel/sandybridge/nri_registers.md 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/28354/1 diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md index d5857ec..e47522e 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_registers.md +++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md @@ -1522,13 +1522,20 @@ | 24:27| tWR | +-----------+------------------------------------------------------------------+ | 29 | Command 3-state options | +| | | | | - 0: Drive when channel is active, tri-state when inactive, | +| | | | | - 1: Always drive command bus | +| | | +-----------+------------------------------------------------------------------+ | 30:31| CMD stretch, | +| | | | | - 00b: 1N, | +| | | | | - 10b: 2N, | +| | | | | - 11b: 3N | +| | | +-----------+------------------------------------------------------------------+ ``` @@ -1896,14 +1903,23 @@ | | plus burst length. | +-----------+------------------------------------------------------------------+ | 8:10| PDWN_mode, selects the mode of power-down: | +| | | | | - 0x0: No power down, | +| | | | | - 0x1: APD, | +| | | | | - 0x2: PPD, | +| | | | | - 0x3: APD+PPD, | +| | | | | - 0x4: Reserved, | +| | | | | - 0x5: Reserved, | +| | | | | - 0x6: PPD-DLLoff, | +| | | | | - 0x7: APD+PPD+DLLof | +| | | +-----------+------------------------------------------------------------------+ ``` @@ -1973,19 +1989,31 @@ | Bit | Description | +===========+==================================================================+ | 0:1| CH_A, defines the largest channel. | +| | | | | - 00b: Channel 0, | +| | | | | - 01b: Channel 1, | +| | | | | - 10b: Channel 2 | +| | | +-----------+------------------------------------------------------------------+ | 2:3| CH_B, defines the mid-size channel. | +| | | | | - 00b: Channel 0, | +| | | | | - 01b: Channel 1, | +| | | | | - 10b: Channel 2 | +| | | +-----------+------------------------------------------------------------------+ | 2:3| CH_C, defines the smallest channel. | +| | | | | - 00b: Channel 0, | +| | | | | - 01b: Channel 1, | +| | | | | - 10b: Channel 2, CH_C is 10 if only 2 channels are supported | +| | | +-----------+------------------------------------------------------------------+ ``` @@ -2002,8 +2030,11 @@ | 0:7| DIMMA size in 256 MB multiples | +-----------+------------------------------------------------------------------+ | 16 | DIMM A select (DAS) Slot to DIMM mapping, | +| | | | | - 0: DIMMA, DIMMB, | +| | | | | - 1: DIMMB, DIMMA | +| | | +-----------+------------------------------------------------------------------+ | 17 | DIMM A number of ranks | +-----------+------------------------------------------------------------------+ @@ -2025,9 +2056,13 @@ | | 20-27 to use for high rank interleave | +-----------+------------------------------------------------------------------+ | 24:25| ECC, | +| | | | | - 00b: No ECC active, | +| | | | | - 01b: ECC is active on IO, | +| | | | | - 11b: ECC is active on both IO and ECC logic | +| | | +-----------+------------------------------------------------------------------+ ``` @@ -2121,7 +2156,9 @@ | Bit | Description | +===========+==================================================================+ | 0:31| Inject error when ECC_inj_Addr_Compare[31:0] = | +| | | | | ADDR[37:6] && ECC_Inj_Addr_Mask[31:0] | +| | | +-----------+------------------------------------------------------------------+ ``` @@ -2138,7 +2175,9 @@ | 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] | +-----------+------------------------------------------------------------------+ | 8 | - 1: 100Mhz reference clock | +| | | | | - 0: 133Mhz reference clock (Ivy Bridge only) | +| | | +-----------+------------------------------------------------------------------+ | 31 | PLL busy | +-----------+------------------------------------------------------------------+ @@ -2155,8 +2194,11 @@ | Bit | Description | +===========+==================================================================+ | 0:7| Active multiplier: | +| | | | | - 100Mhz [7,12], | +| | | | | - 133Mhz [3,19] | +| | | +-----------+------------------------------------------------------------------+ ``` -- To view, visit https://review.coreboot.org/28354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2b77ad266d1c5f693536e161f96f3db19832989c Gerrit-Change-Number: 28354 Gerrit-PatchSet: 1 Gerrit-Owner: Tom Hiller <thrilleratplay(a)gmail.com>

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Change in coreboot[master]: google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHz
by build bot (Jenkins) (Code Review) 27 Aug '18

27 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28353 ) Change subject: google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHz ...................................................................... Patch Set 1: (6 comments) https://review.coreboot.org/#/c/28353/1/src/mainboard/google/kahlee/variant… File src/mainboard/google/kahlee/variants/baseboard/mainboard.c: https://review.coreboot.org/#/c/28353/1/src/mainboard/google/kahlee/variant… PS1, Line 54: write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); line over 80 characters https://review.coreboot.org/#/c/28353/1/src/mainboard/google/kahlee/variant… PS1, Line 56: write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); line over 80 characters https://review.coreboot.org/#/c/28353/1/src/mainboard/google/kahlee/variant… PS1, Line 57: write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); line over 80 characters https://review.coreboot.org/#/c/28353/1/src/mainboard/google/kahlee/variant… PS1, Line 60: write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_READ | BH720_PCR_CSR); line over 80 characters https://review.coreboot.org/#/c/28353/1/src/mainboard/google/kahlee/variant… PS1, Line 62: write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data & ~BH720_PCR_CSR_EMMC_MODE_SEL); line over 80 characters https://review.coreboot.org/#/c/28353/1/src/mainboard/google/kahlee/variant… PS1, Line 63: write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_WRITE | BH720_PCR_CSR); line over 80 characters -- To view, visit https://review.coreboot.org/28353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic080682e67323577c7f0ba4ed08f8adafca620cc Gerrit-Change-Number: 28353 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 27 Aug 2018 04:03:01 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit August 2018