coreboot-gerrit August 2018

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Change in coreboot[master]: src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110...
by Mike Banon (Code Review) 27 Aug '18

27 Aug '18

Mike Banon has uploaded a new patch set (#2). ( https://review.coreboot.org/28370 ) Change subject: src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 ...................................................................... src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 This microcode update for CPU ID 0x700F01 improves system stability: in particular, fixes Xen hardware virtualization freezes. Also it attempts to patch some Spectre-related security vulnerabilities. This new microcode has been tested by multiple coreboot community members and found working perfectly. Old version: 0x700010B [2013-07-09] replaced by New version: 0x7000110 [2018-02-09] Change-Id: Iebe6e54d922378a8a1feb97f37b08ac50c8234b2 Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> --- M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c 1 file changed, 437 insertions(+), 3,462 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/28370/2 -- To view, visit https://review.coreboot.org/28370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iebe6e54d922378a8a1feb97f37b08ac50c8234b2 Gerrit-Change-Number: 28370 Gerrit-PatchSet: 2 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>

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Change in coreboot[master]: src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x0700011...
by Mike Banon (Code Review) 27 Aug '18

27 Aug '18

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/28370 Change subject: src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x07000110 2018-02-09 ...................................................................... src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x07000110 2018-02-09 This microcode update for CPU ID 0x700F01 improves system stability: in particular, fixes Xen hardware virtualization freezes. Also it attempts to patch some Spectre-related security vulnerabilities. This new microcode has been tested by multiple coreboot community members and found working perfectly. Old version: 0x700010B [2013-07-09] replaced by New version: 0x7000110 [2018-02-09] Change-Id: Iebe6e54d922378a8a1feb97f37b08ac50c8234b2 Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> --- M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c 1 file changed, 437 insertions(+), 3,462 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/28370/1 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c index 61876b8..a0a20eb 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c @@ -4,16 +4,16 @@ * * AMD F16Kb Microcode patch. * - * F16Kb Microcode Patch rev 0700010B for 7001 or equivalent. + * F16Kb Microcode Patch rev 07000110 for 7001 or equivalent. * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU/Family/0x16/KB - * @e \$Revision: 267923 $ @e \$Date: 2013-07-15 16:49:48 -0400 (Mon, 15 Jul 2013) $ + * @e \$Revision: 334098 $ @e \$Date: 2018-02-09 14:21:15 -0400 (Fri, 09 Feb 2018) $ */ /***************************************************************************** * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2018, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -64,3468 +64,443 @@ */ -// Encrypt Patch code 0700010B for 7001 and equivalent +// Encrypt Patch code 07000110 for 7001 and equivalent CONST UINT8 ROMDATA CpuF16KbId7001MicrocodePatch [IDS_PAD_4K] = { - 0x13, - 0x20, - 0x09, - 0x07, - 0x0b, - 0x01, - 0x00, - 0x07, - 0x03, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x01, - 0x70, - 0x00, - 0x00, - 0x00, - 0xaa, - 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0x00, 0x00, 0x00, 0x00, + 0x00, 0x00 }; /*---------------------------------------------------------------------------------------- -- To view, visit https://review.coreboot.org/28370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iebe6e54d922378a8a1feb97f37b08ac50c8234b2 Gerrit-Change-Number: 28370 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>

1 0

Change in coreboot[master]: vendorcode/amd/pi/00670F00: Transfer TP_Perf_STRUCT to AGESA.h
by Richard Spiegel (Code Review) 27 Aug '18

27 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28369 Change subject: vendorcode/amd/pi/00670F00: Transfer TP_Perf_STRUCT to AGESA.h ...................................................................... vendorcode/amd/pi/00670F00: Transfer TP_Perf_STRUCT to AGESA.h Google is creating code to measure AGESA performance, which needs structure TP_Perf_STRUCT and associated definitions. In preparation to remove IDS headers, move the necessary definitions to AGESA.h. BUG=b:112885948 TEST=Build grunt Change-Id: I941a67a8889a9dbf35c9fd511c7f670623204134 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/vendorcode/amd/pi/00670F00/AGESA.h M src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h M src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h 3 files changed, 119 insertions(+), 119 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/28369/1 diff --git a/src/vendorcode/amd/pi/00670F00/AGESA.h b/src/vendorcode/amd/pi/00670F00/AGESA.h index 2eee41b..fbe93bd 100644 --- a/src/vendorcode/amd/pi/00670F00/AGESA.h +++ b/src/vendorcode/amd/pi/00670F00/AGESA.h @@ -3581,6 +3581,125 @@ #ifndef IDS_CALLOUT_INIT #define IDS_CALLOUT_INIT 0x01 ///< The function data of IDS callout function of initialization. + +#define IDS_PERF_VERSION 0x00010001ul //version number 0.1.0.1 +/// Time points performance function used +/// N O T E: NEVER change below defination, any new TP MUST be appended to the end of this enum + typedef enum { + TP_BEGINPROCAMDINITEARLY = 0x100, ///< BeginProcAmdInitEarly + TP_ENDPROCAMDINITEARLY = 0x101, ///< EndProcAmdInitEarly + TP_BEGINAMDTOPOINITIALIZE = 0x102, ///< BeginAmdTopoInitialize + TP_ENDAMDTOPOINITIALIZE = 0x103, ///< EndAmdTopoInitialize + TP_BEGINGNBINITATEARLIER = 0x104, ///< BeginGnbInitAtEarlier + TP_ENDGNBINITATEARLIER = 0x105, ///< EndGnbInitAtEarlier + TP_BEGINAMDCPUEARLY = 0x106, ///< BeginAmdCpuEarly + TP_ENDAMDCPUEARLY = 0x107, ///< EndAmdCpuEarly + TP_BEGINGNBINITATEARLY = 0x108, ///< BeginGnbInitAtEarly + TP_ENDGNBINITATEARLY = 0x109, ///< EndGnbInitAtEarly + TP_BEGINPROCAMDINITENV = 0x10A, ///< BeginProcAmdInitEnv + TP_ENDPROCAMDINITENV = 0x10B, ///< EndProcAmdInitEnv + TP_BEGININITENV = 0x10C, ///< BeginInitEnv + TP_ENDINITENV = 0x10D, ///< EndInitEnv + TP_BEGINGNBINITATENV = 0x10E, ///< BeginGnbInitAtEnv + TP_ENDGNBINITATENV = 0x10F, ///< EndGnbInitAtEnv + TP_BEGINPROCAMDINITLATE = 0x110, ///< BeginProcAmdInitLate + TP_ENDPROCAMDINITLATE = 0x111, ///< EndProcAmdInitLate + TP_BEGINCREATSYSTEMTABLE = 0x112, ///< BeginCreatSystemTable + TP_ENDCREATSYSTEMTABLE = 0x113, ///< EndCreatSystemTable + TP_BEGINDISPATCHCPUFEATURESLATE = 0x114, ///< BeginDispatchCpuFeaturesLate + TP_ENDDISPATCHCPUFEATURESLATE = 0x115, ///< EndDispatchCpuFeaturesLate + TP_BEGINAMDCPULATE = 0x116, ///< BeginAmdCpuLate + TP_ENDAMDCPULATE = 0x117, ///< EndAmdCpuLate + TP_BEGINGNBINITATLATE = 0x118, ///< BeginGnbInitAtLate + TP_ENDGNBINITATLATE = 0x119, ///< EndGnbInitAtLate + TP_BEGINPROCAMDINITMID = 0x11A, ///< BeginProcAmdInitMid + TP_ENDPROCAMDINITMID = 0x11B, ///< EndProcAmdInitMid + TP_BEGININITMID = 0x11E, ///< BeginInitMid + TP_ENDINITMID = 0x11F, ///< EndInitMid + TP_BEGINGNBINITATMID = 0x120, ///< BeginGnbInitAtMid + TP_ENDGNBINITATMID = 0x121, ///< EndGnbInitAtMid + TP_BEGINPROCAMDINITPOST = 0x122, ///< BeginProcAmdInitPost + TP_ENDPROCAMDINITPOST = 0x123, ///< EndProcAmdInitPost + TP_BEGINGNBINITATPOST = 0x124, ///< BeginGnbInitAtPost + TP_ENDGNBINITATPOST = 0x125, ///< EndGnbInitAtPost + TP_BEGINAMDMEMAUTO = 0x126, ///< BeginAmdMemAuto + TP_ENDAMDMEMAUTO = 0x127, ///< EndAmdMemAuto + TP_BEGINAMDCPUPOST = 0x128, ///< BeginAmdCpuPost + TP_ENDAMDCPUPOST = 0x129, ///< EndAmdCpuPost + TP_BEGINGNBINITATPOSTAFTERDRAM = 0x12A, ///< BeginGnbInitAtPostAfterDram + TP_ENDGNBINITATPOSTAFTERDRAM = 0x12B, ///< EndGnbInitAtPostAfterDram + TP_BEGINPROCAMDINITRESET = 0x12C, ///< BeginProcAmdInitReset + TP_ENDPROCAMDINITRESET = 0x12D, ///< EndProcAmdInitReset + TP_BEGININITRESET = 0x12E, ///< BeginInitReset + TP_ENDINITRESET = 0x12F, ///< EndInitReset + TP_BEGINHTINITRESET = 0x130, ///< BeginHtInitReset + TP_ENDHTINITRESET = 0x131, ///< EndHtInitReset + TP_BEGINPROCAMDINITRESUME = 0x132, ///< BeginProcAmdInitResume + TP_ENDPROCAMDINITRESUME = 0x133, ///< EndProcAmdInitResume + TP_BEGINAMDMEMS3RESUME = 0x134, ///< BeginAmdMemS3Resume + TP_ENDAMDMEMS3RESUME = 0x135, ///< EndAmdMemS3Resume + TP_BEGINDISPATCHCPUFEATURESS3RESUME = 0x136, ///< BeginDispatchCpuFeaturesS3Resume + TP_ENDDISPATCHCPUFEATURESS3RESUME = 0x137, ///< EndDispatchCpuFeaturesS3Resume + TP_BEGINSETCORESTSCFREQSEL = 0x138, ///< BeginSetCoresTscFreqSel + TP_ENDSETCORESTSCFREQSEL = 0x139, ///< EndSetCoresTscFreqSel + TP_BEGINMEMFMCTMEMCLR_INIT = 0x13A, ///< BeginMemFMctMemClr_Init + TP_ENDNMEMFMCTMEMCLR_INIT = 0x13B, ///< EndnMemFMctMemClr_Init + TP_BEGINMEMBEFOREMEMDATAINIT = 0x13C, ///< BeginMemBeforeMemDataInit + TP_ENDMEMBEFOREMEMDATAINIT = 0x13D, ///< EndMemBeforeMemDataInit + TP_BEGINPROCAMDMEMAUTO = 0x13E, ///< BeginProcAmdMemAuto + TP_ENDPROCAMDMEMAUTO = 0x13F, ///< EndProcAmdMemAuto + TP_BEGINMEMMFLOWC32 = 0x140, ///< BeginMemMFlowC32 + TP_ENDMEMMFLOWC32 = 0x141, ///< EndMemMFlowC32 + TP_BEGINMEMINITIALIZEMCT = 0x142, ///< BeginMemInitializeMCT + TP_ENDMEMINITIALIZEMCT = 0x143, ///< EndMemInitializeMCT + TP_BEGINMEMSYSTEMMEMORYMAPPING = 0x144, ///< BeginMemSystemMemoryMapping + TP_ENDMEMSYSTEMMEMORYMAPPING = 0x145, ///< EndMemSystemMemoryMapping + TP_BEGINMEMDRAMTRAINING = 0x146, ///< BeginMemDramTraining + TP_ENDMEMDRAMTRAINING = 0x147, ///< EndMemDramTraining + TP_BEGINMEMOTHERTIMING = 0x148, ///< BeginMemOtherTiming + TP_ENDMEMOTHERTIMING = 0x149, ///< EndMemOtherTiming + TP_BEGINMEMUMAMEMTYPING = 0x14A, ///< BeginMemUMAMemTyping + TP_ENDMEMUMAMEMTYPING = 0x14B, ///< EndMemUMAMemTyping + TP_BEGINMEMMEMCLR = 0x14C, ///< BeginMemMemClr + TP_ENDMEMMEMCLR = 0x14D, ///< EndMemMemClr + TP_BEGINMEMMFLOWTN = 0x14E, ///< BeginMemMFlowTN + TP_ENDMEMMFLOWTN = 0x14F, ///< EndMemMFlowTN + TP_BEGINAGESAHOOKBEFOREDRAMINIT = 0x150, ///< BeginAgesaHookBeforeDramInit + TP_ENDAGESAHOOKBEFOREDRAMINIT = 0x151, ///< EndAgesaHookBeforeDramInit + TP_BEGINPROCMEMDRAMTRAINING = 0x152, ///< BeginProcMemDramTraining + TP_ENDPROCMEMDRAMTRAINING = 0x153, ///< EndProcMemDramTraining + TP_BEGINGNBINITATRTB = 0x154, ///< BeginGnbInitAtRtb + TP_ENDGNBINITATRTB = 0x155, ///< EndGnbInitAtRtb + TP_BEGINGNBLOADSCSDATA = 0x156, ///< BeginGnbLoadScsData + TP_ENDGNBLOADSCSDATA = 0x157, ///< EndGnbLoadScsData + TP_BEGINGNBPCIETRAINING = 0x158, ///< BeginGnbPcieTraining + TP_ENDGNBPCIETRAINING = 0x159, ///< EndGnbPcieTraining + TP_BEGINDISPATCHCPUFEATURESINITRTB = 0x15A, ///< BeginDispatchCpuFeaturesInitRtb + TP_ENDDISPATCHCPUFEATURESINITRTB = 0x15B, ///< EndDispatchCpuFeaturesInitRtb + TP_BEGINAMDCPUMID = 0x15C, ///< BeginAmdCpuEarly + TP_ENDAMDCPUMID = 0x15D, ///< EndAmdCpuEarly + TP_BEGINAMDGNBMIDLATE = 0x15E, ///< BeginAmdGnbMidLate + TP_ENDAMDAMDGNBMIDLATE = 0x15F, ///< EndAmdGnbMidLate + IDS_TP_END ///< End of IDS TP list + } IDS_PERF_DATA; + +/// Data Structure of Parameters for TestPoint_TSC. +typedef struct { + UINT32 LineInFile; ///< Line of current time counter + UINT64 Description; ///<Description ID + UINT64 StartTsc; ///< The StartTimer of TestPoint_TSC +} TestPoint_TSC; + +#define RESERVED_TP_NUMER 0x20 +#define MAX_PERFORMANCE_UNIT_NUM (IDS_TP_END - TP_BEGINPROCAMDINITEARLY + 1 + RESERVED_TP_NUMER) +/// Data Structure of Parameters for TP_Perf_STRUCT. +typedef struct { + UINT32 Signature; ///< "PERF" + UINT32 Version; ///< version + UINT32 Index; ///< The Index of TP_Perf_STRUCT + UINT32 TscInMhz; ///< Tsc counter in 1 mhz + TestPoint_TSC TP[MAX_PERFORMANCE_UNIT_NUM]; ///< The TP of TP_Perf_STRUCT +} TP_Perf_STRUCT; #endif /************************************************************************ diff --git a/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h b/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h index 40feef6..edb48ac 100644 --- a/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h +++ b/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h @@ -43,106 +43,5 @@ #include <check_for_wrapper.h> #ifndef _IDS_PERFORMANCE_DATA_POINT - #define _IDS_PERFORMANCE_DATA_POINT - #define IDS_PERF_VERSION 0x00010001ul //version number 0.1.0.1 -/// Time points performance function used -/// N O T E: NEVER change below defination, any new TP MUST be appended to the end of this enum - typedef enum { - TP_BEGINPROCAMDINITEARLY = 0x100, ///< BeginProcAmdInitEarly - TP_ENDPROCAMDINITEARLY = 0x101, ///< EndProcAmdInitEarly - TP_BEGINAMDTOPOINITIALIZE = 0x102, ///< BeginAmdTopoInitialize - TP_ENDAMDTOPOINITIALIZE = 0x103, ///< EndAmdTopoInitialize - TP_BEGINGNBINITATEARLIER = 0x104, ///< BeginGnbInitAtEarlier - TP_ENDGNBINITATEARLIER = 0x105, ///< EndGnbInitAtEarlier - TP_BEGINAMDCPUEARLY = 0x106, ///< BeginAmdCpuEarly - TP_ENDAMDCPUEARLY = 0x107, ///< EndAmdCpuEarly - TP_BEGINGNBINITATEARLY = 0x108, ///< BeginGnbInitAtEarly - TP_ENDGNBINITATEARLY = 0x109, ///< EndGnbInitAtEarly - TP_BEGINPROCAMDINITENV = 0x10A, ///< BeginProcAmdInitEnv - TP_ENDPROCAMDINITENV = 0x10B, ///< EndProcAmdInitEnv - TP_BEGININITENV = 0x10C, ///< BeginInitEnv - TP_ENDINITENV = 0x10D, ///< EndInitEnv - TP_BEGINGNBINITATENV = 0x10E, ///< BeginGnbInitAtEnv - TP_ENDGNBINITATENV = 0x10F, ///< EndGnbInitAtEnv - TP_BEGINPROCAMDINITLATE = 0x110, ///< BeginProcAmdInitLate - TP_ENDPROCAMDINITLATE = 0x111, ///< EndProcAmdInitLate - TP_BEGINCREATSYSTEMTABLE = 0x112, ///< BeginCreatSystemTable - TP_ENDCREATSYSTEMTABLE = 0x113, ///< EndCreatSystemTable - TP_BEGINDISPATCHCPUFEATURESLATE = 0x114, ///< BeginDispatchCpuFeaturesLate - TP_ENDDISPATCHCPUFEATURESLATE = 0x115, ///< EndDispatchCpuFeaturesLate - TP_BEGINAMDCPULATE = 0x116, ///< BeginAmdCpuLate - TP_ENDAMDCPULATE = 0x117, ///< EndAmdCpuLate - TP_BEGINGNBINITATLATE = 0x118, ///< BeginGnbInitAtLate - TP_ENDGNBINITATLATE = 0x119, ///< EndGnbInitAtLate - TP_BEGINPROCAMDINITMID = 0x11A, ///< BeginProcAmdInitMid - TP_ENDPROCAMDINITMID = 0x11B, ///< EndProcAmdInitMid - TP_BEGININITMID = 0x11E, ///< BeginInitMid - TP_ENDINITMID = 0x11F, ///< EndInitMid - TP_BEGINGNBINITATMID = 0x120, ///< BeginGnbInitAtMid - TP_ENDGNBINITATMID = 0x121, ///< EndGnbInitAtMid - TP_BEGINPROCAMDINITPOST = 0x122, ///< BeginProcAmdInitPost - TP_ENDPROCAMDINITPOST = 0x123, ///< EndProcAmdInitPost - TP_BEGINGNBINITATPOST = 0x124, ///< BeginGnbInitAtPost - TP_ENDGNBINITATPOST = 0x125, ///< EndGnbInitAtPost - TP_BEGINAMDMEMAUTO = 0x126, ///< BeginAmdMemAuto - TP_ENDAMDMEMAUTO = 0x127, ///< EndAmdMemAuto - TP_BEGINAMDCPUPOST = 0x128, ///< BeginAmdCpuPost - TP_ENDAMDCPUPOST = 0x129, ///< EndAmdCpuPost - TP_BEGINGNBINITATPOSTAFTERDRAM = 0x12A, ///< BeginGnbInitAtPostAfterDram - TP_ENDGNBINITATPOSTAFTERDRAM = 0x12B, ///< EndGnbInitAtPostAfterDram - TP_BEGINPROCAMDINITRESET = 0x12C, ///< BeginProcAmdInitReset - TP_ENDPROCAMDINITRESET = 0x12D, ///< EndProcAmdInitReset - TP_BEGININITRESET = 0x12E, ///< BeginInitReset - TP_ENDINITRESET = 0x12F, ///< EndInitReset - TP_BEGINHTINITRESET = 0x130, ///< BeginHtInitReset - TP_ENDHTINITRESET = 0x131, ///< EndHtInitReset - TP_BEGINPROCAMDINITRESUME = 0x132, ///< BeginProcAmdInitResume - TP_ENDPROCAMDINITRESUME = 0x133, ///< EndProcAmdInitResume - TP_BEGINAMDMEMS3RESUME = 0x134, ///< BeginAmdMemS3Resume - TP_ENDAMDMEMS3RESUME = 0x135, ///< EndAmdMemS3Resume - TP_BEGINDISPATCHCPUFEATURESS3RESUME = 0x136, ///< BeginDispatchCpuFeaturesS3Resume - TP_ENDDISPATCHCPUFEATURESS3RESUME = 0x137, ///< EndDispatchCpuFeaturesS3Resume - TP_BEGINSETCORESTSCFREQSEL = 0x138, ///< BeginSetCoresTscFreqSel - TP_ENDSETCORESTSCFREQSEL = 0x139, ///< EndSetCoresTscFreqSel - TP_BEGINMEMFMCTMEMCLR_INIT = 0x13A, ///< BeginMemFMctMemClr_Init - TP_ENDNMEMFMCTMEMCLR_INIT = 0x13B, ///< EndnMemFMctMemClr_Init - TP_BEGINMEMBEFOREMEMDATAINIT = 0x13C, ///< BeginMemBeforeMemDataInit - TP_ENDMEMBEFOREMEMDATAINIT = 0x13D, ///< EndMemBeforeMemDataInit - TP_BEGINPROCAMDMEMAUTO = 0x13E, ///< BeginProcAmdMemAuto - TP_ENDPROCAMDMEMAUTO = 0x13F, ///< EndProcAmdMemAuto - TP_BEGINMEMMFLOWC32 = 0x140, ///< BeginMemMFlowC32 - TP_ENDMEMMFLOWC32 = 0x141, ///< EndMemMFlowC32 - TP_BEGINMEMINITIALIZEMCT = 0x142, ///< BeginMemInitializeMCT - TP_ENDMEMINITIALIZEMCT = 0x143, ///< EndMemInitializeMCT - TP_BEGINMEMSYSTEMMEMORYMAPPING = 0x144, ///< BeginMemSystemMemoryMapping - TP_ENDMEMSYSTEMMEMORYMAPPING = 0x145, ///< EndMemSystemMemoryMapping - TP_BEGINMEMDRAMTRAINING = 0x146, ///< BeginMemDramTraining - TP_ENDMEMDRAMTRAINING = 0x147, ///< EndMemDramTraining - TP_BEGINMEMOTHERTIMING = 0x148, ///< BeginMemOtherTiming - TP_ENDMEMOTHERTIMING = 0x149, ///< EndMemOtherTiming - TP_BEGINMEMUMAMEMTYPING = 0x14A, ///< BeginMemUMAMemTyping - TP_ENDMEMUMAMEMTYPING = 0x14B, ///< EndMemUMAMemTyping - TP_BEGINMEMMEMCLR = 0x14C, ///< BeginMemMemClr - TP_ENDMEMMEMCLR = 0x14D, ///< EndMemMemClr - TP_BEGINMEMMFLOWTN = 0x14E, ///< BeginMemMFlowTN - TP_ENDMEMMFLOWTN = 0x14F, ///< EndMemMFlowTN - TP_BEGINAGESAHOOKBEFOREDRAMINIT = 0x150, ///< BeginAgesaHookBeforeDramInit - TP_ENDAGESAHOOKBEFOREDRAMINIT = 0x151, ///< EndAgesaHookBeforeDramInit - TP_BEGINPROCMEMDRAMTRAINING = 0x152, ///< BeginProcMemDramTraining - TP_ENDPROCMEMDRAMTRAINING = 0x153, ///< EndProcMemDramTraining - TP_BEGINGNBINITATRTB = 0x154, ///< BeginGnbInitAtRtb - TP_ENDGNBINITATRTB = 0x155, ///< EndGnbInitAtRtb - TP_BEGINGNBLOADSCSDATA = 0x156, ///< BeginGnbLoadScsData - TP_ENDGNBLOADSCSDATA = 0x157, ///< EndGnbLoadScsData - TP_BEGINGNBPCIETRAINING = 0x158, ///< BeginGnbPcieTraining - TP_ENDGNBPCIETRAINING = 0x159, ///< EndGnbPcieTraining - TP_BEGINDISPATCHCPUFEATURESINITRTB = 0x15A, ///< BeginDispatchCpuFeaturesInitRtb - TP_ENDDISPATCHCPUFEATURESINITRTB = 0x15B, ///< EndDispatchCpuFeaturesInitRtb - TP_BEGINAMDCPUMID = 0x15C, ///< BeginAmdCpuEarly - TP_ENDAMDCPUMID = 0x15D, ///< EndAmdCpuEarly - TP_BEGINAMDGNBMIDLATE = 0x15E, ///< BeginAmdGnbMidLate - TP_ENDAMDAMDGNBMIDLATE = 0x15F, ///< EndAmdGnbMidLate - IDS_TP_END ///< End of IDS TP list - } IDS_PERF_DATA; #endif diff --git a/src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h b/src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h index d53878f..167ac6f 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h @@ -45,22 +45,4 @@ #ifndef _IDS_LIB_H_ #define _IDS_LIB_H_ -/// Data Structure of Parameters for TestPoint_TSC. -typedef struct { - UINT32 LineInFile; ///< Line of current time counter - UINT64 Description; ///<Description ID - UINT64 StartTsc; ///< The StartTimer of TestPoint_TSC -} TestPoint_TSC; - -#define RESERVED_TP_NUMER 0x20 -#define MAX_PERFORMANCE_UNIT_NUM (IDS_TP_END - TP_BEGINPROCAMDINITEARLY + 1 + RESERVED_TP_NUMER) -/// Data Structure of Parameters for TP_Perf_STRUCT. -typedef struct { - UINT32 Signature; ///< "PERF" - UINT32 Version; ///< version - UINT32 Index; ///< The Index of TP_Perf_STRUCT - UINT32 TscInMhz; ///< Tsc counter in 1 mhz - TestPoint_TSC TP[MAX_PERFORMANCE_UNIT_NUM]; ///< The TP of TP_Perf_STRUCT -} TP_Perf_STRUCT; - #endif //_IDS_LIB_H_ -- To view, visit https://review.coreboot.org/28369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I941a67a8889a9dbf35c9fd511c7f670623204134 Gerrit-Change-Number: 28369 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

1 0

Change in coreboot[master]: Documentation: add util/pmh7tool to util.md
by Evgeny Zinoviev (Code Review) 27 Aug '18

27 Aug '18

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/28368 Change subject: Documentation: add util/pmh7tool to util.md ...................................................................... Documentation: add util/pmh7tool to util.md Change-Id: Iab5daf101a9ff27aa49b7849bf6bf39362b8db09 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.com> --- M Documentation/util.md 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/28368/1 diff --git a/Documentation/util.md b/Documentation/util.md index 72355e3..10dfe59 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -77,6 +77,7 @@ * __nvidia__ - nvidia blob parsers * __nvramtool__ - Reads and writes coreboot parameters and displaying information from the coreboot table in CMOS/NVRAM. `C` +* __pmh7tool__ - Dumps PMH7 registers on Lenovo ThinkPads. `C` * __post__ - Userspace utility that can be used to test POST cards. `C` * __qualcomm__ - CMM script to debug Qualcomm coreboot environments. `CMM` -- To view, visit https://review.coreboot.org/28368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iab5daf101a9ff27aa49b7849bf6bf39362b8db09 Gerrit-Change-Number: 28368 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com>

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Change in coreboot[master]: mb/intel/coffeelake_rvp: GPIO support for whiskey board
by Lijian Zhao (Code Review) 27 Aug '18

27 Aug '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/28367 Change subject: mb/intel/coffeelake_rvp: GPIO support for whiskey board ...................................................................... mb/intel/coffeelake_rvp: GPIO support for whiskey board Add gpio programming difference for whiskeylake rvp platform. BUG=N/A TEST=N/A Change-Id: I35a0384f828fd3219e0c3adb4830f5bdab800e32 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/28367/1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index fe5a1a8..576c522 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -263,6 +263,9 @@ /* H21 : GPPC_H_21 */ /* H22 : GPPC_H_22 */ PAD_CFG_GPI(GPP_H22, NONE, DEEP), +#if IS_ENABLED(CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP) + PAD_CFG_GPO(GPP_H22, 1, PLTRST), +#endif /* H23 : GPPC_H_23 */ /* GPD */ @@ -292,7 +295,8 @@ return gpio_table; } -const struct pad_config *__weak variant_early_gpio_table(size_t *num) +const struct pad_config *__weak + variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; @@ -302,7 +306,7 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *__weak variant_cros_gpios(size_t *num) +const struct cros_gpio * __weak variant_cros_gpios(size_t *num) { *num = ARRAY_SIZE(cros_gpios); return cros_gpios; -- To view, visit https://review.coreboot.org/28367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I35a0384f828fd3219e0c3adb4830f5bdab800e32 Gerrit-Change-Number: 28367 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/cannonlake: Fix comment errors for SMBUS
by Lijian Zhao (Code Review) 27 Aug '18

27 Aug '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/28366 Change subject: soc/intel/cannonlake: Fix comment errors for SMBUS ...................................................................... soc/intel/cannonlake: Fix comment errors for SMBUS On CannonLake PCH, SMBUS stays at Bus 0 Device 31 and Function 4, previous comment in southbridge.asl mention it as Function 3 that was a mistake. BUG=N/A TEST=N/A Change-Id: I29786457379809b6fcb592e1136ff612539e24dc Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/acpi/southbridge.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/28366/1 diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 4a62485..e4f29b6 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -37,7 +37,7 @@ /* Serial IO */ #include "serialio.asl" -/* SMBus 0:1f.3 */ +/* SMBus 0:1f.4 */ #include "smbus.asl" /* USB XHCI 0:14.0 */ -- To view, visit https://review.coreboot.org/28366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I29786457379809b6fcb592e1136ff612539e24dc Gerrit-Change-Number: 28366 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

1 0

Change in coreboot[master]: Documentation: Fix make rule for sphinx-autobuild
by Martin Roth (Code Review) 27 Aug '18

27 Aug '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28326 ) Change subject: Documentation: Fix make rule for sphinx-autobuild ...................................................................... Documentation: Fix make rule for sphinx-autobuild Execute sphinx-autobuild for livesphinx make rule Change-Id: I725392f1f132101eede8fed75e8d225c972ad1fe Signed-off-by: Tom Hiller <thrilleratplay(a)gmail.com> Reviewed-on: https://review.coreboot.org/28326 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/Makefile.sphinx 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/Documentation/Makefile.sphinx b/Documentation/Makefile.sphinx index 8c10a9f..5236f3e 100644 --- a/Documentation/Makefile.sphinx +++ b/Documentation/Makefile.sphinx @@ -57,7 +57,7 @@ .PHONY: livehtml livehtml: - $(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR) + $(SPHINXAUTOBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR) @echo @echo "Autobuild finished. The HTML pages are in $(BUILDDIR)." -- To view, visit https://review.coreboot.org/28326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I725392f1f132101eede8fed75e8d225c972ad1fe Gerrit-Change-Number: 28326 Gerrit-PatchSet: 2 Gerrit-Owner: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/nvidia: Change ENODATA to ENOATTR for FreeBSD
by Martin Roth (Code Review) 27 Aug '18

27 Aug '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28365 Change subject: util/nvidia: Change ENODATA to ENOATTR for FreeBSD ...................................................................... util/nvidia: Change ENODATA to ENOATTR for FreeBSD FreeBSD doesn't have ENODATA defined, so the cbootimage utility wouldn't build. It looks like the BSDs use ENOATTR in the same fashion, so update the error to use that. Change-Id: Ic70710d5726476755585fd1a3ae3f256a430e8df Signed-off-by: Martin Roth <martinr(a)coreboot.org> --- M util/nvidia/Makefile.inc 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/28365/1 diff --git a/util/nvidia/Makefile.inc b/util/nvidia/Makefile.inc index 133778f..1894fad 100644 --- a/util/nvidia/Makefile.inc +++ b/util/nvidia/Makefile.inc @@ -43,6 +43,10 @@ CBOOTIMAGE_OBJS:=$(addprefix $(objutil)/nvidia/cbootimage/,$(patsubst %.c,%.o,$(filter %.c,$(CBOOTIMAGE_RAW_SRCS)))) CBOOTIMAGE_FLAGS:=-Wall -std=c99 -O2 +ifeq ($(OS_ARCH), FreeBSD) +CBOOTIMAGE_FLAGS:=-DENODATA=ENOATTR +endif + additional-dirs += $(sort $(dir $(CBOOTIMAGE_OBJS))) $(objutil)/nvidia/cbootimage/%.o: util/nvidia/cbootimage/src/%.c -- To view, visit https://review.coreboot.org/28365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic70710d5726476755585fd1a3ae3f256a430e8df Gerrit-Change-Number: 28365 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: util/crossgcc: Update fls function name for binutils nds32 patch
by Martin Roth (Code Review) 27 Aug '18

27 Aug '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28363 Change subject: util/crossgcc: Update fls function name for binutils nds32 patch ...................................................................... util/crossgcc: Update fls function name for binutils nds32 patch When building the toolchain in FreeBSD, the function fls conflicts with the native fls function. Just rename this one since it's only used within the single file in the patch. Change-Id: Iff2019bf4fce2e07e4f78605411bb3fc4f324de7 Signed-off-by: Martin Roth <martinr(a)coreboot.org> --- M util/crossgcc/patches/binutils-2.30_nds32.patch 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/28363/1 diff --git a/util/crossgcc/patches/binutils-2.30_nds32.patch b/util/crossgcc/patches/binutils-2.30_nds32.patch index 9608265..88252c4 100644 --- a/util/crossgcc/patches/binutils-2.30_nds32.patch +++ b/util/crossgcc/patches/binutils-2.30_nds32.patch @@ -5839,7 +5839,7 @@ +} + +static unsigned int -+fls (register unsigned int x) ++fls_ (register unsigned int x) +{ + return ffs (x & (-x)); +} @@ -6698,14 +6698,14 @@ - break; + if (1 < ones32 (tls_type)) + { -+ eff_tls_type = 1 << (fls (tls_type) - 1); ++ eff_tls_type = 1 << (fls_ (tls_type) - 1); + /* TLS model shall be handled in nds32_elf_unify_tls_model () */ + + /* TLS model X -> LE is not implement yet! + * workaround here! */ + if (eff_tls_type == GOT_TLS_LE) + { -+ eff_tls_type = 1 << (fls (tls_type ^ eff_tls_type) - 1); ++ eff_tls_type = 1 << (fls_ (tls_type ^ eff_tls_type) - 1); + } + } @@ -11865,7 +11865,7 @@ } - irel_ptr = irel_ptr->next; + -+ eff_tls_type = 1 << (fls (tls_type) - 1); ++ eff_tls_type = 1 << (fls_ (tls_type) - 1); + sethi_rt = N32_RT5(bfd_getb32 (contents + irel->r_offset)); } -- To view, visit https://review.coreboot.org/28363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iff2019bf4fce2e07e4f78605411bb3fc4f324de7 Gerrit-Change-Number: 28363 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: util/abuild: Use env to find bash
by Martin Roth (Code Review) 27 Aug '18

27 Aug '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28364 Change subject: util/abuild: Use env to find bash ...................................................................... util/abuild: Use env to find bash FreeBSD doesn't have bash in /bin, so use env to find it. This is already done in many other scripts that are used in the actual build path. Change-Id: If6fb6bc3c55835e2144599fea1cdb2f7abefb0fc Signed-off-by: Martin Roth <martinr(a)coreboot.org> --- M util/abuild/abuild 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/28364/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index 3831d59..3228d09 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash # # coreboot autobuild # -- To view, visit https://review.coreboot.org/28364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If6fb6bc3c55835e2144599fea1cdb2f7abefb0fc Gerrit-Change-Number: 28364 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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coreboot-gerrit August 2018