coreboot-gerrit August 2018

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Change in coreboot[master]: [WIP] Nvidia Optimus support for ThinkPads
by Patrick Rudolph (Code Review) 29 Aug '18

29 Aug '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28380 ) Change subject: [WIP] Nvidia Optimus support for ThinkPads ...................................................................... Patch Set 2: (2 comments) Good job! I already fixed _ROM a few times... Time to add tests to FWTS. https://review.coreboot.org/#/c/28380/2/src/mainboard/lenovo/t430/cmos.layo… File src/mainboard/lenovo/t430/cmos.layout: https://review.coreboot.org/#/c/28380/2/src/mainboard/lenovo/t430/cmos.layo… PS2, Line 131: Graphics Unrelated to optimus as you can use two GPUs even without it. Please add it in a separate commit. https://review.coreboot.org/#/c/28380/2/src/mainboard/lenovo/t430s/Kconfig File src/mainboard/lenovo/t430s/Kconfig: https://review.coreboot.org/#/c/28380/2/src/mainboard/lenovo/t430s/Kconfig@… PS2, Line 26: DRIVERS_LENOVO_HYBRID_GRAPHICS T430s doesn't have hybrid graphics, as there's no mux at the lvds panel. You could add a CMOS option to enable/disable the dGPU instead. Dynamic power switching using Optimus is possible here too ofc. -- To view, visit https://review.coreboot.org/28380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Gerrit-Change-Number: 28380 Gerrit-PatchSet: 2 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Aug 2018 06:26:33 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Set grip sensor threshold
by Furquan Shaikh (Code Review) 29 Aug '18

29 Aug '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28381 ) Change subject: mb/google/poppy/variants/nautilus: Set grip sensor threshold ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/28381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8a410a23b5e3831fc8e90118b810fc2409a026eb Gerrit-Change-Number: 28381 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Enrico Granata <egranata(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Aug 2018 06:00:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/*/intel: introduce warning when building with no IFD
by Angel Pons (Code Review) 29 Aug '18

29 Aug '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/28382 ) Change subject: src/*/intel: introduce warning when building with no IFD ...................................................................... Patch Set 1: This is probably overkill and overly convoluted, but I have not thought of any better options. Improvement suggestions well appreciated. -- To view, visit https://review.coreboot.org/28382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I42b6b336bb519f3d18b5a41eb20b380636ff5819 Gerrit-Change-Number: 28382 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 29 Aug 2018 03:40:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src/*/intel: introduce warning when building with no IFD
by Angel Pons (Code Review) 29 Aug '18

29 Aug '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28382 Change subject: src/*/intel: introduce warning when building with no IFD ...................................................................... src/*/intel: introduce warning when building with no IFD Add a warning as suggested in patch #28233 with the "CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED" option. Change-Id: I42b6b336bb519f3d18b5a41eb20b380636ff5819 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/skylake/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/firmware/Makefile.inc M src/southbridge/intel/fsp_bd82x6x/Kconfig M src/southbridge/intel/fsp_i89xx/Kconfig M src/southbridge/intel/fsp_rangeley/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 16 files changed, 28 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/28382/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 3e84a50..0ed8572 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -46,6 +46,7 @@ select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS select GENERIC_GPIO_LIB select HAVE_INTEL_FIRMWARE + select INTEL_DESCRIPTOR_MODE_REQUIRED select HAVE_SMI_HANDLER select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index b4dc823..9bd4c24 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -35,6 +35,7 @@ select UDELAY_TSC select SOC_INTEL_COMMON select HAVE_INTEL_FIRMWARE + select INTEL_DESCRIPTOR_MODE_REQUIRED select HAVE_SPI_CONSOLE_SUPPORT select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 607d78c..906a0c4 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -43,6 +43,7 @@ select UDELAY_TSC select USE_GENERIC_FSP_CAR_INC select HAVE_INTEL_FIRMWARE + select INTEL_DESCRIPTOR_MODE_REQUIRED select HAVE_SPI_CONSOLE_SUPPORT select HAVE_FSP_GOP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 32148c4..dd5548b 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -36,6 +36,7 @@ select UDELAY_TSC select SOC_INTEL_COMMON select HAVE_INTEL_FIRMWARE + select INTEL_DESCRIPTOR_MODE_REQUIRED select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select HAVE_SPI_CONSOLE_SUPPORT select CPU_INTEL_COMMON diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index ef39706..351f4b7 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -37,6 +37,7 @@ select HAVE_FSP_GOP select HAVE_HARD_RESET select HAVE_INTEL_FIRMWARE + select INTEL_DESCRIPTOR_MODE_REQUIRED select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 68084bc..d17598b 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -42,6 +42,7 @@ select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_INTEL_FIRMWARE + select INTEL_DESCRIPTOR_MODE_REQUIRED select HAVE_SPI_CONSOLE_SUPPORT # Microcode header files are delivered in FSP package diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index cc3e6e2..08b3b0f 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -23,6 +23,7 @@ # Microcode header files are delivered in FSP package select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN select HAVE_INTEL_FIRMWARE + select INTEL_DESCRIPTOR_MODE_REQUIRED select SMM_TSEG select HAVE_SMI_HANDLER select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 9412b03..7066eb0 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -33,6 +33,7 @@ select HAVE_FSP_GOP select HAVE_HARD_RESET select HAVE_INTEL_FIRMWARE + select INTEL_DESCRIPTOR_MODE_REQUIRED select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select INTEL_GMA_ACPI diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index c028595..b073d26 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -38,6 +38,7 @@ select COMMON_FADT select ACPI_SATA_GENERATOR select HAVE_INTEL_FIRMWARE + select INTEL_DESCRIPTOR_MODE_REQUIRED select SOUTHBRIDGE_INTEL_COMMON_GPIO select RTC select HAVE_INTEL_CHIPSET_LOCKDOWN diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 4f8a407..be1203a 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -25,6 +25,11 @@ config SOUTHBRIDGE_INTEL_COMMON_SMM def_bool n +config INTEL_DESCRIPTOR_MODE_REQUIRED + # This config states that the platform *requires* running in + # descriptor mode to be usable (prevent Platform Disable Wait). + def_bool n + config INTEL_CHIPSET_LOCKDOWN depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS #ChromeOS's payload seems to handle finalization on its on. diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 426863c..1b7e320 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -20,9 +20,7 @@ # that adds additional components to the final firmware # image outside of CBFS -ifeq ($(CONFIG_HAVE_IFD_BIN),y) INTERMEDIATE+=add_intel_firmware -endif IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) ifneq ($(call strip_quotes,$(CONFIG_IFD_CHIPSET)),) @@ -30,6 +28,7 @@ endif add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) +ifeq ($(CONFIG_HAVE_IFD_BIN),y) printf " DD Adding Intel Firmware Descriptor\n" dd if=$(IFD_BIN_PATH) \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 @@ -85,6 +84,14 @@ mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif +else ifeq ($(CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED),y) + printf "\n\t** WARNING **\n" + printf "coreboot will be built without an Intel Firmware Descriptor.\n" + printf "Never write a complete coreboot.rom without an IFD to your\n" + printf "board's flash chip! You can use flashrom's IFD or layout\n" + printf "parameters to flash only to the BIOS region.\n\n" +endif + PHONY+=add_intel_firmware endif diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index 877a335..9c12d40 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -30,6 +30,7 @@ select PCIEXP_COMMON_CLOCK select COMMON_FADT select HAVE_INTEL_FIRMWARE + select INTEL_DESCRIPTOR_MODE_REQUIRED select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig index d0cb45c..b899567 100644 --- a/src/southbridge/intel/fsp_i89xx/Kconfig +++ b/src/southbridge/intel/fsp_i89xx/Kconfig @@ -30,6 +30,7 @@ select PCIEXP_COMMON_CLOCK select COMMON_FADT select HAVE_INTEL_FIRMWARE + select INTEL_DESCRIPTOR_MODE_REQUIRED select NO_EARLY_BOOTBLOCK_POSTCODES select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index ab85ec4..44412c9 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -30,6 +30,7 @@ select PCIEXP_COMMON_CLOCK select SPI_FLASH select HAVE_INTEL_FIRMWARE + select INTEL_DESCRIPTOR_MODE_REQUIRED select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index d377950..727c630 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -36,6 +36,7 @@ select COMMON_FADT select ACPI_SATA_GENERATOR select HAVE_INTEL_FIRMWARE + select INTEL_DESCRIPTOR_MODE_REQUIRED select SOUTHBRIDGE_INTEL_COMMON_GPIO select HAVE_INTEL_CHIPSET_LOCKDOWN diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index ee870fc..5a07b7e 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -31,6 +31,7 @@ select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select HAVE_INTEL_FIRMWARE + select INTEL_DESCRIPTOR_MODE_REQUIRED select HAVE_SPI_CONSOLE_SUPPORT select RTC select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP -- To view, visit https://review.coreboot.org/28382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I42b6b336bb519f3d18b5a41eb20b380636ff5819 Gerrit-Change-Number: 28382 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Set grip sensor threshold
by Seunghwan Kim (Code Review) 29 Aug '18

29 Aug '18

Hello Enrico Granata, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28381 to look at the new patch set (#2). Change subject: mb/google/poppy/variants/nautilus: Set grip sensor threshold ...................................................................... mb/google/poppy/variants/nautilus: Set grip sensor threshold Set threshold parameter for grip sensor STH9321 .ProxCtrl6: 75 .ProxCtrl7: 99 BUG=b:113303916 BRANCH=poppy TEST=Built and verified parameter passed to driver Change-Id: I8a410a23b5e3831fc8e90118b810fc2409a026eb Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/poppy/variants/nautilus/devicetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/28381/2 -- To view, visit https://review.coreboot.org/28381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8a410a23b5e3831fc8e90118b810fc2409a026eb Gerrit-Change-Number: 28381 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Enrico Granata <egranata(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com>

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Set grip sensor threshold
by Seunghwan Kim (Code Review) 29 Aug '18

29 Aug '18

Seunghwan Kim has uploaded this change for review. ( https://review.coreboot.org/28381 Change subject: mb/google/poppy/variants/nautilus: Set grip sensor threshold ...................................................................... mb/google/poppy/variants/nautilus: Set grip sensor threshold Set threshold parameter for grip sensor STH9321 .ProxCtrl6: 75 .ProxCtrl7: 99 BUG=b:113303916 BRANCH=poppy TEST=Built and verified parameter passed to driver Change-Id: I8a410a23b5e3831fc8e90118b810fc2409a026eb Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/poppy/variants/nautilus/devicetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/28381/1 diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 37edd8a..c26e3bf 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -334,6 +334,13 @@ register "desc" = ""SAR Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A18_IRQ)" register "device_present_gpio" = "GPP_B20" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""STH9321,reg_prox_ctrl6"" + register "property_list[0].integer" = "75" + register "property_list[1].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[1].name" = ""STH9321,reg_prox_ctrl7"" + register "property_list[1].integer" = "99" device i2c 28 on end end end # I2C #2 -- To view, visit https://review.coreboot.org/28381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8a410a23b5e3831fc8e90118b810fc2409a026eb Gerrit-Change-Number: 28381 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com>

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Change in coreboot[master]: [WIP] Nvidia Optimus support for ThinkPads
by Evgeny Zinoviev (Code Review) 29 Aug '18

29 Aug '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28380 to look at the new patch set (#2). Change subject: [WIP] Nvidia Optimus support for ThinkPads ...................................................................... [WIP] Nvidia Optimus support for ThinkPads Based on siro's work #23041. Tested on ThinkPad W530. Enables dual graphics mode for T420, T420s, T520, T430, T430s, T530 mainboards, adds ACPI code for dGPU power management. What works (tested on 4.16.13-gentoo kernel): - power management via _PS0 and _DSM + _PS3 ACPI calls - nouveau driver (with a workaround, see below) - bumblebee (from the "develop" branch) - bbswitch Known problems: - `lspci -s 01:00.0 -vv` turns dGPU on if it was off before. Not sure why it happens (probably it calls _PS0 at some point) or whether it should happen. - nouveau driver unloading (`rmmod` or `modprobe -r`) does not work well: it crashes in nouveau_backlight_exit (invalid pointer). The current hack is to comment out these lines in drivers/gpu/drm/nouveau/nouveau_backlight.c, function `nouveau_backlight_exit`: list_for_each_entry(connector, &drm->bl_connectors, head) { if (connector->id >= 0) ida_simple_remove(&bl_ida, connector->id); } Need to debug why it happens. - VGA ROM for Nvidia GPU is not loaded from BIOS (i.e. coreboot). Need to debug and fix this too. (Or maybe I'm just doing it wrong.) The current workaround is to load it from a file. To do this automatically, create a new file in /etc/modprobe.d with this line: config=NvBios=pci10de-0ffc.rom where "pci10de-0ffc.rom" is a file in /lib/firmware directory (the path is relative to /lib/firmware). VGA ROM has to be extracted from vendor UEFI dump, GUID is 9781FA9D-5A3B-431A-AD59-2748C9A170EC. Not tested yet: - nvidia proprietary driver Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.com> --- A src/drivers/lenovo/hybrid_graphics/acpi/gpu.asl A src/drivers/nvidia/optimus/acpi/optimus.asl A src/ec/lenovo/pmh7/acpi/pmh7.asl M src/mainboard/lenovo/t420/acpi/ec.asl M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420/dsdt.asl M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/acpi/ec.asl M src/mainboard/lenovo/t420s/cmos.layout M src/mainboard/lenovo/t420s/dsdt.asl M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/acpi/ec.asl M src/mainboard/lenovo/t430/cmos.layout M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430/dsdt.asl M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t430s/Makefile.inc M src/mainboard/lenovo/t430s/acpi/ec.asl M src/mainboard/lenovo/t430s/cmos.default M src/mainboard/lenovo/t430s/cmos.layout M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t430s/dsdt.asl M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/acpi/ec.asl M src/mainboard/lenovo/t520/dsdt.asl M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/acpi/ec.asl M src/mainboard/lenovo/t530/cmos.layout M src/mainboard/lenovo/t530/dsdt.asl M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/t530/variants/t530/devicetree.cb M src/mainboard/lenovo/t530/variants/w530/devicetree.cb M src/northbridge/intel/sandybridge/acpi/peg.asl 34 files changed, 427 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/28380/2 -- To view, visit https://review.coreboot.org/28380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Gerrit-Change-Number: 28380 Gerrit-PatchSet: 2 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [WIP] Nvidia Optimus support for ThinkPads
by Evgeny Zinoviev (Code Review) 28 Aug '18

28 Aug '18

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/28380 Change subject: [WIP] Nvidia Optimus support for ThinkPads ...................................................................... [WIP] Nvidia Optimus support for ThinkPads Based on siro's work #23041. Tested on ThinkPad W530. Enables dual graphics mode for T420, T420s, T530, T430, T430s, T530 mainboards, adds ACPI code for dGPU power management. What works (tested on 4.16.13-gentoo kernel): - power management via _PS0 and _DSM + _PS3 ACPI calls - nouveau driver (with a workaround, see below) - bumblebee (from the "develop" branch) - bbswitch Known problems: - `lspci -s 01:00.0 -vv` turns dGPU on if it was off before. Not sure why it happens (probably it calls _PS0 at some point) or whether it should happen. - nouveau driver unloading (`rmmod` or `modprobe -r`) does not work well: it crashes in nouveau_backlight_exit (invalid pointer). The current hack is to comment out these lines in drivers/gpu/drm/nouveau/nouveau_backlight.c, function `nouveau_backlight_exit`: list_for_each_entry(connector, &drm->bl_connectors, head) { if (connector->id >= 0) ida_simple_remove(&bl_ida, connector->id); } Need to debug why it happens. - VGA ROM for Nvidia GPU is not loaded from BIOS (i.e. coreboot). Need to debug and fix this too. The current workaround is to load it from a file. To do this automatically, create a new file in /etc/modprobe.d with this line: config=NvBios=pci10de-0ffc.rom where "pci10de-0ffc.rom" is a file in /lib/firmware directory (the path is relative to /lib/firmware). VGA ROM has to be extracted from vendor UEFI dump, GUID is 9781FA9D-5A3B-431A-AD59-2748C9A170EC. Not tested yet: - nvidia proprietary driver Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.com> --- A src/drivers/lenovo/hybrid_graphics/acpi/gpu.asl A src/drivers/nvidia/optimus/acpi/optimus.asl A src/ec/lenovo/pmh7/acpi/pmh7.asl M src/mainboard/lenovo/t420/acpi/ec.asl M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420/dsdt.asl M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/acpi/ec.asl M src/mainboard/lenovo/t420s/cmos.layout M src/mainboard/lenovo/t420s/dsdt.asl M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/acpi/ec.asl M src/mainboard/lenovo/t430/cmos.layout M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430/dsdt.asl M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t430s/Makefile.inc M src/mainboard/lenovo/t430s/acpi/ec.asl M src/mainboard/lenovo/t430s/cmos.default M src/mainboard/lenovo/t430s/cmos.layout M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t430s/dsdt.asl M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/acpi/ec.asl M src/mainboard/lenovo/t520/dsdt.asl M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/acpi/ec.asl M src/mainboard/lenovo/t530/cmos.layout M src/mainboard/lenovo/t530/dsdt.asl M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/t530/variants/t530/devicetree.cb M src/mainboard/lenovo/t530/variants/w530/devicetree.cb M src/northbridge/intel/sandybridge/acpi/peg.asl 34 files changed, 427 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/28380/1 diff --git a/src/drivers/lenovo/hybrid_graphics/acpi/gpu.asl b/src/drivers/lenovo/hybrid_graphics/acpi/gpu.asl new file mode 100644 index 0000000..feb9d5e --- /dev/null +++ b/src/drivers/lenovo/hybrid_graphics/acpi/gpu.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.PEGP.DEV0) { + Method (_INI) { + // Tell peg.asl that we have _OFF and _ON + Store (One, DEVP) + } + + Method (_OFF) { + \_SB.PCI0.LPCB.PMH7.GPUP(Zero) + } + + Method (_ON) { + \_SB.PCI0.LPCB.PMH7.GPUP(One) + } + + Method (_STA) { + Return (\_SB.PCI0.LPCB.PMH7.GPUS()) + } +} diff --git a/src/drivers/nvidia/optimus/acpi/optimus.asl b/src/drivers/nvidia/optimus/acpi/optimus.asl new file mode 100644 index 0000000..feb2b5d --- /dev/null +++ b/src/drivers/nvidia/optimus/acpi/optimus.asl @@ -0,0 +1,199 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + Scope (\_SB.PCI0.PEGP.DEV0) { + + Name (DGOS, 0x00) + Name (OMPR, 0x02) + Name (HDAS, 0x00) + + Method (NVOP, 4, Serialized) + { + If (LNotEqual (Arg1, 0x0100)) + { + Return (0x80000001) + } + + Store (ToInteger (Arg2), Local0) + + /* Supported Optimus functions advertisement */ + If (LEqual (Local0, 0x00)) + { + Return (Buffer (0x04) + { + 0x09, 0x00, 0x00, 0x06 + }) + } + /* NOUVEAU_DSM_OPTIMUS_CAPS */ + If (LEqual (Local0, 0x1A)) + { + CreateField (Arg3, 0x18, 0x02, OPCE) + CreateField (Arg3, 0x00, 0x01, FLCH) + If (ToInteger (FLCH)) + { + // NOUVEAU_DSM_OPTIMUS_SET_POWERDOWN + // only called if no _PR3 in parent + Store (OPCE, OMPR) + } + + Store (Buffer (0x04) + { + 0x00, 0x00, 0x00, 0x00 + }, Local0) + CreateField (Local0, 0x00, 0x01, OPEN) + CreateField (Local0, 0x03, 0x02, CGCS) + CreateField (Local0, 0x06, 0x01, SHPC) + CreateField (Local0, 0x18, 0x03, DGPC) + CreateField (Local0, 0x1B, 0x02, HDAC) + Store (One, OPEN) // OPTIMUS_ENABLED + Store (One, SHPC) // OPTIMUS_DISPLAY_HOTPLUG + Store (One, DGPC) // OPTIMUS_DYNAMIC_PWR_CAP + If (\_SB.PCI0.PEGP.DEV0._STA ()) + { + Store (0x03, CGCS) // OPTIMUS_STATUS_PWR_STABLE + } + + Store (0x02, HDAC) // OPTIMUS_HDA_CODEC_MASK + Return (Local0) + } + /* NOUVEAU_DSM_OPTIMUS_FLAGS */ + If (LEqual (Local0, 0x1B)) + { + CreateField (Arg3, 0x00, 0x01, HDAU) + CreateField (Arg3, 0x01, 0x01, HDAR) + Store (Buffer (0x04) + { + 0x00, 0x00, 0x00, 0x00 + }, Local0) + CreateField (Local0, 0x02, 0x02, RQGS) + CreateField (Local0, 0x04, 0x01, PWST) + Store (One, PWST) + Store (Zero, RQGS) + If (ToInteger (HDAR)) + { + //VGA switcheroo: Called on card power off + Store (ToInteger (HDAU), HDAS) + } + + Return (Local0) + } + /* NOUVEAU_DSM_POWER */ + If (LEqual (Local0, 3)) + { + // Unused if _PS0 and _PS3 is present ? + If (ToInteger(Arg3)) { + \_SB.PCI0.PEGP.DEV0._ON() + } Else { + \_SB.PCI0.PEGP.DEV0._OFF() + } + } + + Return (0x80000002) + } + + // helper function to compare two buffers + Method (CMP, 2, NotSerialized) + { + If (LNotEqual (0x10, SizeOf (Arg0))) + { + Return (0x00) + } + + If (LNotEqual (0x10, SizeOf (Arg1))) + { + Return (0x00) + } + + Store (0x00, Local0) + While (LLess (Local0, 0x10)) + { + If (LNotEqual (DerefOf (Index (Arg0, Local0)), DerefOf (Index ( + Arg1, Local0)))) + { + Return (0x00) + } + + Increment (Local0) + } + + Return (0x01) + } + + Method (_DSM, 4, NotSerialized) + { + /* NV DSM OPTIMUS */ + If (CMP (Arg0, Buffer (0x10) { + 0xF8, 0xD8, 0x86, 0xA4, 0xDA, 0x0B, 0x1B, 0x47, + 0xA7, 0x2B, 0x60, 0x42, 0xA6, 0xB5, 0xBE, 0xE0})) + { + Return (NVOP (Arg0, Arg1, Arg2, Arg3)) + } + + Return (Buffer (0x04) + { + 0x01, 0x00, 0x00, 0x80 + }) + } + + OperationRegion (RPCS, PCI_Config, 0x00, 0x100) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + VID, 16, + } + + Method (_PS0, 0, NotSerialized) + { + If (\_SB.PCI0.PEGP.DEV0.DGOS) + { + \_SB.PCI0.PEGP.DEV0._ON () + Sleep(50) + + \_SB.PCI0.PEGP._ON () + Sleep(50) + + Store (0x32, Local0) + While (Or(LEqual(VID, 0xffff), LEqual(VID, 0x0000))) + { + Sleep (10) + Decrement (Local0) + } + Store (Zero, HDAS) + Store (Zero, DGOS) + } + } + + Method (_PS1, 0, NotSerialized) + { + } + + Method (_PS2, 0, NotSerialized) + { + } + + Method (_PS3, 0, NotSerialized) + { + If (LEqual (\_SB.PCI0.PEGP.DEV0.OMPR, 0x03)) + { + \_SB.PCI0.PEGP._OFF () + Sleep(50) + + \_SB.PCI0.PEGP.DEV0._OFF () + Sleep(50) + + Store (0x02, \_SB.PCI0.PEGP.DEV0.OMPR) + Store (0x01, \_SB.PCI0.PEGP.DEV0.DGOS) + } + } +} diff --git a/src/ec/lenovo/pmh7/acpi/pmh7.asl b/src/ec/lenovo/pmh7/acpi/pmh7.asl new file mode 100644 index 0000000..1559209 --- /dev/null +++ b/src/ec/lenovo/pmh7/acpi/pmh7.asl @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(PMH7) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + + OperationRegion (CREG, SystemIO, 0x15e0, 0x10) + Field (CREG, ByteAcc, NoLock, Preserve) + { + Offset(0x0c), + ADDR, 16, /* PMH7 has 9-bit address space, which is supported by + pmh7tool, and if some register greater than 0xff was + read before, then 0x0D port must be cleared, otherwise + it won't work (as it contains the wrong address) */ + DATA, 8 + } + + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x50), + , 3, + DPWR, 1, + , 3, + DRST, 1 + } + + // Control dGPU power + Method (GPUP, 1) + { + If (LNotEqual(Arg0, GPUS())) { + If (Arg0) { + Store (Zero, DRST) + Store (One, DPWR) + Sleep (50) + Store (One, DRST) + Sleep (100) + } Else { + Store (Zero, DRST) + Sleep (10) + Store (Zero, DPWR) + } + } + } + + // Return dGPU power state + Method (GPUS) + { + Return (DPWR) + } +} diff --git a/src/mainboard/lenovo/t420/acpi/ec.asl b/src/mainboard/lenovo/t420/acpi/ec.asl index d631f12..faf8f86 100644 --- a/src/mainboard/lenovo/t420/acpi/ec.asl +++ b/src/mainboard/lenovo/t420/acpi/ec.asl @@ -15,6 +15,7 @@ */ #include <ec/lenovo/h8/acpi/ec.asl> +#include <ec/lenovo/pmh7/acpi/pmh7.asl> Scope(\_SB.PCI0.LPCB.EC) { diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index 5a9e570..f55c203 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -129,6 +129,7 @@ 11 6 224M 12 0 Integrated Only 12 1 Discrete Only +12 2 Dual Graphics 13 0 Disable 13 1 AC and battery 13 2 AC only diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl index 7db8344..a4af7cf 100644 --- a/src/mainboard/lenovo/t420/dsdt.asl +++ b/src/mainboard/lenovo/t420/dsdt.asl @@ -50,6 +50,9 @@ } } + #include <drivers/lenovo/hybrid_graphics/acpi/gpu.asl> + #include <drivers/nvidia/optimus/acpi/optimus.asl> + /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index 36e83a3..bef2562 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -30,6 +30,9 @@ early_hybrid_graphics(&igd, &peg); + if (peg && igd) + return; + /* Hide disabled devices */ reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); diff --git a/src/mainboard/lenovo/t420s/acpi/ec.asl b/src/mainboard/lenovo/t420s/acpi/ec.asl index d631f12..faf8f86 100644 --- a/src/mainboard/lenovo/t420s/acpi/ec.asl +++ b/src/mainboard/lenovo/t420s/acpi/ec.asl @@ -15,6 +15,7 @@ */ #include <ec/lenovo/h8/acpi/ec.asl> +#include <ec/lenovo/pmh7/acpi/pmh7.asl> Scope(\_SB.PCI0.LPCB.EC) { diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index f395c0c..2be55f6 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -129,6 +129,7 @@ 11 6 224M 12 0 Integrated Only 12 1 Discrete Only +12 2 Dual Graphics 13 0 Disable 13 1 AC and battery 13 2 AC only diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index c549988..3893114 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -51,6 +51,9 @@ } } + #include <drivers/lenovo/hybrid_graphics/acpi/gpu.asl> + #include <drivers/nvidia/optimus/acpi/optimus.asl> + /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index 55011cf2..be8052c 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -32,6 +32,9 @@ early_hybrid_graphics(&igd, &peg); + if (peg && igd) + return; + /* Hide disabled devices */ reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); diff --git a/src/mainboard/lenovo/t430/acpi/ec.asl b/src/mainboard/lenovo/t430/acpi/ec.asl index 3c7f89d..924bd37 100644 --- a/src/mainboard/lenovo/t430/acpi/ec.asl +++ b/src/mainboard/lenovo/t430/acpi/ec.asl @@ -20,3 +20,4 @@ #define THINKPAD_EC_GPE 17 #include <ec/lenovo/h8/acpi/ec.asl> +#include <ec/lenovo/pmh7/acpi/pmh7.asl> diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout index 2b687c2..1b50e7f 100644 --- a/src/mainboard/lenovo/t430/cmos.layout +++ b/src/mainboard/lenovo/t430/cmos.layout @@ -128,6 +128,7 @@ 11 6 224M 12 0 Integrated Only 12 1 Discrete Only +12 2 Dual Graphics 13 0 Disable 13 1 AC and battery 13 2 AC only diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index d466b36..5eb92bc 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -167,7 +167,7 @@ register "has_backlight_gpio" = "0" register "has_dgpu_power_gpio" = "0" - register "has_thinker1" = "0" + register "has_thinker1" = "1" end chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl index dff8dcd..ad817f0 100644 --- a/src/mainboard/lenovo/t430/dsdt.asl +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -40,4 +40,7 @@ #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } + + #include <drivers/lenovo/hybrid_graphics/acpi/gpu.asl> + #include <drivers/nvidia/optimus/acpi/optimus.asl> } diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index 94679df..90d0886 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -30,6 +30,9 @@ early_hybrid_graphics(&igd, &peg); + if (peg && igd) + return; + /* Hide disabled devices */ reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 728dd5c..a86f9f5 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -23,6 +23,7 @@ select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS select INTEL_GMA_HAVE_VBT + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index cb01f1c..2dab950 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -15,4 +15,5 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += gpio.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t430s/acpi/ec.asl b/src/mainboard/lenovo/t430s/acpi/ec.asl index d631f12..faf8f86 100644 --- a/src/mainboard/lenovo/t430s/acpi/ec.asl +++ b/src/mainboard/lenovo/t430s/acpi/ec.asl @@ -15,6 +15,7 @@ */ #include <ec/lenovo/h8/acpi/ec.asl> +#include <ec/lenovo/pmh7/acpi/pmh7.asl> Scope(\_SB.PCI0.LPCB.EC) { diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default index 979f132..e65869b 100644 --- a/src/mainboard/lenovo/t430s/cmos.default +++ b/src/mainboard/lenovo/t430s/cmos.default @@ -14,3 +14,4 @@ trackpoint=Enable backlight=Both usb_always_on=Disable +hybrid_graphics_mode=Integrated Only diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 538e624..1689b64 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -76,7 +76,8 @@ # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused 440 8 h 0 volume # SandyBridge MRC Scrambler Seed values diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index b14d60c..376ea07 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -159,6 +159,20 @@ register "bdc_gpio_num" = "54" register "bdc_gpio_lvl" = "0" end + chip drivers/lenovo/hybrid_graphics + device pnp ff.f on end # dummy + + register "detect_gpio" = "21" + + register "has_panel_hybrid_gpio" = "1" + register "panel_hybrid_gpio" = "52" + register "panel_integrated_lvl" = "1" + + register "has_backlight_gpio" = "0" + register "has_dgpu_power_gpio" = "0" + + register "has_thinker1" = "1" + end end # LPC Controller device pci 1f.2 on subsystemid 0x17aa 0x21fb diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index c549988..3893114 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -51,6 +51,9 @@ } } + #include <drivers/lenovo/hybrid_graphics/acpi/gpu.asl> + #include <drivers/nvidia/optimus/acpi/optimus.asl> + /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index 3f6d9f2..8b7e396 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -20,8 +20,35 @@ #include <device/pci_def.h> #include <console/console.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <southbridge/intel/bd82x6x/pch.h> +static void hybrid_graphics_init(void) +{ + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + if (peg && igd) + return; + + /* Hide disabled devices */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + else + /* Disable IGD VGA decode, no GTT or GFX stolen */ + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); +} + void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ @@ -64,6 +91,7 @@ } void mainboard_early_init(int s3resume) { + hybrid_graphics_init(); } void mainboard_config_superio(void) diff --git a/src/mainboard/lenovo/t520/acpi/ec.asl b/src/mainboard/lenovo/t520/acpi/ec.asl index d631f12..faf8f86 100644 --- a/src/mainboard/lenovo/t520/acpi/ec.asl +++ b/src/mainboard/lenovo/t520/acpi/ec.asl @@ -15,6 +15,7 @@ */ #include <ec/lenovo/h8/acpi/ec.asl> +#include <ec/lenovo/pmh7/acpi/pmh7.asl> Scope(\_SB.PCI0.LPCB.EC) { diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index 7db8344..39d6d29 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -50,6 +50,9 @@ } } + #include <drivers/lenovo/hybrid_graphics/acpi/gpu.asl> + #include <drivers/nvidia/optimus/acpi/optimus.asl> + /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 328ae37..4fcd651 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -42,6 +42,9 @@ early_hybrid_graphics(&igd, &peg); + if (peg && igd) + return; + /* Hide disabled devices */ reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); diff --git a/src/mainboard/lenovo/t530/acpi/ec.asl b/src/mainboard/lenovo/t530/acpi/ec.asl index d631f12..faf8f86 100644 --- a/src/mainboard/lenovo/t530/acpi/ec.asl +++ b/src/mainboard/lenovo/t530/acpi/ec.asl @@ -15,6 +15,7 @@ */ #include <ec/lenovo/h8/acpi/ec.asl> +#include <ec/lenovo/pmh7/acpi/pmh7.asl> Scope(\_SB.PCI0.LPCB.EC) { diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index 9a099f5..a47b7e8 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -3,6 +3,7 @@ ## ## Copyright (C) 2007-2008 coresystems GmbH ## Copyright (C) 2014 Vladimir Serbinenko +## Copyright (C) 2018 Evgeny Zinoviev ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -129,6 +130,7 @@ 11 6 224M 12 0 Integrated Only 12 1 Discrete Only +12 2 Dual Graphics 13 0 Disable 13 1 AC and battery 13 2 AC only diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index 7db8344..39d6d29 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -50,6 +50,9 @@ } } + #include <drivers/lenovo/hybrid_graphics/acpi/gpu.asl> + #include <drivers/nvidia/optimus/acpi/optimus.asl> + /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index ba7a229..88e07c1 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -34,6 +34,9 @@ early_hybrid_graphics(&igd, &peg); + if (peg && igd) + return; + /* Hide disabled devices */ reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 0da05e0..4dcdc9d 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -157,7 +157,7 @@ register "has_backlight_gpio" = "0" register "has_dgpu_power_gpio" = "0" - register "has_thinker1" = "0" + register "has_thinker1" = "1" end end # LPC bridge device pci 1f.2 on end # SATA Controller 1 diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index d9d9df5..7a72b26 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -179,7 +179,7 @@ register "has_backlight_gpio" = "0" register "has_dgpu_power_gpio" = "0" - register "has_thinker1" = "0" + register "has_thinker1" = "1" end end device pci 1f.2 on # SATA Controller 1 diff --git a/src/northbridge/intel/sandybridge/acpi/peg.asl b/src/northbridge/intel/sandybridge/acpi/peg.asl index f98a4ce..89c2e25 100644 --- a/src/northbridge/intel/sandybridge/acpi/peg.asl +++ b/src/northbridge/intel/sandybridge/acpi/peg.asl @@ -28,6 +28,44 @@ { Name(_ADR, 0x00000000) } + + OperationRegion (RPCS, PCI_Config, 0x00, 0x100) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + Offset (0xb0), // Link Capabilities + , 4, + LNKD, 1, // Link Disable + RTRL, 1, // Retrain Link + Offset (0xb2), // Link Status + , 10, + LNKT, 1, // Link Training + } + + Name (DEVP, 0) + + Method (_ON) + { + Store(Zero, LNKD) + Store(One, RTRL) + + Store (0x32, Local1) + While (Local1) + { + Sleep (10) + If (LEqual(LNKT, 0)) + { + Break + } + + Decrement (Local1) + } + } + + Method (_OFF) + { + Store(One, LNKD) + Sleep (10) + } } Device (PEG1) -- To view, visit https://review.coreboot.org/28380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Gerrit-Change-Number: 28380 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com>

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Change in coreboot[master]: Documentation: add description for util/pmh7tool
by Tom Hiller (Code Review) 28 Aug '18

28 Aug '18

Tom Hiller has posted comments on this change. ( https://review.coreboot.org/28368 ) Change subject: Documentation: add description for util/pmh7tool ...................................................................... Patch Set 2: Code-Review+1 Thanks. -- To view, visit https://review.coreboot.org/28368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iab5daf101a9ff27aa49b7849bf6bf39362b8db09 Gerrit-Change-Number: 28368 Gerrit-PatchSet: 2 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Aug 2018 22:29:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/vendorcode/amd/agesa/f12: Update microcode to version 0x3000027 2...
by Mike Banon (Code Review) 28 Aug '18

28 Aug '18

Mike Banon has posted comments on this change. ( https://review.coreboot.org/28378 ) Change subject: src/vendorcode/amd/agesa/f12: Update microcode to version 0x3000027 2011-09-13 ...................................................................... Patch Set 1: Code-Review+1 Dear Martin, this f12 microcode is a part of microcode_amd.bin officially released by AMD at linux-firmware (offset 0x217C, size 0x03C0). Please review, I think it could be merged because it is "official". Although I don't have any f12 hardware to test it by myself, it has been tested well by the Linux users because it has been a part of linux-firmware repository since 2013-07-11 : https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git… . P.S. if that matters, I also found exactly the same file at platomav's repository as cpu00300F10_ver03000027_2011-13-09_044B0CEC.bin , SHA256 checksum is 72a4557d3ea16d97ea2b90481f5e463d633a1ff42a056c702351d753ad6f0291 -- To view, visit https://review.coreboot.org/28378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9650fab377d957904318ebb393323c2509cfea26 Gerrit-Change-Number: 28378 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Aug 2018 22:28:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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