coreboot-gerrit August 2018

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Change in coreboot[master]: mainboard/google/kahlee: Enable EC firmware update screen
by Martin Roth (Code Review) 29 Aug '18

29 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28374 ) Change subject: mainboard/google/kahlee: Enable EC firmware update screen ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28374/1/src/mainboard/google/kahlee/Kconfig File src/mainboard/google/kahlee/Kconfig: https://review.coreboot.org/#/c/28374/1/src/mainboard/google/kahlee/Kconfig… PS1, Line 101: if VBOOT_EC_SOFTWARE_SYNC > nit: VBOOT_EC_SLOW_UPDATE already has a 'depends on VBOOT_EC_SOFTWARE_SYNC', this if clause is prett […] Unfortunately, select statements override "depends on", so the 'if' is needed. >From the Kconfig doc: https://doc.coreboot.org/getting_started/kconfig.html Select statement usage The ‘select’ keyword forces the value of a symbol with a bool type to ‘y’. It overrides any dependencies of the symbol, so using it carelessly can lead to unpredictable results. -- To view, visit https://review.coreboot.org/28374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I95fc4d3430bac66c09f57a4d34abde08752e5f0e Gerrit-Change-Number: 28374 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Aug 2018 15:45:35 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/drivers/spi/tpm: Fix typo
by Elyes HAOUAS (Code Review) 29 Aug '18

29 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28387 Change subject: src/drivers/spi/tpm: Fix typo ...................................................................... src/drivers/spi/tpm: Fix typo Change-Id: Ifb1e024821153865dd4a27a100f8a9c61151e0e1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/spi/tpm/tpm.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/28387/1 diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 3206ba1..ac9cf24 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -442,7 +442,7 @@ for (retries = 15; retries > 0; retries--) { int i; - /* In case of falure to read div_vid is set to zero. */ + /* In case of failure to read div_vid is set to zero. */ tpm2_read_reg(TPM_DID_VID_REG, &did_vid, sizeof(did_vid)); for (i = 0; i < ARRAY_SIZE(supported_did_vids); i++) -- To view, visit https://review.coreboot.org/28387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifb1e024821153865dd4a27a100f8a9c61151e0e1 Gerrit-Change-Number: 28387 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: chromeec: PS2K node can't be under SIO node
by Martin Roth (Code Review) 29 Aug '18

29 Aug '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28386 Change subject: chromeec: PS2K node can't be under SIO node ...................................................................... chromeec: PS2K node can't be under SIO node Some operating systems won't find the keyboard if it is under the SIO node. BRANCH=none BUG=none TEST=Boot Windows, observe that keyboard is working Original-Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Original-Change-Id: I76b1ca9bf9243ffa861bed9c356a45377e7f43ef Original-Reviewed-on: https://chromium-review.googlesource.com/895364 Change-Id: If99e15bef2173c44cecaa8fdeaa69381bd0e499a Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/ec/google/chromeec/acpi/superio.asl 1 file changed, 28 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/28386/1 diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index 6c9cb2c..0f37570 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -131,21 +131,34 @@ }) } #endif +} #ifdef SIO_EC_ENABLE_PS2K - Device (PS2K) // Keyboard +Device (PS2K) // Keyboard +{ + Name (_UID, 0) + Name (_ADR, 0) + Name (_HID, "GOOG000A") + Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } ) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() { - Name (_UID, 0) - Name (_ADR, 0) - Name (_HID, "GOOG000A") - Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } ) + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) +#ifdef SIO_EC_PS2K_IRQ + SIO_EC_PS2K_IRQ +#else + IRQ (Edge, ActiveHigh, Exclusive) {1} +#endif + }) - Method (_STA, 0, NotSerialized) { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate() - { + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) { IO (Decode16, 0x60, 0x60, 0x01, 0x01) IO (Decode16, 0x64, 0x64, 0x01, 0x01) #ifdef SIO_EC_PS2K_IRQ @@ -153,17 +166,10 @@ #else IRQ (Edge, ActiveHigh, Exclusive) {1} #endif - }) - - Name (_PRS, ResourceTemplate() - { - StartDependentFn (0, 0) { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) -#ifdef SIO_EC_PS2K_IRQ - SIO_EC_PS2K_IRQ -#else - IRQ (Edge, ActiveHigh, Exclusive) {1} + } + EndDependentFn () + }) +} #endif } EndDependentFn () -- To view, visit https://review.coreboot.org/28386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If99e15bef2173c44cecaa8fdeaa69381bd0e499a Gerrit-Change-Number: 28386 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <reinauer(a)chromium.org>

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Change in coreboot[master]: intel/fsp2_0: automatically split FSP into fsp{t, m, s}.bin
by Krystian Hebel (Code Review) 29 Aug '18

29 Aug '18

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/28385 Change subject: intel/fsp2_0: automatically split FSP into fsp{t,m,s}.bin ...................................................................... intel/fsp2_0: automatically split FSP into fsp{t,m,s}.bin Automatically splited binary is used if all of the following are true: - CONFIG_PLATFORM_USES_FSP2_0 is set - supported processor family is used - CONFIG_FSP_x_FILE is not set, so existing platform configs won't break. Tested on custom board with Intel i7-6500U CPU. Change-Id: Ic7b7ab6197e72ef06f90d4fc41d937cbb570bbbc Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/drivers/intel/fsp2_0/Makefile.inc 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/28385/1 diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index d5709ad..fc75ccc 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -15,6 +15,28 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) +FAMILIES := APOLLOLAKE COFFEELAKE DENVERTON_NS KABYLAKE SKYLAKE +FAMILY := $(subst CONFIG_SOC_INTEL_,,$(strip \ + $(foreach F, $(FAMILIES), $(filter %$(F),$(.VARIABLES))))) + +ifneq ($(FAMILY),) +$(info $(shell python ./util/fsptool/SplitFsp.py $(FAMILY))) +endif + +ifeq ($(CONFIG_FSP_T_FILE),"") +undefine CONFIG_FSP_T_FILE +endif +ifeq ($(CONFIG_FSP_M_FILE),"") +undefine CONFIG_FSP_M_FILE +endif +ifeq ($(CONFIG_FSP_S_FILE),"") +undefine CONFIG_FSP_S_FILE +endif + +CONFIG_FSP_T_FILE ?= $(obj)/fspt.bin +CONFIG_FSP_M_FILE ?= $(obj)/fspm.bin +CONFIG_FSP_S_FILE ?= $(obj)/fsps.bin + romstage-y += debug.c romstage-y += hand_off_block.c romstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c -- To view, visit https://review.coreboot.org/28385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic7b7ab6197e72ef06f90d4fc41d937cbb570bbbc Gerrit-Change-Number: 28385 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel (1002088)

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Change in coreboot[master]: intel/fsp2_0: automatically split FSP into fsp{t, m, s}.bin
by Krystian Hebel (Code Review) 29 Aug '18

29 Aug '18

Krystian Hebel has abandoned this change. ( https://review.coreboot.org/28376 ) Change subject: intel/fsp2_0: automatically split FSP into fsp{t,m,s}.bin ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/28376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: If8213b665fb12a8b2c884c74931bad5b0a66c5fb Gerrit-Change-Number: 28376 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel (1002088) Gerrit-Reviewer: Krystian Hebel (1002088) Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com>

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Change in coreboot[master]: [WIP] Nvidia Optimus support for ThinkPads
by Evgeny Zinoviev (Code Review) 29 Aug '18

29 Aug '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28380 to look at the new patch set (#3). Change subject: [WIP] Nvidia Optimus support for ThinkPads ...................................................................... [WIP] Nvidia Optimus support for ThinkPads Based on siro's work #23041. Tested on ThinkPad W530. Enables dual graphics mode for T420, T420s, T520, T430, T430s, T530 mainboards, adds ACPI code for dGPU power management. What works (tested on 4.16.13-gentoo kernel): - power management via _PS0 and _DSM + _PS3 ACPI calls - nouveau driver (with a workaround, see below) - bumblebee (from the "develop" branch) - bbswitch Known problems: - `lspci -s 01:00.0 -vv` turns dGPU on if it was off before. Not sure why it happens (probably it calls _PS0 at some point) or whether it should happen. - nouveau driver unloading (`rmmod` or `modprobe -r`) does not work well: it crashes in nouveau_backlight_exit (invalid pointer). The current hack is to comment out these lines in drivers/gpu/drm/nouveau/nouveau_backlight.c, function `nouveau_backlight_exit`: list_for_each_entry(connector, &drm->bl_connectors, head) { if (connector->id >= 0) ida_simple_remove(&bl_ida, connector->id); } Need to debug why it happens. - VGA ROM for Nvidia GPU is not loaded from BIOS (i.e. coreboot). Need to debug and fix this too. (Or maybe I'm just doing it wrong.) The current workaround is to load it from a file. To do this automatically, create a new file in /etc/modprobe.d with this line: options nouveau config=NvBios=pci10de-0ffc.rom where "pci10de-0ffc.rom" is a file in /lib/firmware directory (the path is relative to /lib/firmware). VGA ROM has to be extracted from vendor UEFI dump, GUID is 9781FA9D-5A3B-431A-AD59-2748C9A170EC. Not tested yet: - nvidia proprietary driver Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.com> --- A src/drivers/lenovo/hybrid_graphics/acpi/gpu.asl A src/drivers/nvidia/optimus/acpi/optimus.asl A src/ec/lenovo/pmh7/acpi/pmh7.asl M src/mainboard/lenovo/t420/acpi/ec.asl M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420/dsdt.asl M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/acpi/ec.asl M src/mainboard/lenovo/t420s/cmos.layout M src/mainboard/lenovo/t420s/dsdt.asl M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/acpi/ec.asl M src/mainboard/lenovo/t430/cmos.layout M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430/dsdt.asl M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t430s/Makefile.inc M src/mainboard/lenovo/t430s/acpi/ec.asl M src/mainboard/lenovo/t430s/cmos.default M src/mainboard/lenovo/t430s/cmos.layout M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t430s/dsdt.asl M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/acpi/ec.asl M src/mainboard/lenovo/t520/dsdt.asl M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/acpi/ec.asl M src/mainboard/lenovo/t530/cmos.layout M src/mainboard/lenovo/t530/dsdt.asl M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/t530/variants/t530/devicetree.cb M src/mainboard/lenovo/t530/variants/w530/devicetree.cb M src/northbridge/intel/sandybridge/acpi/peg.asl 34 files changed, 427 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/28380/3 -- To view, visit https://review.coreboot.org/28380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Gerrit-Change-Number: 28380 Gerrit-PatchSet: 3 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: add entry assembly file for RAMSTAGE
by Xiang Wang (Code Review) 29 Aug '18

29 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28384 to look at the new patch set (#2). Change subject: riscv: add entry assembly file for RAMSTAGE ...................................................................... riscv: add entry assembly file for RAMSTAGE RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling needs to be moved to ddr memory. So add a assembly file to do this. Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc A src/arch/riscv/assembly_entry.S M src/arch/riscv/include/arch/header.ld 3 files changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28384/2 -- To view, visit https://review.coreboot.org/28384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d Gerrit-Change-Number: 28384 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [WIP] Nvidia Optimus support for ThinkPads
by Evgeny Zinoviev (Code Review) 29 Aug '18

29 Aug '18

Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/28380 ) Change subject: [WIP] Nvidia Optimus support for ThinkPads ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28380/2/src/mainboard/lenovo/t430/cmos.layo… File src/mainboard/lenovo/t430/cmos.layout: https://review.coreboot.org/#/c/28380/2/src/mainboard/lenovo/t430/cmos.layo… PS2, Line 131: Graphics > Unrelated to optimus as you can use two GPUs even without it. Please add it in a separate commit. Do you think I should move has_thinker1 changes in devicetrees to a separate commit too? By the way I'm not sure "has_thinker1" is correct, as they seemingly don't have thinker1 (according to schematics), but dGPU registers still work and it seems it's the only usage of has_thinker1 in coreboot. -- To view, visit https://review.coreboot.org/28380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Gerrit-Change-Number: 28380 Gerrit-PatchSet: 2 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Aug 2018 09:38:56 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: add entry assembly file for RAMSTAGE
by Xiang Wang (Code Review) 29 Aug '18

29 Aug '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/28384 Change subject: riscv: add entry assembly file for RAMSTAGE ...................................................................... riscv: add entry assembly file for RAMSTAGE RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling needs to be moved to ddr memory. So add a assembly file to do this. Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc A src/arch/riscv/assembly_entry.S M src/arch/riscv/include/arch/header.ld 3 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28384/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index c485940..4038964 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -97,6 +97,10 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = +ramstage-y += assembly_entry.S +ramstage-y += mcall.c +ramstage-y += trap_util.S +ramstage-y += trap_handler.c ramstage-y += virtual_memory.c ramstage-y += stages.c ramstage-y += misc.c diff --git a/src/arch/riscv/assembly_entry.S b/src/arch/riscv/assembly_entry.S new file mode 100644 index 0000000..724de92 --- /dev/null +++ b/src/arch/riscv/assembly_entry.S @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/encoding.h> +#include <mcall.h> + +.section ".text._start", "ax", %progbits +.globl _start +_start: + # initialize stack point for each hart + # and the stack must be page-aligned. + # 0xDEADBEEF used to check stack overflow + csrr a0, mhartid + la t0, _stack + slli t1, a0, RISCV_PGSHIFT + add t0, t0, t1 + li t1, 0xDEADBEEF + sd t1, 0(t0) + li t1, RISCV_PGSIZE - HLS_SIZE + add sp, t0, t1 + + # initialize hart-local storage + csrr a0, mhartid + call hls_init + + # initialize entry of interrupt/exception + la t0, trap_entry + csrw mtvec, t0 + + # clear any pending interrupts + csrwi mip, 0 + + call exit_car + # set up the mstatus register for VM + call mstatus_init + tail main + + # These codes need to be implemented on a specific SoC + .weak exit_car +exit_car: + ret + diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld index 3e078d8..2edcd67 100644 --- a/src/arch/riscv/include/arch/header.ld +++ b/src/arch/riscv/include/arch/header.ld @@ -23,6 +23,8 @@ #ifdef __BOOTBLOCK__ ENTRY(_start) +#elif __RAMSTAGE__ +ENTRY(_start) #else ENTRY(stage_entry) #endif -- To view, visit https://review.coreboot.org/28384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d Gerrit-Change-Number: 28384 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: riscv: separately define stack locations at different stages
by Xiang Wang (Code Review) 29 Aug '18

29 Aug '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/28383 Change subject: riscv: separately define stack locations at different stages ...................................................................... riscv: separately define stack locations at different stages BOOTBLOCK/ROMSTAGE run in CAR/scratchpad. When RAMSTAGE begin execution will enable cache, then CAR will disappear. So the Stack will be separated. Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/include/arch/memlayout.h M src/soc/sifive/fu540/include/soc/memlayout.ld 2 files changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/28383/1 diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h index 9097cf5..bbd0231 100644 --- a/src/arch/riscv/include/arch/memlayout.h +++ b/src/arch/riscv/include/arch/memlayout.h @@ -20,6 +20,18 @@ #define STACK(addr, size) REGION(stack, addr, size, 4096) +#if ENV_BOOTBLOCK || ENV_ROMSTAGE +# define CAR_STACK(addr, size) REGION(stack, addr, size, 4096) +#else +# define CAR_STACK(addr, size) +#endif + +#if ENV_RAMSTAGE +# define MEM_STACK(addr, size) REGION(stack, addr, size, 4096) +#else +# define MEM_STACK(addr, size) +#endif + /* TODO: Need to add DMA_COHERENT region like on ARM? */ #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index a03c03d..b9b9c47 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -25,11 +25,12 @@ { L2LIM_START(FU540_L2LIM) BOOTBLOCK(FU540_L2LIM, 64K) - STACK(FU540_L2LIM + 64K, 4K) - PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 68K, 8K) + CAR_STACK(FU540_L2LIM + 64K, 20K) + PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) ROMSTAGE(FU540_L2LIM + 128K, 128K) L2LIM_END(FU540_L2LIM + 2M) DRAM_START(FU540_DRAM) RAMSTAGE(FU540_DRAM, 256K) + MEM_STACK(FU540_DRAM + 256K, 20K) } -- To view, visit https://review.coreboot.org/28383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782 Gerrit-Change-Number: 28383 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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coreboot-gerrit August 2018