coreboot-gerrit August 2018

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Change in coreboot[master]: util/crossgcc: Add GCC 8.1 patch for missing backslash
by Martin Roth (Code Review) 27 Aug '18

27 Aug '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28362 Change subject: util/crossgcc: Add GCC 8.1 patch for missing backslash ...................................................................... util/crossgcc: Add GCC 8.1 patch for missing backslash When building the toolchain under BSDs, this missing backslash is needed. Change-Id: I40b0adaa73b241713493fd74f24c93f85e7aabbe Signed-off-by: Martin Roth <martinr(a)coreboot.org> --- A util/crossgcc/patches/gcc-8.1.0_bsd.patch 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/28362/1 diff --git a/util/crossgcc/patches/gcc-8.1.0_bsd.patch b/util/crossgcc/patches/gcc-8.1.0_bsd.patch new file mode 100644 index 0000000..75b0b65 --- /dev/null +++ b/util/crossgcc/patches/gcc-8.1.0_bsd.patch @@ -0,0 +1,12 @@ +diff -Naur gcc-8.1.0/gcc/ada/link.c gcc-8.1.0_/gcc/ada/link.c +--- gcc-8.1.0/gcc/ada/link.c 2018-01-11 01:55:25.000000000 -0700 ++++ gcc-8.1.0_/gcc/ada/link.c 2018-08-25 20:47:29.274166706 -0600 +@@ -104,7 +104,7 @@ + const char *__gnat_default_libgcc_subdir = "lib"; + + #elif defined (__FreeBSD__) || defined (__DragonFly__) \ +- || defined (__NetBSD__) || defined (__OpenBSD__) ++ || defined (__NetBSD__) || defined (__OpenBSD__) \ + || defined (__QNX__) + const char *__gnat_object_file_option = "-Wl,@"; + const char *__gnat_run_path_option = "-Wl,-rpath,"; -- To view, visit https://review.coreboot.org/28362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I40b0adaa73b241713493fd74f24c93f85e7aabbe Gerrit-Change-Number: 28362 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: Snappy:TESTONLY Test setting is correct.
by TungYang Huang (Code Review) 27 Aug '18

27 Aug '18

TungYang Huang has abandoned this change. ( https://review.coreboot.org/28098 ) Change subject: Snappy:TESTONLY Test setting is correct. ...................................................................... Abandoned Test only -- To view, visit https://review.coreboot.org/28098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ieb6c859bba3aa2e53dfc491465188dccdfce3f40 Gerrit-Change-Number: 28098 Gerrit-PatchSet: 2 Gerrit-Owner: TungYang Huang <Tony-Huang(a)quantatw.com> Gerrit-Reviewer: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/octopus/variants/meep: Add weida touchscreen support
by TungYang Huang (Code Review) 27 Aug '18

27 Aug '18

Hello Tony Huang, I'd like you to do a code review. Please visit https://review.coreboot.org/28361 to review the following change. Change subject: mb/google/octopus/variants/meep: Add weida touchscreen support ...................................................................... mb/google/octopus/variants/meep: Add weida touchscreen support Add weida touchscreen support BUG=none BRANCH=master TEST=emerge-octopus coreboot, and verified that touchscreen works on meep. Change-Id: I4352322820237e4c2289410af6643e15109060a1 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/meep/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/28361/1 diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index 20cd9d1..42bd83b 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -54,6 +54,20 @@ register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""WDHT0002"" + register "generic.desc" = ""WDT Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "130" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end end # - I2C 7 end end -- To view, visit https://review.coreboot.org/28361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4352322820237e4c2289410af6643e15109060a1 Gerrit-Change-Number: 28361 Gerrit-PatchSet: 1 Gerrit-Owner: TungYang Huang <Tony-Huang(a)quantatw.com> Gerrit-Reviewer: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: vendorcode/facebook: Add vendorcode
by Arthur Heymans (Code Review) 27 Aug '18

27 Aug '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/28351 ) Change subject: vendorcode/facebook: Add vendorcode ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/28351/1/src/vendorcode/facebook/Kconfig File src/vendorcode/facebook/Kconfig: https://review.coreboot.org/#/c/28351/1/src/vendorcode/facebook/Kconfig@27 PS1, Line 27: "Enables TIVA hard reset feature" are you sure you don't want this in help instead of bool? Is this something you want to be able to select in menuconfig? https://review.coreboot.org/#/c/28351/1/src/vendorcode/facebook/opencellula… File src/vendorcode/facebook/opencellular/reset.c: https://review.coreboot.org/#/c/28351/1/src/vendorcode/facebook/opencellula… PS1, Line 20: void do_hard_reset(void) : { : } Should it have an empty body? -- To view, visit https://review.coreboot.org/28351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I761ac3d1dcbab9dceb7a4c4f835ca8363680eb03 Gerrit-Change-Number: 28351 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 27 Aug 2018 11:30:53 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: intel/fsp2_0: Add FSP_NXT shared stack feature support
by Aamir Bohra (Code Review) 27 Aug '18

27 Aug '18

Aamir Bohra has uploaded a new patch set (#2). ( https://review.coreboot.org/28358 ) Change subject: intel/fsp2_0: Add FSP_NXT shared stack feature support ...................................................................... intel/fsp2_0: Add FSP_NXT shared stack feature support FSP_NXT implementation is adding features on top of fsp2_0. One such feature is a shared stack implementation that requires coreboot to allocate stack for fspm and fspm then uses the same stack as coreboot. This implementation adds support for shared stack feature. Change-Id: I6581111dbaddfa403eca14100577ccc8a05c4ec7 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/arch/x86/car.ld M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/memory_init.c 3 files changed, 36 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/28358/2 -- To view, visit https://review.coreboot.org/28358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6581111dbaddfa403eca14100577ccc8a05c4ec7 Gerrit-Change-Number: 28358 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: intel/fsp2_0: Add FSP_NXT shared stack feature support
by build bot (Jenkins) (Code Review) 27 Aug '18

27 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28358 ) Change subject: intel/fsp2_0: Add FSP_NXT shared stack feature support ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/28358/1/src/drivers/intel/fsp2_0/memory_ini… File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/#/c/28358/1/src/drivers/intel/fsp2_0/memory_ini… PS1, Line 173: if (!IS_ENABLED(CONFIG_PLATFORM_USES_FSP_NXT)) that open brace { should be on the previous line https://review.coreboot.org/#/c/28358/1/src/drivers/intel/fsp2_0/memory_ini… PS1, Line 178: * FSPM_UPD passed here is populated with default values provided by line over 80 characters https://review.coreboot.org/#/c/28358/1/src/drivers/intel/fsp2_0/memory_ini… PS1, Line 179: * the blob itself. We let FSPM use top of CAR region of the size it line over 80 characters -- To view, visit https://review.coreboot.org/28358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6581111dbaddfa403eca14100577ccc8a05c4ec7 Gerrit-Change-Number: 28358 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 27 Aug 2018 08:41:46 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: intel/fsp2_0: Add FSP_NXT shared stack feature support
by Aamir Bohra (Code Review) 27 Aug '18

27 Aug '18

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/28358 Change subject: intel/fsp2_0: Add FSP_NXT shared stack feature support ...................................................................... intel/fsp2_0: Add FSP_NXT shared stack feature support FSP_NXT implementation is adding features on top of fsp2_0. One such feature is a shared stack implementation that requires coreboot to allocate stack for fspm and fspm then uses the same stack as coreboot. This implementation adds support for shared stack feature. Change-Id: I6581111dbaddfa403eca14100577ccc8a05c4ec7 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/arch/x86/car.ld M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/memory_init.c 3 files changed, 37 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/28358/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 7122776..b0c23c8 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -36,6 +36,9 @@ * the stack size. */ #if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) _car_stack_start = .; +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP_NXT) + . += CONFIG_FSP_NXT_STACK_SIZE; +#endif . += CONFIG_DCACHE_BSP_STACK_SIZE; _car_stack_end = .; #endif diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index f149544..d7bcbd3 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -19,6 +19,13 @@ help Include FSP 2.0 wrappers and functionality +config PLATFORM_USES_FSP_NXT + bool + default n + select PLATFORM_USES_FSP2_0 + help + Include FSP next feature support + if PLATFORM_USES_FSP2_0 config ADD_FSP_BINARIES @@ -133,4 +140,12 @@ This allows deployed systems to bump their version number with the same FSP which will trigger a retrain of the memory. +config FSP_NXT_STACK_SIZE + hex + depends on PLATFORM_USES_FSP_NXT + default 0x20000 + help + Stack size to be allocated for fsp-m. The FSP NXT version expects + the stack being allocated from coreboot and it uses the same stack + as coreboot. endif diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index cf033d7..aa13872 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -170,22 +170,26 @@ bool s3wake, uint32_t fsp_version, const struct memranges *memmap) { - uintptr_t stack_begin; - uintptr_t stack_end; + if (!IS_ENABLED(CONFIG_PLATFORM_USES_FSP_NXT)) + { + uintptr_t stack_begin; + uintptr_t stack_end; + /* + * FSPM_UPD passed here is populated with default values provided by + * the blob itself. We let FSPM use top of CAR region of the size it + * requests. + */ + stack_end = (uintptr_t)_car_region_end; + stack_begin = stack_end - arch_upd->StackSize; + if (check_region_overlap(memmap, "FSPM stack", stack_begin, + stack_end) != CB_SUCCESS) + return CB_ERR; - /* - * FSPM_UPD passed here is populated with default values provided by - * the blob itself. We let FSPM use top of CAR region of the size it - * requests. - */ - stack_end = (uintptr_t)_car_region_end; - stack_begin = stack_end - arch_upd->StackSize; - - if (check_region_overlap(memmap, "FSPM stack", stack_begin, - stack_end) != CB_SUCCESS) - return CB_ERR; - - arch_upd->StackBase = (void *)stack_begin; + arch_upd->StackBase = (void *)stack_begin; + } else { + arch_upd->StackBase = (void *)_car_stack_end; + arch_upd->StackSize = CONFIG_FSP_NXT_STACK_SIZE; + } fsp_fill_mrc_cache(arch_upd, fsp_version); -- To view, visit https://review.coreboot.org/28358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6581111dbaddfa403eca14100577ccc8a05c4ec7 Gerrit-Change-Number: 28358 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com>

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Change in coreboot[master]: Documentation: fix sphinx warnings
by Patrick Rudolph (Code Review) 27 Aug '18

27 Aug '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28354 ) Change subject: Documentation: fix sphinx warnings ...................................................................... Patch Set 2: Code-Review+2 Nice find ! I could't figure out what it was trying to tell me. -- To view, visit https://review.coreboot.org/28354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2b77ad266d1c5f693536e161f96f3db19832989c Gerrit-Change-Number: 28354 Gerrit-PatchSet: 2 Gerrit-Owner: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 27 Aug 2018 07:39:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: riscv: fix to write XS
by Xiang Wang (Code Review) 27 Aug '18

27 Aug '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/28357 Change subject: riscv: fix to write XS ...................................................................... riscv: fix to write XS XS is a read-only field of mstatus. Unable to be write. So remove this code. Change-Id: I3ad6b0029900124ac7cce062e668a0ea5a8b2c0e Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/virtual_memory.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/28357/1 diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 71e2ac9..68936b6 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -39,7 +39,6 @@ uintptr_t ms = 0; ms = INSERT_FIELD(ms, MSTATUS_FS, 3); - ms = INSERT_FIELD(ms, MSTATUS_XS, 3); write_csr(mstatus, ms); // clear any pending timer interrupts. -- To view, visit https://review.coreboot.org/28357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3ad6b0029900124ac7cce062e668a0ea5a8b2c0e Gerrit-Change-Number: 28357 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: riscv: update delegate
by Xiang Wang (Code Review) 27 Aug '18

27 Aug '18

Xiang Wang has uploaded a new patch set (#2). ( https://review.coreboot.org/28356 ) Change subject: riscv: update delegate ...................................................................... riscv: update delegate PMP may trigger an access fault. PMP operations must be in m-mode. So access fault can't be delegate to s-mode. Change-Id: If08220fdbb483ebf323f481ab0c7b012ac7a196c Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/virtual_memory.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/28356/2 -- To view, visit https://review.coreboot.org/28356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: If08220fdbb483ebf323f481ab0c7b012ac7a196c Gerrit-Change-Number: 28356 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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coreboot-gerrit August 2018