Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/28336
to look at the new patch set (#3).
Change subject: soc/cavium: Add dynamic dtb support
......................................................................
soc/cavium: Add dynamic dtb support
* Add a kconfig variable containing the per board
dts name.
* Add auto generation of device tree (DTB) file if
kconfig option is set in the mainboard implementation.
* Fix cavium/cn81xx for dynamic device tree loading.
Change-Id: Ie470092e424b86e04141b8e2bd2b080a5aadcf58
Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
---
M Makefile.inc
M src/mainboard/Kconfig
M src/mainboard/cavium/cn8100_sff_evb/Kconfig
M src/mainboard/cavium/cn8100_sff_evb/Makefile.inc
M src/soc/cavium/cn81xx/Makefile.inc
M src/soc/cavium/cn81xx/soc.c
6 files changed, 34 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/28336/3
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ie470092e424b86e04141b8e2bd2b080a5aadcf58
Gerrit-Change-Number: 28336
Gerrit-PatchSet: 3
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org>
Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/28343 )
Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/28343/1/src/soc/amd/stoneyridge/include/soc…
File src/soc/amd/stoneyridge/include/soc/southbridge.h:
https://review.coreboot.org/#/c/28343/1/src/soc/amd/stoneyridge/include/soc…
PS1, Line 311: #define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18))
> I don't understand... it is enclosed by parenthesis.
probably it should be :
(BIT(16) | BIT(17) | BIT(18))
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Gerrit-Change-Id: I0aa49d567d24c10a2273c5e748cd0c89e83dfd70
Gerrit-Change-Number: 28343
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>
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Gerrit-Comment-Date: Sat, 25 Aug 2018 17:21:33 +0000
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/28345 )
Change subject: drivers/intel/gma: store uint8_t brightness values in mailbox3
......................................................................
Patch Set 1:
Did you notice the conflicting change? :)
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Gerrit-Change-Id: I290b5f5b2a8ee406e39e86d3e0de9997798d890d
Gerrit-Change-Number: 28345
Gerrit-PatchSet: 1
Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/28345
Change subject: drivers/intel/gma: store uint8_t brightness values in mailbox3
......................................................................
drivers/intel/gma: store uint8_t brightness values in mailbox3
The _BCM function requires a percentage value. While the
brightness in mailbox3 requires a value in uint8_t. Meaning 255 = 100%.
Previous implementation stored the percentage brightness value resulting
in limiting the brightness to ~40% of it's maximum power.
Only affects brightness control using mailbox3.
Fixes: 6838aaebf9ec ("drvs/intel/gma/acpi: Add methods to use MBOX3")
Change-Id: I290b5f5b2a8ee406e39e86d3e0de9997798d890d
Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu>
---
M src/drivers/intel/gma/acpi/configure_brightness_levels.asl
1 file changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/28345/1
diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
index 8625f04..0867c5a 100644
--- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
+++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
@@ -69,7 +69,14 @@
Return (Ones)
}
- Store (Or (Arg0, 0x80000000), BCLP)
+ /* BCLP requires brightness unsigned 8bit. 255 = 100 % */
+ Store (Divide (Multiply (Arg0, 255), 100), Local1)
+ If (LGreater(Local1, 255)) {
+ Store (255, Local1)
+ }
+ /* set valid bit */
+ Store (Or (Local1, 0x80000000), BCLP)
+
/* Request back-light change */
Store (0x2, ASLC)
/* Trigger IRQ */
--
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Gerrit-Change-Id: I290b5f5b2a8ee406e39e86d3e0de9997798d890d
Gerrit-Change-Number: 28345
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Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu>
Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/28331 )
Change subject: mb/intel/coffeelake_rvp: Remove superfluous header file
......................................................................
mb/intel/coffeelake_rvp: Remove superfluous header file
TEST: same sha256sum with BUILD_TIMELESS=1.
Change-Id: Icf3368bcf1351f0e7cd4041c3792d76362aec9e5
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28331
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao(a)intel.com>
---
M src/mainboard/intel/coffeelake_rvp/bootblock.c
M src/mainboard/intel/coffeelake_rvp/chromeos.c
M src/mainboard/intel/coffeelake_rvp/mainboard.c
D src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/gpio.h
D src/mainboard/intel/coffeelake_rvp/variants/cfl_u/include/variant/gpio.h
5 files changed, 0 insertions(+), 45 deletions(-)
Approvals:
build bot (Jenkins): Verified
Lijian Zhao: Looks good to me, approved
diff --git a/src/mainboard/intel/coffeelake_rvp/bootblock.c b/src/mainboard/intel/coffeelake_rvp/bootblock.c
index 8655947..cac219e 100644
--- a/src/mainboard/intel/coffeelake_rvp/bootblock.c
+++ b/src/mainboard/intel/coffeelake_rvp/bootblock.c
@@ -16,7 +16,6 @@
#include <baseboard/variants.h>
#include <bootblock_common.h>
#include <soc/gpio.h>
-#include <variant/gpio.h>
void bootblock_mainboard_init(void)
{
diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c
index 6fe27cd..9f7bc41 100644
--- a/src/mainboard/intel/coffeelake_rvp/chromeos.c
+++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c
@@ -18,7 +18,6 @@
#include <gpio.h>
#include <rules.h>
#include <soc/gpio.h>
-#include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
#if ENV_RAMSTAGE
diff --git a/src/mainboard/intel/coffeelake_rvp/mainboard.c b/src/mainboard/intel/coffeelake_rvp/mainboard.c
index 522cfc4..aabb3ed 100644
--- a/src/mainboard/intel/coffeelake_rvp/mainboard.c
+++ b/src/mainboard/intel/coffeelake_rvp/mainboard.c
@@ -20,7 +20,6 @@
#include <soc/gpio.h>
#include <soc/nhlt.h>
#include <vendorcode/google/chromeos/chromeos.h>
-#include <variant/gpio.h>
static void mainboard_init(void *chip_info)
{
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/gpio.h
deleted file mode 100644
index c34a9b3..0000000
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/gpio.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2018 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MAINBOARD_GPIO_H__
-#define __MAINBOARD_GPIO_H__
-
-#include <baseboard/gpio.h>
-
-#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/include/variant/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/include/variant/gpio.h
deleted file mode 100644
index c34a9b3..0000000
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/include/variant/gpio.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2018 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MAINBOARD_GPIO_H__
-#define __MAINBOARD_GPIO_H__
-
-#include <baseboard/gpio.h>
-
-#endif /* __MAINBOARD_GPIO_H__ */
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/28331 )
Change subject: mb/intel/coffeelake_rvp: Remove superfluous header file
......................................................................
Patch Set 2:
> Okay, then I can move all the GPIO programming in gpio.c under
> baseboard.
either that or you can link different gpio.c files for variants.
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Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/28339 )
Change subject: util: Add script to download FSP headers
......................................................................
Patch Set 1:
Do we have some location requirement to run the tool? Like under util ?
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