coreboot-gerrit August 2018

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Change in coreboot[master]: OC fixes WIP
by Philipp Deppenwiese (Code Review) 24 Aug '18

24 Aug '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/28335 Change subject: OC fixes WIP ...................................................................... OC fixes WIP Change-Id: I1ccd0c28e05f5d57f0c2a7575021efbe4ba1c570 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/mainboard/opencellular/Kconfig M src/mainboard/opencellular/Kconfig.name M src/mainboard/opencellular/elgon/Kconfig M src/mainboard/opencellular/elgon/Kconfig.name M src/mainboard/opencellular/elgon/Makefile.inc M src/mainboard/opencellular/rotundu/Kconfig M src/mainboard/opencellular/rotundu/Kconfig.name M src/soc/cavium/cn81xx/soc.c 8 files changed, 10 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/28335/1 diff --git a/src/mainboard/opencellular/Kconfig b/src/mainboard/opencellular/Kconfig index 2df6ba3..1a80c3f 100644 --- a/src/mainboard/opencellular/Kconfig +++ b/src/mainboard/opencellular/Kconfig @@ -25,6 +25,6 @@ config MAINBOARD_VENDOR string - default "OpenCellular" + default "Open Cellular" endif # VENDOR_OPENCELLULAR diff --git a/src/mainboard/opencellular/Kconfig.name b/src/mainboard/opencellular/Kconfig.name index c65882f..fbbca76 100644 --- a/src/mainboard/opencellular/Kconfig.name +++ b/src/mainboard/opencellular/Kconfig.name @@ -1,2 +1,2 @@ config VENDOR_OPENCELLULAR - bool "OpenCellular" + bool "Open Cellular" diff --git a/src/mainboard/opencellular/elgon/Kconfig b/src/mainboard/opencellular/elgon/Kconfig index bd35e9c..37a020a 100644 --- a/src/mainboard/opencellular/elgon/Kconfig +++ b/src/mainboard/opencellular/elgon/Kconfig @@ -42,10 +42,6 @@ string default "opencellular/elgon" -config MAINBOARD_VENDOR - string - default "Open Cellular" - config DRIVER_TPM_I2C_BUS hex default 0x1 @@ -91,4 +87,8 @@ string default "Elgon" +config MAINBOARD_FIT_DTS + string + default "gbcv2.dts" + endif diff --git a/src/mainboard/opencellular/elgon/Kconfig.name b/src/mainboard/opencellular/elgon/Kconfig.name index e0c4290..7d02111 100644 --- a/src/mainboard/opencellular/elgon/Kconfig.name +++ b/src/mainboard/opencellular/elgon/Kconfig.name @@ -1,2 +1,2 @@ config BOARD_OPENCELLULAR_ELGON - bool "Elgon" + bool "Elgon (GBCv2)" diff --git a/src/mainboard/opencellular/elgon/Makefile.inc b/src/mainboard/opencellular/elgon/Makefile.inc index 26de1cc..343a52e 100644 --- a/src/mainboard/opencellular/elgon/Makefile.inc +++ b/src/mainboard/opencellular/elgon/Makefile.inc @@ -29,13 +29,3 @@ verstage-y += memlayout.ld verstage-y += death.c - -MB_DIR = src/mainboard/$(MAINBOARDDIR) - -LINUX_DTB = gbcv2.dtb -build/$(LINUX_DTB): - dtc -p 4096 -I dts -O dtb -o build/$(LINUX_DTB) -i $(MB_DIR) $(MB_DIR)/$(patsubst %.dtb,%.dts,$(LINUX_DTB)) - -cbfs-files-y += $(LINUX_DTB) -$(LINUX_DTB)-file := build/$(LINUX_DTB) -$(LINUX_DTB)-type := raw diff --git a/src/mainboard/opencellular/rotundu/Kconfig b/src/mainboard/opencellular/rotundu/Kconfig index edacf0d..4164768 100644 --- a/src/mainboard/opencellular/rotundu/Kconfig +++ b/src/mainboard/opencellular/rotundu/Kconfig @@ -66,10 +66,6 @@ string default "opencellular/rotundu" -config MAINBOARD_VENDOR - string - default "OpenCellular" - config MAX_CPUS int default 16 diff --git a/src/mainboard/opencellular/rotundu/Kconfig.name b/src/mainboard/opencellular/rotundu/Kconfig.name index 1346b94..37df2e2 100644 --- a/src/mainboard/opencellular/rotundu/Kconfig.name +++ b/src/mainboard/opencellular/rotundu/Kconfig.name @@ -1,7 +1,7 @@ config BOARD_OPENCELLULAR_ROTUNDU - bool "OpenCellular Rotundu (GBCv1)" + bool "Rotundu (GBCv1)" select BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU config BOARD_OPENCELLULAR_SUPABRCKV1 - bool "OpenCellular Supabrck V1 (BRCK)" + bool "Supabrck V1 (BRCK)" select BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 8efcb13..0d10f4e 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -327,7 +327,7 @@ size_t size = 0; - void *ptr = cbfs_boot_map_with_leak("sff8104-linux.dtb", + void *ptr = cbfs_boot_map_with_leak(CONFIG_MAINBOARD_FIT_DTS, CBFS_TYPE_RAW, &size); if (ptr) memcpy(_sff8104, ptr, size); -- To view, visit https://review.coreboot.org/28335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1ccd0c28e05f5d57f0c2a7575021efbe4ba1c570 Gerrit-Change-Number: 28335 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: payloads/tianocore: rebase patches to UDK2018 release
by Patrick Rudolph (Code Review) 24 Aug '18

24 Aug '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/27615 ) Change subject: payloads/tianocore: rebase patches to UDK2018 release ...................................................................... Patch Set 1: Code-Review+1 Tested on QEMU, runs except that Patch 6 doesn't apply. -- To view, visit https://review.coreboot.org/27615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib409f6f93eb64d7a9a2f09a75f8e637ab8689410 Gerrit-Change-Number: 27615 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Aug 2018 11:43:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/cavium/cn81xx: Don't directly manipulate devicetree data
by Philipp Deppenwiese (Code Review) 24 Aug '18

24 Aug '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28266 ) Change subject: soc/cavium/cn81xx: Don't directly manipulate devicetree data ...................................................................... soc/cavium/cn81xx: Don't directly manipulate devicetree data As preparation to constify devicetree data, do it the right way. Change-Id: I5081de020bb73c56aa8bdf7bb17fe6b2913d0ffe Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/28266 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/soc/cavium/cn81xx/soc.c 1 file changed, 16 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Philipp Deppenwiese: Looks good to me, approved diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index dfb06e0..4a4312d 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -241,12 +241,24 @@ __func__); continue; } + + u32 *data_cleaned = malloc(size); + if (!data_cleaned) + continue; + + size_t n = 0; + /* Remove phandle from mmu-masters list */ for (size_t j = 0; j < size / (sizeof(u32) * 2); j++) - if (be32_to_cpu(data[j * 2]) == phandle) { - data[j * 2] = 0; - data[j * 2 + 1] = 0; - break; + if (be32_to_cpu(data[j * 2]) != phandle) { + data_cleaned[n * 2] = data[j * 2]; + data_cleaned[n * 2 + 1] = data[j * 2 + 1]; + n++; } + + dt_add_bin_prop(dt_node, "mmu-masters", data_cleaned, + n * sizeof(u32) * 2); + + free(data_cleaned); } /* Remove QLM mode entries */ -- To view, visit https://review.coreboot.org/28266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I5081de020bb73c56aa8bdf7bb17fe6b2913d0ffe Gerrit-Change-Number: 28266 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: device_tree/fit: Constify data structures
by Philipp Deppenwiese (Code Review) 24 Aug '18

24 Aug '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28267 ) Change subject: device_tree/fit: Constify data structures ...................................................................... device_tree/fit: Constify data structures * Add const quailifier to arguments and elements. * Add casts where necessary in cn81xx/soc. Tested on Cavium CN81xx EVB SFF. Change-Id: Id27966427fb97457fe883be32685d1397fb0781f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/28267 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/include/device_tree.h M src/include/fit.h M src/lib/device_tree.c M src/lib/fit.c M src/lib/fit_payload.c M src/soc/cavium/cn81xx/soc.c 6 files changed, 75 insertions(+), 64 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Julius Werner: Looks good to me, approved diff --git a/src/include/device_tree.h b/src/include/device_tree.h index 4c1a37c..14be832 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -50,7 +50,7 @@ struct fdt_property { const char *name; - void *data; + const void *data; uint32_t size; }; @@ -88,7 +88,7 @@ struct device_tree { - void *header; + const void *header; uint32_t header_size; struct list_node reserve_map; @@ -104,17 +104,18 @@ */ // Read the property, if any, at offset offset. -int fdt_next_property(void *blob, uint32_t offset, struct fdt_property *prop); +int fdt_next_property(const void *blob, uint32_t offset, + struct fdt_property *prop); // Read the name of the node, if any, at offset offset. -int fdt_node_name(void *blob, uint32_t offset, const char **name); +int fdt_node_name(const void *blob, uint32_t offset, const char **name); -void fdt_print_node(void *blob, uint32_t offset); -int fdt_skip_node(void *blob, uint32_t offset); +void fdt_print_node(const void *blob, uint32_t offset); +int fdt_skip_node(const void *blob, uint32_t offset); // Read a flattened device tree into a heirarchical structure which refers to // the contents of the flattened tree in place. Modifying the flat tree // invalidates the unflattened one. -struct device_tree *fdt_unflatten(void *blob); +struct device_tree *fdt_unflatten(const void *blob); @@ -123,12 +124,13 @@ */ // Figure out how big a device tree would be if it were flattened. -uint32_t dt_flat_size(struct device_tree *tree); +uint32_t dt_flat_size(const struct device_tree *tree); // Flatten a device tree into the buffer pointed to by dest. -void dt_flatten(struct device_tree *tree, void *dest); -void dt_print_node(struct device_tree_node *node); +void dt_flatten(const struct device_tree *tree, void *dest); +void dt_print_node(const struct device_tree_node *node); // Read #address-cells and #size-cells properties from a node. -void dt_read_cell_props(struct device_tree_node *node, u32 *addrcp, u32 *sizecp); +void dt_read_cell_props(const struct device_tree_node *node, u32 *addrcp, + u32 *sizecp); // Look up or create a node relative to a parent node, through its path // represented as an array of strings. struct device_tree_node *dt_find_node(struct device_tree_node *parent, const char **path, @@ -148,15 +150,16 @@ struct device_tree_node *dt_find_prop_value(struct device_tree_node *parent, const char *name, void *data, size_t size); // Return the phandle -uint32_t dt_get_phandle(struct device_tree_node *node); +uint32_t dt_get_phandle(const struct device_tree_node *node); // Write src into *dest as a 'length'-byte big-endian integer. void dt_write_int(u8 *dest, u64 src, size_t length); // Delete a property void dt_delete_prop(struct device_tree_node *node, const char *name); // Add different kinds of properties to a node, or update existing ones. -void dt_add_bin_prop(struct device_tree_node *node, const char *name, void *data, - size_t size); -void dt_add_string_prop(struct device_tree_node *node, const char *name, char *str); +void dt_add_bin_prop(struct device_tree_node *node, const char *name, + const void *data, size_t size); +void dt_add_string_prop(struct device_tree_node *node, const char *name, + const char *str); void dt_add_u32_prop(struct device_tree_node *node, const char *name, u32 val); void dt_add_u64_prop(struct device_tree_node *node, const char *name, u64 val); void dt_add_reg_prop(struct device_tree_node *node, u64 *addrs, u64 *sizes, @@ -164,9 +167,10 @@ int dt_set_bin_prop_by_path(struct device_tree *tree, const char *path, void *data, size_t size, int create); -void dt_find_bin_prop(struct device_tree_node *node, const char *name, void **data, - size_t *size); -const char *dt_find_string_prop(struct device_tree_node *node, const char *name); +void dt_find_bin_prop(const struct device_tree_node *node, const char *name, + const void **data, size_t *size); +const char *dt_find_string_prop(const struct device_tree_node *node, + const char *name); /* * Fixups to apply to a kernel's device tree before booting it. diff --git a/src/include/fit.h b/src/include/fit.h index eb51b50..6e0667f 100644 --- a/src/include/fit.h +++ b/src/include/fit.h @@ -27,7 +27,7 @@ struct fit_image_node { const char *name; - void *data; + const void *data; uint32_t size; int compression; @@ -54,7 +54,7 @@ /* * Updates the cmdline in the devicetree. */ -void fit_update_chosen(struct device_tree *tree, char *cmd_line); +void fit_update_chosen(struct device_tree *tree, const char *cmd_line); /* * Add a compat string to the list of supported board ids. diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 89387ff..79561a6 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -28,7 +28,8 @@ * Functions for picking apart flattened trees. */ -int fdt_next_property(void *blob, uint32_t offset, struct fdt_property *prop) +int fdt_next_property(const void *blob, uint32_t offset, + struct fdt_property *prop) { struct fdt_header *header = (struct fdt_header *)blob; uint32_t *ptr = (uint32_t *)(((uint8_t *)blob) + offset); @@ -52,7 +53,7 @@ return index * sizeof(uint32_t); } -int fdt_node_name(void *blob, uint32_t offset, const char **name) +int fdt_node_name(const void *blob, uint32_t offset, const char **name) { uint8_t *ptr = ((uint8_t *)blob) + offset; if (be32toh(*(uint32_t *)ptr) != FDT_TOKEN_BEGIN_NODE) @@ -76,7 +77,7 @@ printk(BIOS_DEBUG, " "); } -static void print_property(struct fdt_property *prop, int depth) +static void print_property(const struct fdt_property *prop, int depth) { print_indent(depth); printk(BIOS_DEBUG, "prop \"%s\" (%d bytes).\n", prop->name, prop->size); @@ -89,7 +90,7 @@ printk(BIOS_DEBUG, "\n"); } -static int print_flat_node(void *blob, uint32_t start_offset, int depth) +static int print_flat_node(const void *blob, uint32_t start_offset, int depth) { int offset = start_offset; const char *name; @@ -116,7 +117,7 @@ return offset - start_offset + sizeof(uint32_t); } -void fdt_print_node(void *blob, uint32_t offset) +void fdt_print_node(const void *blob, uint32_t offset) { print_flat_node(blob, offset, 0); } @@ -127,7 +128,7 @@ * A utility function to skip past nodes in flattened trees. */ -int fdt_skip_node(void *blob, uint32_t start_offset) +int fdt_skip_node(const void *blob, uint32_t start_offset) { int offset = start_offset; int size; @@ -171,7 +172,7 @@ return buf; } -static int fdt_unflatten_node(void *blob, uint32_t start_offset, +static int fdt_unflatten_node(const void *blob, uint32_t start_offset, struct device_tree_node **new_node) { struct list_node *last; @@ -216,12 +217,12 @@ return offset - start_offset + sizeof(uint32_t); } -static int fdt_unflatten_map_entry(void *blob, uint32_t offset, +static int fdt_unflatten_map_entry(const void *blob, uint32_t offset, struct device_tree_reserve_map_entry **new) { - uint64_t *ptr = (uint64_t *)(((uint8_t *)blob) + offset); - uint64_t start = be64toh(ptr[0]); - uint64_t size = be64toh(ptr[1]); + const uint64_t *ptr = (const uint64_t *)(((uint8_t *)blob) + offset); + const uint64_t start = be64toh(ptr[0]); + const uint64_t size = be64toh(ptr[1]); if (!size) return 0; @@ -237,10 +238,10 @@ return sizeof(uint64_t) * 2; } -struct device_tree *fdt_unflatten(void *blob) +struct device_tree *fdt_unflatten(const void *blob) { struct device_tree *tree = malloc(sizeof(*tree)); - struct fdt_header *header = (struct fdt_header *)blob; + const struct fdt_header *header = (const struct fdt_header *)blob; if (!tree) return NULL; memset(tree, 0, sizeof(*tree)); @@ -315,7 +316,7 @@ *struct_size += sizeof(uint32_t); } -uint32_t dt_flat_size(struct device_tree *tree) +uint32_t dt_flat_size(const struct device_tree *tree) { uint32_t size = tree->header_size; struct device_tree_reserve_map_entry *entry; @@ -377,8 +378,9 @@ *strings_start = dstrings; } -static void dt_flatten_node(struct device_tree_node *node, void **struct_start, - void *strings_base, void **strings_start) +static void dt_flatten_node(const struct device_tree_node *node, + void **struct_start, void *strings_base, + void **strings_start) { uint8_t *dstruct = (uint8_t *)*struct_start; uint8_t *dstrings = (uint8_t *)*strings_start; @@ -406,7 +408,7 @@ *strings_start = dstrings; } -void dt_flatten(struct device_tree *tree, void *start_dest) +void dt_flatten(const struct device_tree *tree, void *start_dest) { uint8_t *dest = (uint8_t *)start_dest; @@ -449,7 +451,7 @@ * Functions for printing a non-flattened device tree. */ -static void print_node(struct device_tree_node *node, int depth) +static void print_node(const struct device_tree_node *node, int depth) { print_indent(depth); printk(BIOS_DEBUG, "name = %s\n", node->name); @@ -463,7 +465,7 @@ print_node(child, depth + 1); } -void dt_print_node(struct device_tree_node *node) +void dt_print_node(const struct device_tree_node *node) { print_node(node, 0); } @@ -481,7 +483,8 @@ * @param addrcp Pointer to store #address-cells in, skipped if NULL. * @param sizecp Pointer to store #size-cells in, skipped if NULL. */ -void dt_read_cell_props(struct device_tree_node *node, u32 *addrcp, u32 *sizecp) +void dt_read_cell_props(const struct device_tree_node *node, u32 *addrcp, + u32 *sizecp) { struct device_tree_property *prop; list_for_each(prop, node->properties, list_node) { @@ -706,7 +709,7 @@ list_for_each(prop, parent->properties, list_node) { if (!strcmp(name, prop->prop.name)) { size_t bytes = prop->prop.size; - void *prop_data = prop->prop.data; + const void *prop_data = prop->prop.data; if (size != bytes) break; if (!memcmp(data, prop_data, size)) @@ -731,16 +734,16 @@ * @param node Pointer to node containing the phandle * @return Zero on error, the phandle on success */ -uint32_t dt_get_phandle(struct device_tree_node *node) +uint32_t dt_get_phandle(const struct device_tree_node *node) { - uint32_t *phandle; + const uint32_t *phandle; size_t len; - dt_find_bin_prop(node, "phandle", (void **)&phandle, &len); + dt_find_bin_prop(node, "phandle", (const void **)&phandle, &len); if (phandle != NULL && len == sizeof(*phandle)) return be32_to_cpu(*phandle); - dt_find_bin_prop(node, "linux,phandle", (void **)&phandle, &len); + dt_find_bin_prop(node, "linux,phandle", (const void **)&phandle, &len); if (phandle != NULL && len == sizeof(*phandle)) return be32_to_cpu(*phandle); @@ -789,7 +792,7 @@ * @param size The size of data in bytes. */ void dt_add_bin_prop(struct device_tree_node *node, const char *name, - void *data, size_t size) + const void *data, size_t size) { struct device_tree_property *prop; @@ -817,9 +820,10 @@ * @param name The name of the property. * @return The found string, or NULL. */ -const char *dt_find_string_prop(struct device_tree_node *node, const char *name) +const char *dt_find_string_prop(const struct device_tree_node *node, + const char *name) { - void *content; + const void *content; size_t size; dt_find_bin_prop(node, name, &content, &size); @@ -835,8 +839,8 @@ * @param data Pointer to return raw data blob in the property. * @param size Pointer to return the size of data in bytes. */ -void dt_find_bin_prop(struct device_tree_node *node, const char *name, - void **data, size_t *size) +void dt_find_bin_prop(const struct device_tree_node *node, const char *name, + const void **data, size_t *size) { struct device_tree_property *prop; @@ -860,7 +864,7 @@ * @param str The zero-terminated string to be stored in the property. */ void dt_add_string_prop(struct device_tree_node *node, const char *name, - char *str) + const char *str) { dt_add_bin_prop(node, name, str, strlen(str) + 1); } diff --git a/src/lib/fit.c b/src/lib/fit.c index 68f5bed..da55072 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -158,7 +158,7 @@ return NULL; } -static int fdt_find_compat(void *blob, uint32_t start_offset, +static int fdt_find_compat(const void *blob, uint32_t start_offset, struct fdt_property *prop) { int offset = start_offset; @@ -196,7 +196,7 @@ return -1; } -void fit_update_chosen(struct device_tree *tree, char *cmd_line) +void fit_update_chosen(struct device_tree *tree, const char *cmd_line) { const char *path[] = { "chosen", NULL }; struct device_tree_node *node; @@ -388,10 +388,12 @@ * @param fdt_blob Pointer to FDT * @param config The current config node to operate on */ -static void fit_update_compat(void *fdt_blob, struct fit_config_node *config) +static void fit_update_compat(const void *fdt_blob, + struct fit_config_node *config) { struct compat_string_entry *compat_node; - struct fdt_header *fdt_header = (struct fdt_header *)fdt_blob; + const struct fdt_header *fdt_header = + (const struct fdt_header *)fdt_blob; uint32_t fdt_offset = be32_to_cpu(fdt_header->structure_offset); size_t i = 0; diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index ec947c0..3e1819d 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -119,7 +119,7 @@ struct device_tree_node *coreboot_node = dt_find_node(firmware_node, coreboot_path, &addr_cells, &size_cells, 1); - dt_add_string_prop(coreboot_node, "compatible", strdup("coreboot")); + dt_add_string_prop(coreboot_node, "compatible", "coreboot"); /* Fetch CB tables from cbmem */ void *cbtable = cbmem_find(CBMEM_ID_CBTABLE); diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 8efcb13..dfb06e0 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -64,9 +64,9 @@ static void dt_platform_fixup_phy(struct device_tree_node *node, char *path, int64_t phy_address, bdk_qlm_modes_t qlm_mode) { - char *data = NULL; + const char *data = NULL; size_t size = 0; - dt_find_bin_prop(node, "qlm-mode", (void **)&data, &size); + dt_find_bin_prop(node, "qlm-mode", (const void **)&data, &size); if (!data || strncmp(data, path, 6) != 0) return; /* No key prefix match. */ @@ -127,10 +127,10 @@ static void dt_platform_fixup_mac(struct device_tree_node *node) { const char *name = "local-mac-address"; - u64 *localmac = NULL; + const u64 *localmac = NULL; size_t size = 0; - dt_find_bin_prop(node, name, (void **)&localmac, &size); + dt_find_bin_prop(node, name, (const void **)&localmac, &size); if (!localmac) return; @@ -150,8 +150,8 @@ if (*localmac) return; if (used_mac < num_free_mac_addresses) { - *localmac = next_free_mac_address + used_mac; - dt_add_bin_prop(node, name, (void *)&localmac, 6); + const u64 genmac = next_free_mac_address + used_mac; + dt_add_bin_prop(node, name, &genmac, 6); used_mac++; return; } @@ -232,9 +232,10 @@ __func__); continue; } - u32 *data = NULL; + const u32 *data = NULL; size_t size = 0; - dt_find_bin_prop(dt_node, "mmu-masters", (void **)&data, &size); + dt_find_bin_prop(dt_node, "mmu-masters", (const void **)&data, + &size); if (!size) { printk(BIOS_ERR, "%s: mmu-masters entry not found\n", __func__); -- To view, visit https://review.coreboot.org/28267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Id27966427fb97457fe883be32685d1397fb0781f Gerrit-Change-Number: 28267 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: eve: Specify an unique ID for PS2 devices
by Lucas Chen (Code Review) 24 Aug '18

24 Aug '18

Hello Matt Delco, I'd like you to do a code review. Please visit https://review.coreboot.org/28334 to review the following change. Change subject: eve: Specify an unique ID for PS2 devices ...................................................................... eve: Specify an unique ID for PS2 devices Windows certification tests will fail if the PS2 devices are using Plug and Play ID (PNP0303). For all Chromebooks we should use GOOG000A. BRANCH=eve BUG=b:110066056 TEST=AltOS certification test verify. Change-Id: I479471fdb3102e3b492612a4e6ad07612273083a Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1098874 Reviewed-by: Matt Delco <delco(a)chromium.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Commit-Queue: Hung-Te Lin <hungte(a)chromium.org> Trybot-Ready: Hung-Te Lin <hungte(a)chromium.org> --- M src/ec/google/chromeec/acpi/superio.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/28334/1 diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index 8faabee..6c9cb2c 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -137,8 +137,8 @@ { Name (_UID, 0) Name (_ADR, 0) - Name (_HID, EISAID("PNP0303")) - Name (_CID, EISAID("PNP030B")) + Name (_HID, "GOOG000A") + Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } ) Method (_STA, 0, NotSerialized) { Return (0x0F) -- To view, visit https://review.coreboot.org/28334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I479471fdb3102e3b492612a4e6ad07612273083a Gerrit-Change-Number: 28334 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: acpi: Hide Chrome and Coreboot specific devices
by Lucas Chen (Code Review) 24 Aug '18

24 Aug '18

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/28333 Change subject: acpi: Hide Chrome and Coreboot specific devices ...................................................................... acpi: Hide Chrome and Coreboot specific devices Some ACPI interfaces introduced by Chrome or Coreboot do not need drivers outside ChromeOS, for example Chrome EC or Coreboot table. These interfaces should be set to hidden so non-ChromeOS systems, for example Windows, won't have problem finding driver. Interfaces changed: - Coreboot (BOOT0000), only used by Chrome OS / Linux kernel. - Chrome OS EC - Chrome OS EC PD - Chrome OS TBMC - Chrome OS RAMoops BUG=b:72200466 BRANCH=eve TEST=Boot into legacy mode and checked ACPI devices on UI. Change-Id: I9786cf9ee07b2c3f11509850604f2bfb3f3e710a Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1078211 Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Commit-Queue: Hung-Te Lin <hungte(a)chromium.org> Tested-by: Hung-Te Lin <hungte(a)chromium.org> Trybot-Ready: Hung-Te Lin <hungte(a)chromium.org> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpigen.h M src/ec/google/chromeec/acpi/cros_ec.asl M src/ec/google/chromeec/acpi/pd.asl M src/ec/google/chromeec/acpi/tbmc.asl M src/vendorcode/google/chromeos/acpi/ramoops.asl 6 files changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/28333/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 78eeaa7..8e16f94 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -324,7 +324,7 @@ acpigen_write_device("CTBL"); acpigen_write_coreboot_hid(COREBOOT_ACPI_ID_CBTABLE); acpigen_write_name_integer("_UID", 0); - acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpigen_write_mem32fixed(0, base, size); diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 775339a..a27bd6f 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -36,6 +36,9 @@ ACPI_STATUS_DEVICE_ENABLED |\ ACPI_STATUS_DEVICE_SHOW_IN_UI |\ ACPI_STATUS_DEVICE_STATE_OK) +#define ACPI_STATUS_DEVICE_HIDDEN_ON (ACPI_STATUS_DEVICE_PRESENT |\ + ACPI_STATUS_DEVICE_ENABLED |\ + ACPI_STATUS_DEVICE_STATE_OK) /* ACPI Op/Prefix Codes */ enum { diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index 1d7fb52..d0a5b68 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -39,4 +39,8 @@ Name (_DDN, "EC Base Switch Device") } #endif + Method(_STA, 0) + { + Return (0xB) + } } diff --git a/src/ec/google/chromeec/acpi/pd.asl b/src/ec/google/chromeec/acpi/pd.asl index a5a58f5..7b799e8 100644 --- a/src/ec/google/chromeec/acpi/pd.asl +++ b/src/ec/google/chromeec/acpi/pd.asl @@ -18,4 +18,8 @@ Name (_HID, "GOOG0003") Name (_UID, 1) Name (_DDN, "EC PD Device") + Method(_STA, 0) + { + Return (0xB) + } } diff --git a/src/ec/google/chromeec/acpi/tbmc.asl b/src/ec/google/chromeec/acpi/tbmc.asl index 25a27ef1b..86a6de8 100644 --- a/src/ec/google/chromeec/acpi/tbmc.asl +++ b/src/ec/google/chromeec/acpi/tbmc.asl @@ -26,4 +26,8 @@ Return (0x0) } } + Method(_STA, 0) + { + Return (0xB) + } } diff --git a/src/vendorcode/google/chromeos/acpi/ramoops.asl b/src/vendorcode/google/chromeos/acpi/ramoops.asl index 5a8ed86..810ff91 100644 --- a/src/vendorcode/google/chromeos/acpi/ramoops.asl +++ b/src/vendorcode/google/chromeos/acpi/ramoops.asl @@ -35,5 +35,9 @@ Store (\RMOL, RLEN) Return (^RBUF) } + Method(_STA, 0) + { + Return (0xB) + } } } -- To view, visit https://review.coreboot.org/28333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9786cf9ee07b2c3f11509850604f2bfb3f3e710a Gerrit-Change-Number: 28333 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: util/pmh7tool: Add tool to dump PMH7 registers
by build bot (Jenkins) (Code Review) 24 Aug '18

24 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27776 ) Change subject: util/pmh7tool: Add tool to dump PMH7 registers ...................................................................... Patch Set 9: (3 comments) https://review.coreboot.org/#/c/27776/9/util/pmh7tool/pmh7tool.c File util/pmh7tool/pmh7tool.c: https://review.coreboot.org/#/c/27776/9/util/pmh7tool/pmh7tool.c@151 PS9, Line 151: fprintf(stderr, "Error: <addr> cannot be greater than 9 bits long.\n"); line over 80 characters https://review.coreboot.org/#/c/27776/9/util/pmh7tool/pmh7tool.c@157 PS9, Line 157: fprintf(stderr, "Error: <bit> cannot be greater than 8.\n"); line over 80 characters https://review.coreboot.org/#/c/27776/9/util/pmh7tool/pmh7tool.c@162 PS9, Line 162: fprintf(stderr, "Error: <data> cannot be greater than 9 bits long.\n"); line over 80 characters -- To view, visit https://review.coreboot.org/27776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I05ccb5a9a861fe44efec794aafe1805062543d53 Gerrit-Change-Number: 27776 Gerrit-PatchSet: 9 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 24 Aug 2018 10:34:18 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/octopus: add Digitizer and Synaptics Touchpad for bobba
by Pan Sheng-Liang (Code Review) 24 Aug '18

24 Aug '18

Hello Sheng-Liang Pan, I'd like you to do a code review. Please visit https://review.coreboot.org/28332 to review the following change. Change subject: mb/google/octopus: add Digitizer and Synaptics Touchpad for bobba ...................................................................... mb/google/octopus: add Digitizer and Synaptics Touchpad for bobba add device "WCOM Digitizer" and "Synaptics Touchpad" for bobba BUG=none BRANCH=master TEST=emerge-octopus coreboot Change-Id: Ie0bf8ebab6d9cb9c8fe42a500efaa3d11ae359db Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/bobba/overridetree.cb 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/28332/1 diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 6726b41..acb1d50 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -1,6 +1,17 @@ chip soc/intel/apollolake device domain 0 on + device pci 16.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 0 device pci 17.1 on chip drivers/i2c/da7219 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" @@ -29,6 +40,15 @@ register "probed" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW2_02" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end end # - I2C 6 device pci 17.3 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/28332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie0bf8ebab6d9cb9c8fe42a500efaa3d11ae359db Gerrit-Change-Number: 28332 Gerrit-PatchSet: 1 Gerrit-Owner: Pan Sheng-Liang <sl.pan.quantw(a)gmail.com> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Remove superfluous header file
by Arthur Heymans (Code Review) 24 Aug '18

24 Aug '18

Hello build bot (Jenkins), Lijian Zhao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28331 to look at the new patch set (#2). Change subject: mb/intel/coffeelake_rvp: Remove superfluous header file ...................................................................... mb/intel/coffeelake_rvp: Remove superfluous header file TEST: same sha256sum with BUILD_TIMELESS=1. Change-Id: Icf3368bcf1351f0e7cd4041c3792d76362aec9e5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/coffeelake_rvp/bootblock.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/mainboard.c D src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/gpio.h D src/mainboard/intel/coffeelake_rvp/variants/cfl_u/include/variant/gpio.h 5 files changed, 0 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/28331/2 -- To view, visit https://review.coreboot.org/28331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icf3368bcf1351f0e7cd4041c3792d76362aec9e5 Gerrit-Change-Number: 28331 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Remove superfluous header file
by Arthur Heymans (Code Review) 24 Aug '18

24 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28331 Change subject: mb/intel/coffeelake_rvp: Remove superfluous header file ...................................................................... mb/intel/coffeelake_rvp: Remove superfluous header file TEST: same sha256sum with BUILD_TIMELESS=1. Change-Id: Icf3368bcf1351f0e7cd4041c3792d76362aec9e5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/coffeelake_rvp/bootblock.c M src/mainboard/intel/coffeelake_rvp/mainboard.c D src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/gpio.h D src/mainboard/intel/coffeelake_rvp/variants/cfl_u/include/variant/gpio.h 4 files changed, 0 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/28331/1 diff --git a/src/mainboard/intel/coffeelake_rvp/bootblock.c b/src/mainboard/intel/coffeelake_rvp/bootblock.c index 8655947..cac219e 100644 --- a/src/mainboard/intel/coffeelake_rvp/bootblock.c +++ b/src/mainboard/intel/coffeelake_rvp/bootblock.c @@ -16,7 +16,6 @@ #include <baseboard/variants.h> #include <bootblock_common.h> #include <soc/gpio.h> -#include <variant/gpio.h> void bootblock_mainboard_init(void) { diff --git a/src/mainboard/intel/coffeelake_rvp/mainboard.c b/src/mainboard/intel/coffeelake_rvp/mainboard.c index 522cfc4..aabb3ed 100644 --- a/src/mainboard/intel/coffeelake_rvp/mainboard.c +++ b/src/mainboard/intel/coffeelake_rvp/mainboard.c @@ -20,7 +20,6 @@ #include <soc/gpio.h> #include <soc/nhlt.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <variant/gpio.h> static void mainboard_init(void *chip_info) { diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/gpio.h deleted file mode 100644 index c34a9b3..0000000 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_GPIO_H__ -#define __MAINBOARD_GPIO_H__ - -#include <baseboard/gpio.h> - -#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/include/variant/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/include/variant/gpio.h deleted file mode 100644 index c34a9b3..0000000 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/include/variant/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_GPIO_H__ -#define __MAINBOARD_GPIO_H__ - -#include <baseboard/gpio.h> - -#endif /* __MAINBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/28331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icf3368bcf1351f0e7cd4041c3792d76362aec9e5 Gerrit-Change-Number: 28331 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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coreboot-gerrit August 2018