coreboot-gerrit August 2018

coreboot-gerrit@coreboot.org

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1120 discussions

Change in coreboot[master]: fsp/fsp2_0/coffeelake: Update CFL FSP headers
by Lijian Zhao (Code Review) 23 Aug '18

23 Aug '18

Hello Nathaniel L Desimone, build bot (Jenkins), Krzysztof M Sywula, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28286 to look at the new patch set (#3). Change subject: fsp/fsp2_0/coffeelake: Update CFL FSP headers ...................................................................... fsp/fsp2_0/coffeelake: Update CFL FSP headers Coffeelake FSP headers had been updated to version 7.0.3D.60. Original file location from https://github.com/IntelFsp/FSP/tree/master/ CoffeeLakeFspBinPkg/Include . BUG=N/A TEST=Build and flash, able to boot up into OS on whiskeylake rvp platform. Change-Id: I656da83e9042642576b785643e423ba47da8dd73 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h 2 files changed, 3,351 insertions(+), 3,241 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/28286/3 -- To view, visit https://review.coreboot.org/28286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I656da83e9042642576b785643e423ba47da8dd73 Gerrit-Change-Number: 28286 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/kahlee: Fix I2C bus 0 timing for Grunt
by Martin Roth (Code Review) 23 Aug '18

23 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28280 ) Change subject: mb/google/kahlee: Fix I2C bus 0 timing for Grunt ...................................................................... Patch Set 1: Code-Review+2 What speed is the bus running at after this change? -- To view, visit https://review.coreboot.org/28280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I34a4f62815d192005c3324d4f71b0aba377fe738 Gerrit-Change-Number: 28280 Gerrit-PatchSet: 1 Gerrit-Owner: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-Reviewer: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: David Wells <dawells(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 23 Aug 2018 16:45:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: vendorcode/amd/cimx/sb*: Rename RSDP header
by Marc Jones (Code Review) 23 Aug '18

23 Aug '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/28294 Change subject: vendorcode/amd/cimx/sb*: Rename RSDP header ...................................................................... vendorcode/amd/cimx/sb*: Rename RSDP header Rename RSDP to RSDP_HEADER to match other AMD vendorcode and to not pollute the namespace. We will use RSDP in a future patch. Change-Id: I3b66135ae1732b86b5ebfcdc01a850a0d9d3eb50 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/vendorcode/amd/cimx/sb800/ACPILIB.c M src/vendorcode/amd/cimx/sb800/ACPILIB.h M src/vendorcode/amd/cimx/sb900/AcpiLib.c M src/vendorcode/amd/cimx/sb900/AcpiLib.h 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/28294/1 diff --git a/src/vendorcode/amd/cimx/sb800/ACPILIB.c b/src/vendorcode/amd/cimx/sb800/ACPILIB.c index bc11209..e112fe8 100644 --- a/src/vendorcode/amd/cimx/sb800/ACPILIB.c +++ b/src/vendorcode/amd/cimx/sb800/ACPILIB.c @@ -63,7 +63,7 @@ Rsdt = NULL; do { if ( *RsdPtr == Int32FromChar('R', 'S', 'D', ' ') && *(RsdPtr + 1) == Int32FromChar('P', 'T', 'R', ' ')) { - Rsdt = (UINT32*) (UINTN) ((RSDP*)RsdPtr)->RsdtAddress; + Rsdt = (UINT32*) (UINTN) ((RSDP_HEADER*)RsdPtr)->RsdtAddress; break; } RsdPtr += 4; diff --git a/src/vendorcode/amd/cimx/sb800/ACPILIB.h b/src/vendorcode/amd/cimx/sb800/ACPILIB.h index 73571f4..442043a 100644 --- a/src/vendorcode/amd/cimx/sb800/ACPILIB.h +++ b/src/vendorcode/amd/cimx/sb800/ACPILIB.h @@ -44,7 +44,7 @@ unsigned long long XsdtAddress; /* physical address of XSDT */ unsigned char ExtendedChecksum; /* chechsum of whole table */ unsigned char Reserved[3]; -} RSDP; +} RSDP_HEADER; /** diff --git a/src/vendorcode/amd/cimx/sb900/AcpiLib.c b/src/vendorcode/amd/cimx/sb900/AcpiLib.c index 2b8a389..845b34d 100644 --- a/src/vendorcode/amd/cimx/sb900/AcpiLib.c +++ b/src/vendorcode/amd/cimx/sb900/AcpiLib.c @@ -61,7 +61,7 @@ // if ( *RsdPtr == ' DSR' && *(RsdPtr + 1) == ' RTP' ) { // if ( (*RsdPtr == 0x52534420) && (*(RsdPtr + 1) == 0x50545220) ) { if ( (*RsdPtr == 0x20445352) && (*(RsdPtr + 1) == 0x20525450) ) { - Rsdt = (UINT32*) (UINTN) ((RSDP*)RsdPtr)->RsdtAddress; + Rsdt = (UINT32*) (UINTN) ((RSDP_HEADER*)RsdPtr)->RsdtAddress; break; } RsdPtr += 4; diff --git a/src/vendorcode/amd/cimx/sb900/AcpiLib.h b/src/vendorcode/amd/cimx/sb900/AcpiLib.h index 63913c2..c604023 100644 --- a/src/vendorcode/amd/cimx/sb900/AcpiLib.h +++ b/src/vendorcode/amd/cimx/sb900/AcpiLib.h @@ -40,7 +40,7 @@ unsigned long long XsdtAddress; ///< physical address of XSDT unsigned char ExtendedChecksum; ///< chechsum of whole table unsigned char Reserved[3]; ///< Reserved -} RSDP; +} RSDP_HEADER; /// DESCRIPTION_HEADER - ACPI common table header -- To view, visit https://review.coreboot.org/28294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3b66135ae1732b86b5ebfcdc01a850a0d9d3eb50 Gerrit-Change-Number: 28294 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: util/nvramtool: Fix typos
by Elyes HAOUAS (Code Review) 23 Aug '18

23 Aug '18

Elyes HAOUAS has uploaded a new patch set (#2). ( https://review.coreboot.org/28290 ) Change subject: util/nvramtool: Fix typos ...................................................................... util/nvramtool: Fix typos Change-Id: I0a704cba80d0439ae95db34a6b73df7be5b3b862 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/nvramtool/coreboot_tables.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/28290/2 -- To view, visit https://review.coreboot.org/28290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0a704cba80d0439ae95db34a6b73df7be5b3b862 Gerrit-Change-Number: 28290 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: util/msrtool: Fix typos
by Elyes HAOUAS (Code Review) 23 Aug '18

23 Aug '18

Elyes HAOUAS has uploaded a new patch set (#2). ( https://review.coreboot.org/28289 ) Change subject: util/msrtool: Fix typos ...................................................................... util/msrtool: Fix typos Change-Id: I36ed2c33f9bed3e640871283c2cb163d6800d1d5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/msrtool/intel_atom.c M util/msrtool/intel_core2_later.c M util/msrtool/intel_nehalem.c 3 files changed, 22 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/28289/2 -- To view, visit https://review.coreboot.org/28289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I36ed2c33f9bed3e640871283c2cb163d6800d1d5 Gerrit-Change-Number: 28289 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/kconfig: Fix typos
by Elyes HAOUAS (Code Review) 23 Aug '18

23 Aug '18

Elyes HAOUAS has uploaded a new patch set (#2). ( https://review.coreboot.org/28288 ) Change subject: util/kconfig: Fix typos ...................................................................... util/kconfig: Fix typos Change-Id: I02063c1d4e76f0c55937da7a309c0f668bc0e064 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/kconfig/conf.c M util/kconfig/confdata.c M util/kconfig/gconf.c M util/kconfig/kxgettext.c M util/kconfig/lkc_proto.h M util/kconfig/mconf.c M util/kconfig/nconf.c M util/kconfig/qconf.cc M util/kconfig/symbol.c 9 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/28288/2 -- To view, visit https://review.coreboot.org/28288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I02063c1d4e76f0c55937da7a309c0f668bc0e064 Gerrit-Change-Number: 28288 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: util/{ifdtool, ipqheader}: Fix typos
by Elyes HAOUAS (Code Review) 23 Aug '18

23 Aug '18

Elyes HAOUAS has uploaded a new patch set (#2). ( https://review.coreboot.org/28287 ) Change subject: util/{ifdtool,ipqheader}: Fix typos ...................................................................... util/{ifdtool,ipqheader}: Fix typos Change-Id: I53ddff302681737006f40ca8b79ec0735f1e6e45 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/ifdtool/ifdtool.c M util/ipqheader/mbn_tools.py 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/28287/2 -- To view, visit https://review.coreboot.org/28287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I53ddff302681737006f40ca8b79ec0735f1e6e45 Gerrit-Change-Number: 28287 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: util/romcc: Fix typos
by build bot (Jenkins) (Code Review) 23 Aug '18

23 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28293 ) Change subject: util/romcc: Fix typos ...................................................................... Patch Set 1: (22 comments) https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c File util/romcc/romcc.c: https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@1770 PS1, Line 1770: for(spot = triple->occurrence; spot; spot = spot->parent) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@1952 PS1, Line 1952: if (occurrence->parent) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@2403 PS1, Line 2403: piece = alloc_triple(state, OP_PIECE, piece_type, -1, -1, ins->occurrence); line over 80 characters https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@2522 PS1, Line 2522: for(ptr = ins->occurrence; ptr; ptr = ptr->parent) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@2605 PS1, Line 2605: for(ptr = orig->occurrence; ptr; ptr = ptr->parent) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@13722 PS1, Line 13722: occurrence = inline_occurrence(state, base_occurrence, old->occurrence); line over 80 characters https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@15918 PS1, Line 15918: while(ins != block->last && (ins->occurrence->line == 0)) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@15918 PS1, Line 15918: while(ins != block->last && (ins->occurrence->line == 0)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@16628 PS1, Line 16628: phi->type, 0, 0, phi->occurrence)); line over 80 characters https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@20782 PS1, Line 20782: #warning "FIXME constant propagate through expressions with multiple left hand sides" line over 80 characters https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@21479 PS1, Line 21479: if ( (dummy_occurrence.count != 2) || space prohibited after that open parenthesis '(' https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@21484 PS1, Line 21484: internal_error(state, &unknown_triple, "dummy_occurrence corrupted!"); line over 80 characters https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@24821 PS1, Line 24821: ins->occurrence->function?ins->occurrence->function:"(null)", line over 80 characters https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@24822 PS1, Line 24822: ins->occurrence->filename?ins->occurrence->filename:"(null)", line over 80 characters https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@24831 PS1, Line 24831: for(ptr = ins->occurrence; ptr; ptr = ptr->parent) { line over 80 characters https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@24831 PS1, Line 24831: for(ptr = ins->occurrence; ptr; ptr = ptr->parent) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28293/1/util/romcc/romcc.c@24844 PS1, Line 24844: if (last_occurrence) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/28293/1/util/romcc/tests/linux_test2.c File util/romcc/tests/linux_test2.c: https://review.coreboot.org/#/c/28293/1/util/romcc/tests/linux_test2.c@487 PS1, Line 487: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/28293/1/util/romcc/tests/raminit_test.c File util/romcc/tests/raminit_test.c: https://review.coreboot.org/#/c/28293/1/util/romcc/tests/raminit_test.c@757 PS1, Line 757: * DRAMC register, which records if ram is registered or not, line over 80 characters https://review.coreboot.org/#/c/28293/1/util/romcc/tests/raminit_test1.c File util/romcc/tests/raminit_test1.c: https://review.coreboot.org/#/c/28293/1/util/romcc/tests/raminit_test1.c@757 PS1, Line 757: * DRAMC register, which records if ram is registered or not, line over 80 characters https://review.coreboot.org/#/c/28293/1/util/romcc/tests/raminit_test2.c File util/romcc/tests/raminit_test2.c: https://review.coreboot.org/#/c/28293/1/util/romcc/tests/raminit_test2.c@757 PS1, Line 757: * DRAMC register, which records if ram is registered or not, line over 80 characters https://review.coreboot.org/#/c/28293/1/util/romcc/tests/simple_test30.c File util/romcc/tests/simple_test30.c: https://review.coreboot.org/#/c/28293/1/util/romcc/tests/simple_test30.c@901 PS1, Line 901: * This field defines the upp address bits of a 40-bit address that line over 80 characters -- To view, visit https://review.coreboot.org/28293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia9f0f1f527476900e6c54c60508600e16bea786f Gerrit-Change-Number: 28293 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 23 Aug 2018 16:27:29 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: util/msrtool: Fix typo
by build bot (Jenkins) (Code Review) 23 Aug '18

23 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28289 ) Change subject: util/msrtool: Fix typo ...................................................................... Patch Set 1: (19 comments) https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_atom.c File util/msrtool/intel_atom.c: https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_atom.c@800 PS1, Line 800: conditions occurring in the logical processor which programmed the MSR" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_atom.c@802 PS1, Line 802: occurring across all logical processors sharing a processor core" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_atom.c@823 PS1, Line 823: conditions occurring in the logical processor which programmed the MSR" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_atom.c@825 PS1, Line 825: occurring across all logical processors sharing a processor core" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_atom.c@846 PS1, Line 846: conditions occurring in the logical processor which programmed the MSR" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_atom.c@848 PS1, Line 848: occurring across all logical processors sharing a processor core" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_core2_later.c File util/msrtool/intel_core2_later.c: https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_core2_later.c@824 PS1, Line 824: conditions occurring in the logical processor which programmed the MSR" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_core2_later.c@826 PS1, Line 826: occurring across all logical processors sharing a processor core" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_core2_later.c@847 PS1, Line 847: conditions occurring in the logical processor which programmed the MSR" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_core2_later.c@849 PS1, Line 849: occurring across all logical processors sharing a processor core" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_core2_later.c@870 PS1, Line 870: conditions occurring in the logical processor which programmed the MSR" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_core2_later.c@872 PS1, Line 872: occurring across all logical processors sharing a processor core" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c File util/msrtool/intel_nehalem.c: https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c@1112 PS1, Line 1112: { MSR1(1), "CPU switch to the Minimum Enhanced Intel \ Avoid line continuations in quoted strings https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c@1376 PS1, Line 1376: conditions occurring in the logical processor which programmed the MSR" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c@1378 PS1, Line 1378: occurring across all logical processors sharing a processor core" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c@1399 PS1, Line 1399: conditions occurring in the logical processor which programmed the MSR" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c@1401 PS1, Line 1401: occurring across all logical processors sharing a processor core" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c@1422 PS1, Line 1422: conditions occurring in the logical processor which programmed the MSR" }, line over 80 characters https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c@1424 PS1, Line 1424: occurring across all logical processors sharing a processor core" }, line over 80 characters -- To view, visit https://review.coreboot.org/28289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I36ed2c33f9bed3e640871283c2cb163d6800d1d5 Gerrit-Change-Number: 28289 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 23 Aug 2018 16:26:55 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: util/cbfstool: Fix typos
by build bot (Jenkins) (Code Review) 23 Aug '18

23 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28208 ) Change subject: util/cbfstool: Fix typos ...................................................................... Patch Set 3: (34 comments) https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c File util/cbfstool/lz4/lib/xxhash.c: https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@68 PS3, Line 68: * By default, xxHash library provides endian-independent Hash values, based on little-endian convention. line over 80 characters https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@222 PS3, Line 222: typedef enum { XXH_bigEndian=0, XXH_littleEndian=1 } XXH_endianness; spaces required around that '=' (ctx:VxV) https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@222 PS3, Line 222: typedef enum { XXH_bigEndian=0, XXH_littleEndian=1 } XXH_endianness; spaces required around that '=' (ctx:VxV) https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@236 PS3, Line 236: FORCE_INLINE U32 XXH_readLE32_align(const void* ptr, XXH_endianness endian, XXH_alignment align) line over 80 characters https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@236 PS3, Line 236: FORCE_INLINE U32 XXH_readLE32_align(const void* ptr, XXH_endianness endian, XXH_alignment align) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@244 PS3, Line 244: FORCE_INLINE U32 XXH_readLE32(const void* ptr, XXH_endianness endian) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@249 PS3, Line 249: FORCE_INLINE U64 XXH_readLE64_align(const void* ptr, XXH_endianness endian, XXH_alignment align) line over 80 characters https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@249 PS3, Line 249: FORCE_INLINE U64 XXH_readLE64_align(const void* ptr, XXH_endianness endian, XXH_alignment align) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@257 PS3, Line 257: FORCE_INLINE U64 XXH_readLE64(const void* ptr, XXH_endianness endian) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@288 PS3, Line 288: FORCE_INLINE U32 XXH32_endian_align(const void* input, size_t len, U32 seed, XXH_endianness endian, XXH_alignment align) line over 80 characters https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@288 PS3, Line 288: FORCE_INLINE U32 XXH32_endian_align(const void* input, size_t len, U32 seed, XXH_endianness endian, XXH_alignment align) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@374 PS3, Line 374: XXH_endianness endian_detected = (XXH_endianness)XXH_CPU_LITTLE_ENDIAN; please, no spaces at the start of a line https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@393 PS3, Line 393: FORCE_INLINE U64 XXH64_endian_align(const void* input, size_t len, U64 seed, XXH_endianness endian, XXH_alignment align) line over 80 characters https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@393 PS3, Line 393: FORCE_INLINE U64 XXH64_endian_align(const void* input, size_t len, U64 seed, XXH_endianness endian, XXH_alignment align) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@514 PS3, Line 514: XXH_endianness endian_detected = (XXH_endianness)XXH_CPU_LITTLE_ENDIAN; please, no spaces at the start of a line https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@615 PS3, Line 615: FORCE_INLINE XXH_errorcode XXH32_update_endian (XXH32_state_t* state_in, const void* input, size_t len, XXH_endianness endian) line over 80 characters https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@615 PS3, Line 615: FORCE_INLINE XXH_errorcode XXH32_update_endian (XXH32_state_t* state_in, const void* input, size_t len, XXH_endianness endian) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@615 PS3, Line 615: FORCE_INLINE XXH_errorcode XXH32_update_endian (XXH32_state_t* state_in, const void* input, size_t len, XXH_endianness endian) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@615 PS3, Line 615: FORCE_INLINE XXH_errorcode XXH32_update_endian (XXH32_state_t* state_in, const void* input, size_t len, XXH_endianness endian) space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@706 PS3, Line 706: XXH_endianness endian_detected = (XXH_endianness)XXH_CPU_LITTLE_ENDIAN; please, no spaces at the start of a line https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@716 PS3, Line 716: FORCE_INLINE U32 XXH32_digest_endian (const XXH32_state_t* state_in, XXH_endianness endian) line over 80 characters https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@716 PS3, Line 716: FORCE_INLINE U32 XXH32_digest_endian (const XXH32_state_t* state_in, XXH_endianness endian) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@716 PS3, Line 716: FORCE_INLINE U32 XXH32_digest_endian (const XXH32_state_t* state_in, XXH_endianness endian) space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@760 PS3, Line 760: XXH_endianness endian_detected = (XXH_endianness)XXH_CPU_LITTLE_ENDIAN; please, no spaces at the start of a line https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@769 PS3, Line 769: FORCE_INLINE XXH_errorcode XXH64_update_endian (XXH64_state_t* state_in, const void* input, size_t len, XXH_endianness endian) line over 80 characters https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@769 PS3, Line 769: FORCE_INLINE XXH_errorcode XXH64_update_endian (XXH64_state_t* state_in, const void* input, size_t len, XXH_endianness endian) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@769 PS3, Line 769: FORCE_INLINE XXH_errorcode XXH64_update_endian (XXH64_state_t* state_in, const void* input, size_t len, XXH_endianness endian) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@769 PS3, Line 769: FORCE_INLINE XXH_errorcode XXH64_update_endian (XXH64_state_t* state_in, const void* input, size_t len, XXH_endianness endian) space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@860 PS3, Line 860: XXH_endianness endian_detected = (XXH_endianness)XXH_CPU_LITTLE_ENDIAN; please, no spaces at the start of a line https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@870 PS3, Line 870: FORCE_INLINE U64 XXH64_digest_endian (const XXH64_state_t* state_in, XXH_endianness endian) line over 80 characters https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@870 PS3, Line 870: FORCE_INLINE U64 XXH64_digest_endian (const XXH64_state_t* state_in, XXH_endianness endian) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@870 PS3, Line 870: FORCE_INLINE U64 XXH64_digest_endian (const XXH64_state_t* state_in, XXH_endianness endian) space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/28208/3/util/cbfstool/lz4/lib/xxhash.c@954 PS3, Line 954: XXH_endianness endian_detected = (XXH_endianness)XXH_CPU_LITTLE_ENDIAN; please, no spaces at the start of a line https://review.coreboot.org/#/c/28208/3/util/cbfstool/lzma/C/LzmaEnc.h File util/cbfstool/lzma/C/LzmaEnc.h: https://review.coreboot.org/#/c/28208/3/util/cbfstool/lzma/C/LzmaEnc.h@40 PS3, Line 40: SZ_ERROR_PARAM - Incorrect parameter in props please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/28208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6967a106ce1286d633ddeeb041f582e65f9ea78c Gerrit-Change-Number: 28208 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 23 Aug 2018 16:26:30 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit August 2018