coreboot-gerrit August 2018

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Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
by Richard Spiegel (Code Review) 25 Aug '18

25 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28343 Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() ...................................................................... soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL, which was deprecated in favor of a public PCI register (though only the bits to enable debug port became public) 0x90. Therefor code needs to be updated. BUG=b:69231009 TEST=Build and boot grunt. Change-Id: I0aa49d567d24c10a2273c5e748cd0c89e83dfd70 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/28343/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index acbd6ec..f054b3b 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -308,7 +308,7 @@ #define EHCI_HUB_CONFIG4 0x90 #define DEBUG_PORT_SELECT_SHIFT 16 #define DEBUG_PORT_ENABLE BIT(18) -#define DEBUG_PORT_MASK ((BIT(16) | BIT(17) | (BIT(18))) +#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18)) #define WIDEIO_RANGE_ERROR -1 #define TOTAL_WIDEIO_PORTS 3 -- To view, visit https://review.coreboot.org/28343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0aa49d567d24c10a2273c5e748cd0c89e83dfd70 Gerrit-Change-Number: 28343 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
by Richard Spiegel (Code Review) 25 Aug '18

25 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28342 Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() ...................................................................... soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL, which was deprecated in favor of a public PCI register (though only the bits to enable debug port became public) 0x90. Therefor code needs to be updated. BUG=b:69231009 TEST=Build and boot grunt. Change-Id: I5938ada96999774bd998998d47686427ec34d4d1 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/28342/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 5f1faea..acbd6ec 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -308,7 +308,7 @@ #define EHCI_HUB_CONFIG4 0x90 #define DEBUG_PORT_SELECT_SHIFT 16 #define DEBUG_PORT_ENABLE BIT(18) -#define DEBUG_PORT_MASK ( BIT(16) | BIT(17) | (BIT(18) ) +#define DEBUG_PORT_MASK ((BIT(16) | BIT(17) | (BIT(18))) #define WIDEIO_RANGE_ERROR -1 #define TOTAL_WIDEIO_PORTS 3 -- To view, visit https://review.coreboot.org/28342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5938ada96999774bd998998d47686427ec34d4d1 Gerrit-Change-Number: 28342 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
by Richard Spiegel (Code Review) 25 Aug '18

25 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28341 Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() ...................................................................... soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL, which was deprecated in favor of a public PCI register (though only the bits to enable debug port became public) 0x90. Therefor code needs to be updated. BUG=b:69231009 TEST=Build and boot grunt. Change-Id: I47b0e4450f96399fc3066d0a974e7a9324d82f90 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/28341/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index f054b3b..5f1faea 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -308,7 +308,7 @@ #define EHCI_HUB_CONFIG4 0x90 #define DEBUG_PORT_SELECT_SHIFT 16 #define DEBUG_PORT_ENABLE BIT(18) -#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18)) +#define DEBUG_PORT_MASK ( BIT(16) | BIT(17) | (BIT(18) ) #define WIDEIO_RANGE_ERROR -1 #define TOTAL_WIDEIO_PORTS 3 -- To view, visit https://review.coreboot.org/28341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I47b0e4450f96399fc3066d0a974e7a9324d82f90 Gerrit-Change-Number: 28341 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
by Richard Spiegel (Code Review) 25 Aug '18

25 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28340 Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() ...................................................................... soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL, which was deprecated in favor of a public PCI register (though only the bits to enable debug port became public) 0x90. Therefor code needs to be updated. BUG=b:69231009 TEST=Build and boot grunt. Change-Id: Ic10c43cb6e5a9e8fe3bccf79a8ed69a6a0b49fce Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/enable_usbdebug.c M src/soc/amd/stoneyridge/include/soc/southbridge.h 2 files changed, 20 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/28340/1 diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index efe34e5..a2b5dd5 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -22,8 +22,6 @@ #include <device/pci_def.h> #include <soc/southbridge.h> -#define DEBUGPORT_MISC_CONTROL 0x80 - pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { /* Enable all of the USB controllers */ @@ -38,15 +36,22 @@ return PCI_DEV(0, 0x12, 0); } +/* + * Stoneyridge selects port 1 as the debug port by default, and coreboot + * function usbdebug_init_() also selects port 1 if USBDEBUG_DEFAULT_PORT + * is not selected or set to 0. So if port 1 is used, no change is needed. + * For ports 2 and 3, value of USBDEBUG_DEFAULT_PORT is the port itself, + * but to work around usbdebug_init_(), if port 0 is desired set + * USBDEBUG_DEFAULT_PORT to 4. + */ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { - u8 *base_regs = pci_ehci_base_regs(dev); - u32 reg32; + u32 reg32, value; - /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ - reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL); - reg32 &= ~(0xf << 28); - reg32 |= (port << 28); - reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ - write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); + value = (port & 0x00000003) << DEBUG_PORT_SELECT_SHIFT; + value |= DEBUG_PORT_ENABLE; + reg32 = pci_read_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4); + reg32 &= ~DEBUG_PORT_MASK; + reg32 |= value; + pci_write_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4, reg32); } diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 530b93a..f054b3b 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -305,6 +305,11 @@ #define OC_PORT2_SHIFT 8 #define OC_PORT3_SHIFT 12 +#define EHCI_HUB_CONFIG4 0x90 +#define DEBUG_PORT_SELECT_SHIFT 16 +#define DEBUG_PORT_ENABLE BIT(18) +#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18)) + #define WIDEIO_RANGE_ERROR -1 #define TOTAL_WIDEIO_PORTS 3 -- To view, visit https://review.coreboot.org/28340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic10c43cb6e5a9e8fe3bccf79a8ed69a6a0b49fce Gerrit-Change-Number: 28340 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: util: Add script to download FSP headers
by Krzysztof M Sywula (Code Review) 25 Aug '18

25 Aug '18

Krzysztof M Sywula has posted comments on this change. ( https://review.coreboot.org/28339 ) Change subject: util: Add script to download FSP headers ...................................................................... Patch Set 1: Patrick, please review first revision of the script. I saw your comment asking for such utility. Take a note that currently script doesn't support some families: 1. coreboot.org denverton_ns doesn't match github DenvertonNSFspBinPkg 2. coreboot.org skykabylake doesn't match github KabylakeFspBinPkg 3. coreboot.org glk doesn't exist on github 4. coreboot.org quark doesn't exist on github (1) and (2) I would recommend renaming to denvertonns and kabylake accordingly as currently they don't follow naming convention. -- To view, visit https://review.coreboot.org/28339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2cda87a4cbfa7ce102b10b555f83cdf163c80e5f Gerrit-Change-Number: 28339 Gerrit-PatchSet: 1 Gerrit-Owner: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Aug 2018 23:34:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: util: Add script to download FSP headers
by Krzysztof M Sywula (Code Review) 25 Aug '18

25 Aug '18

Krzysztof M Sywula has uploaded this change for review. ( https://review.coreboot.org/28339 Change subject: util: Add script to download FSP headers ...................................................................... util: Add script to download FSP headers This is small script that updates existing FSP header files with ones downloaded from github. To run do: ./update-fsp-headers.sh CoffeeLake Change-Id: I2cda87a4cbfa7ce102b10b555f83cdf163c80e5f Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula(a)intel.com> --- A util/update-fsp-headers/update-fsp-headers.sh 1 file changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/28339/1 diff --git a/util/update-fsp-headers/update-fsp-headers.sh b/util/update-fsp-headers/update-fsp-headers.sh new file mode 100755 index 0000000..f54d3dc --- /dev/null +++ b/util/update-fsp-headers/update-fsp-headers.sh @@ -0,0 +1,27 @@ +#!/bin/sh +set -e + +type curl +type dos2unix + +if [ "$#" -ne 1 ]; then + printf "Usage: ./$0 <CPU family>\n" + printf "Available params: ApolloLake CannonLake CoffeeLake\n" + exit 1 +fi + +FAMILY="${1}" +ME="$(dirname "$(readlink -f "$0")")" +DEST="${ME}"/../src/vendorcode/intel/fsp/fsp2_0/$(echo $1 | tr '[A-Z]' '[a-z]') + +if ! [ -d "${DEST}" ]; then + printf "Destination path does not exist: ${DEST}"; exit 1 +fi + +do_work() { + wget -O "${DEST}"/"${1}" https://raw.githubusercontent.com/IntelFsp/FSP/master/"${FAMILY}"FspBinPkg/Include/"${1}" + dos2unix "${DEST}"/"${1}" +} + +do_work "FspmUpd.h" +do_work "FspsUpd.h" -- To view, visit https://review.coreboot.org/28339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2cda87a4cbfa7ce102b10b555f83cdf163c80e5f Gerrit-Change-Number: 28339 Gerrit-PatchSet: 1 Gerrit-Owner: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com>

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Change in coreboot[master]: mb/google/octopus: add Digitizer and Synaptics Touchpad for bobba
by Furquan Shaikh (Code Review) 24 Aug '18

24 Aug '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28332 ) Change subject: mb/google/octopus: add Digitizer and Synaptics Touchpad for bobba ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie0bf8ebab6d9cb9c8fe42a500efaa3d11ae359db Gerrit-Change-Number: 28332 Gerrit-PatchSet: 1 Gerrit-Owner: Pan Sheng-Liang <sl.pan.quantw(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Aug 2018 17:48:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Remove superfluous header file
by Lijian Zhao (Code Review) 24 Aug '18

24 Aug '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/28331 ) Change subject: mb/intel/coffeelake_rvp: Remove superfluous header file ...................................................................... Patch Set 2: Code-Review+2 Okay, then I can move all the GPIO programming in gpio.c under baseboard. -- To view, visit https://review.coreboot.org/28331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icf3368bcf1351f0e7cd4041c3792d76362aec9e5 Gerrit-Change-Number: 28331 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Aug 2018 16:37:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/common: Don't clear GPE status register
by Subrata Banik (Code Review) 24 Aug '18

24 Aug '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28337 Change subject: soc/intel/common: Don't clear GPE status register ...................................................................... soc/intel/common: Don't clear GPE status register As per EDS definition for GPE Status register is RW/1C/V, hence writting mask bit into GPE status will force clear GPE status bit. This will lead into device side "IRQ timeout" problem as soc code might relying on GPE status read to know the interrupt status. TEST=Don't see IRQ timeout issue for TPM. Change-Id: I27fabb3612251fd8d04f58c05ff9fb2a42ad64b3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/pmc/pmclib.c 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/28337/1 diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 339e674..7f106f4 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -460,7 +460,7 @@ return acpi_sleep_from_pm1(pmc_read_pm1_control()) == ACPI_S3; } -/* Read and clear GPE status (defined in arch/acpi.h) */ +/* Read GPE status (defined in arch/acpi.h) */ int acpi_get_gpe(int gpe) { int bank; @@ -474,17 +474,15 @@ bank = gpe / 32; mask = 1 << (gpe % 32); - /* Wait up to 1ms for GPE status to clear */ + /* Wait up to 1ms for GPE status to trigger */ stopwatch_init_msecs_expire(&sw, 1); do { if (stopwatch_expired(&sw)) return rc; sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank)); - if (sts & mask) { - outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank)); + if (sts & mask) rc = 1; - } } while (sts & mask); return rc; -- To view, visit https://review.coreboot.org/28337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I27fabb3612251fd8d04f58c05ff9fb2a42ad64b3 Gerrit-Change-Number: 28337 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/cavium: Add dynamic dtb support
by Patrick Rudolph (Code Review) 24 Aug '18

24 Aug '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28336 ) Change subject: soc/cavium: Add dynamic dtb support ...................................................................... Patch Set 2: (4 comments) also set the default devicetree in payloads linux and linuxboot to $(obj)/fit.dtb if FIT_DEVICETREE_NAME != "" ? https://review.coreboot.org/#/c/28336/2/Makefile.inc File Makefile.inc: https://review.coreboot.org/#/c/28336/2/Makefile.inc@574 PS2, Line 574: FIT_DEVICETREE_FILE := $(src)/mainboard/$(MAINBOARDDIR)/$(FIT_DEVICETREE_NAME) $(src)/mainboard/$(MAINBOARDDIR)/$(VARIANT_DIR)/$(FIT_DEVICETREE_NAME) https://review.coreboot.org/#/c/28336/2/Makefile.inc@582 PS2, Line 582: dtc -I dts -O dtb -o $@ -i $(src)/mainboard/$(MAINBOARDDIR) -i $(src)/mainboard/$(VARIANT_DIR) $< $(src)/mainboard/$(MAINBOARDDIR)/$(VARIANT_DIR)/ https://review.coreboot.org/#/c/28336/2/Makefile.inc@584 PS2, Line 584: cbfs-files-y += $(FIT_DEVICETREE_NAME) has nothing to do with FIT. Should be placed in soc/cavium/cn81xx and marked deprecated https://review.coreboot.org/#/c/28336/2/src/mainboard/Kconfig File src/mainboard/Kconfig: https://review.coreboot.org/#/c/28336/2/src/mainboard/Kconfig@186 PS2, Line 186: default "" Overwrite the default in src/mainboard/cavium/cn81xx_sff_evb -- To view, visit https://review.coreboot.org/28336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie470092e424b86e04141b8e2bd2b080a5aadcf58 Gerrit-Change-Number: 28336 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 24 Aug 2018 15:20:52 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit August 2018