coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/stoneridge: Add DRAM check for s3
by Marshall Dawson (Code Review) 13 Nov '18

13 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29406 to look at the new patch set (#3). Change subject: soc/amd/stoneridge: Add DRAM check for s3 ...................................................................... soc/amd/stoneridge: Add DRAM check for s3 Allocate cbmem space to store DRAM check data during S3. Verify the the data is unchanged during the resume. Due to where the save and verify steps are placed, the test cannot capture 100% of potential memory corruption causes in coreboot. The ranges to verify are determined by the coreboot tables that are constructed at the end of POST. If a failure occurs within RAM available to the OS, the test reports "ERROR" to force suspend_stress_test to stop. Otherwise, the mismatch is reported as "FYI", e.g. in memory owned by coreboot. CAUTION: This test must not be deployed in a shipping system. It disables TSEG, and its protections, in order to allow the performance to be at an acceptable level. TODO: Add the capability of checking DRAM above 4GB. TEST=Suspend/resume grunt. Verify mismatch with induced error. BUG=b:118157730 Change-Id: I375dd7ea9a3ab8992f1616126bcbd9724e4fc9a0 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/pi/amd_resume_final.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/finalize.c M src/soc/amd/stoneyridge/include/soc/iomap.h A src/soc/amd/stoneyridge/include/soc/s3test_util.h A src/soc/amd/stoneyridge/s3test_util.c M src/soc/amd/stoneyridge/smihandler.c 8 files changed, 433 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/29406/3 -- To view, visit https://review.coreboot.org/29406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I375dd7ea9a3ab8992f1616126bcbd9724e4fc9a0 Gerrit-Change-Number: 29406 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: config GPP_E1 for WLAN_WAKE_L
by Nick Vaccaro (Code Review) 13 Nov '18

13 Nov '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/29630 Change subject: mb/google/poppy/variant/nocturne: config GPP_E1 for WLAN_WAKE_L ...................................................................... mb/google/poppy/variant/nocturne: config GPP_E1 for WLAN_WAKE_L The GPP_E1 gpio was incorrectly being defined as a no-connect. Configure GPP_E1 for the WLAN_WAKE_L signal. BUG=b:119508897 TEST=none Change-Id: I4efb4f6d601e172ae4807901e3bd4c9954319f80 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/29630/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index 70b748b..c62317a 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -212,8 +212,8 @@ /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), - /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + /* E1 : SATAXPCIE1 ==> WLAN_WAKE_L */ + PAD_CFG_GPI_ACPI_SCI(GPP_E1, NONE, DEEP, INVERT), /* E2 : SATAXPCIE2 ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_E2, 1, DEEP), /* E3 : CPU_GP0 ==> NC */ -- To view, visit https://review.coreboot.org/29630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4efb4f6d601e172ae4807901e3bd4c9954319f80 Gerrit-Change-Number: 29630 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

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Change in coreboot[master]: mb/*/*/Kconfig: Don't specify devicetree path if default val used
by Angel Pons (Code Review) 13 Nov '18

13 Nov '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/29625 ) Change subject: mb/*/*/Kconfig: Don't specify devicetree path if default val used ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3d77a625c5ece7b7ea5476fe0bd42829d1fc72c4 Gerrit-Change-Number: 29625 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Nov 2018 20:32:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part Number
by Martin Roth (Code Review) 13 Nov '18

13 Nov '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/29557 ) Change subject: google/grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part Number ...................................................................... google/grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part Number Correct SPD Module Part Number to "K4A8G165WC-BCTD" from "M471A5244CB0-CTD". BUG=b:119400832 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage mosys memory spd print all 0 | DDR4 | SO-DIMM 0 | 1-78: Samsung | 00000000 | K4A8G165WC-BCTD 0 | 4096 | 1 | 64 0 | DDR4-1333, DDR4-1600, DDR4-2400 Change-Id: I29505d3eece2283579499a0afc424c4a28017fa5 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Reviewed-on: https://review.coreboot.org/29557 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WC-BCTD.spd.hex 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WC-BCTD.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WC-BCTD.spd.hex index 2688254..d03dc5b 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WC-BCTD.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WC-BCTD.spd.hex @@ -19,8 +19,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 35 32 -34 34 43 42 30 2D 43 54 44 20 20 20 20 00 80 CE +80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36 +35 57 43 2D 42 43 54 44 20 20 20 20 20 00 80 CE 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/29557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I29505d3eece2283579499a0afc424c4a28017fa5 Gerrit-Change-Number: 29557 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part Number
by Martin Roth (Code Review) 13 Nov '18

13 Nov '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/29557 ) Change subject: google/grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part Number ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/29557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I29505d3eece2283579499a0afc424c4a28017fa5 Gerrit-Change-Number: 29557 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Nov 2018 20:30:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: azalia: Add Azalia Reset macro
by build bot (Jenkins) (Code Review) 13 Nov '18

13 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29554 ) Change subject: azalia: Add Azalia Reset macro ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/29554/7/src/include/device/azalia_device.h File src/include/device/azalia_device.h: https://review.coreboot.org/#/c/29554/7/src/include/device/azalia_device.h@… PS7, Line 50: #define AZALIA_RESET(pin) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/29554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36 Gerrit-Change-Number: 29554 Gerrit-PatchSet: 7 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Nov 2018 19:21:01 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: google/grunt/aleena: Update H1/TP/TS i2c timings
by Martin Roth (Code Review) 13 Nov '18

13 Nov '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/29548 ) Change subject: google/grunt/aleena: Update H1/TP/TS i2c timings ...................................................................... google/grunt/aleena: Update H1/TP/TS i2c timings After adjustment on aleena EVT Audio: 390.0 KHz H1: 390.0 KHz TP: 399.8 KHz TS: 399.8 kHz BUG=b:116306959 BRANCH=master TEST=emerge-grunt coreboot, scope measuring. Change-Id: I6f621508ce2dbb1b9dcdf529ac35afc80d485f53 Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29548 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/variants/aleena/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb index 27a8e28..784ea6f 100644 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb @@ -32,22 +32,22 @@ register "i2c[1]" = "{ .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 84, + .rise_time_ns = 45, .fall_time_ns = 4, }" # Enable I2C2 for trackpad, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 117, - .fall_time_ns = 113, + .rise_time_ns = 26, + .fall_time_ns = 11, }" # Enable I2C3 for touchscreen at 400kHz register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 82, - .fall_time_ns = 67, + .rise_time_ns = 20, + .fall_time_ns = 19, }" register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ -- To view, visit https://review.coreboot.org/29548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I6f621508ce2dbb1b9dcdf529ac35afc80d485f53 Gerrit-Change-Number: 29548 Gerrit-PatchSet: 2 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/grunt/aleena: Update H1/TP/TS i2c timings
by Martin Roth (Code Review) 13 Nov '18

13 Nov '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/29548 ) Change subject: google/grunt/aleena: Update H1/TP/TS i2c timings ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6f621508ce2dbb1b9dcdf529ac35afc80d485f53 Gerrit-Change-Number: 29548 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Nov 2018 19:03:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/sarien: Enable EC _PTS/_WAK methods
by Duncan Laurie (Code Review) 13 Nov '18

13 Nov '18

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/29614 ) Change subject: mb/google/sarien: Enable EC _PTS/_WAK methods ...................................................................... mb/google/sarien: Enable EC _PTS/_WAK methods Enable the option to have the system level _PTS/_WAK methods call the EC provided methods when they are invoked by the OS. Verified on sarien board by inspecting dsdt.dsl: Method (_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep { DBG0 = 0x96 \_SB.PCI0.LPCB.EC0.PTS (Arg0) } Method (_WAK, 1, NotSerialized) // _WAK: Wake { DBG0 = 0x97 \_SB.PCI0.LPCB.EC0.WAK (Arg0) Return (Package (0x02) { Zero, Zero }) } Change-Id: I52be1c1cd7adae9ad317a51868735eb87a410549 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/29614 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/sarien/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index e571be2..7494edd 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_HAS_TPM2 select SOC_INTEL_COFFEELAKE select SOC_INTEL_CANNONLAKE_MEMCFG_INIT + select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP -- To view, visit https://review.coreboot.org/29614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I52be1c1cd7adae9ad317a51868735eb87a410549 Gerrit-Change-Number: 29614 Gerrit-PatchSet: 4 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/cannonlake: Remove SmbusEnable
by Duncan Laurie (Code Review) 13 Nov '18

13 Nov '18

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/29552 ) Change subject: soc/intel/cannonlake: Remove SmbusEnable ...................................................................... soc/intel/cannonlake: Remove SmbusEnable Remove the SmbusEnable config option from devicetree and instead use the state of the PCI device to determine if it should be enabled or disabled. Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/29552 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 5 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 2deb35f..015133e 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -166,9 +166,6 @@ * clksrc. */ uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; - /* SMBus */ - uint8_t SmbusEnable; - /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; /* Need to update DLL setting to get Emmc running at HS400 speed */ diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 8506214..8f6fa2f 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -66,6 +66,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct device *smbus = dev_find_slot(0, PCH_DEVFN_SMBUS); assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; @@ -73,7 +74,10 @@ soc_memory_init_params(m_cfg, config); /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; + if (!smbus) + m_cfg->SmbusEnable = 0; + else + m_cfg->SmbusEnable = smbus->enabled; /* Set debug probe type */ m_cfg->PlatformDebugConsent = config->DebugConsent; -- To view, visit https://review.coreboot.org/29552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a Gerrit-Change-Number: 29552 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit November 2018