coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

1 participants
1699 discussions

Change in coreboot[master]: src/mainboard/google: Remove defining EC_ENABLE_TABLET_EVENT config
by Karthik Ramasubramanian (Code Review) 14 Nov '18

14 Nov '18

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/29637 Change subject: src/mainboard/google: Remove defining EC_ENABLE_TABLET_EVENT config ...................................................................... src/mainboard/google: Remove defining EC_ENABLE_TABLET_EVENT config Remove defining EC_ENABLE_TABLET_EVENT configuration from the boards where it is not required. BUG=b:118149364 BRANCH=None TEST=Build Change-Id: Iee70192916ac6c53bb27b7f73f3ad6d069afd030 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/eve/ec.h M src/mainboard/google/poppy/variants/nami/include/variant/ec.h M src/mainboard/google/poppy/variants/rammus/include/variant/ec.h 3 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/29637/1 diff --git a/src/mainboard/google/eve/ec.h b/src/mainboard/google/eve/ec.h index 1b55248..b940121 100644 --- a/src/mainboard/google/eve/ec.h +++ b/src/mainboard/google/eve/ec.h @@ -77,8 +77,6 @@ #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE /* Enable Tablet switch */ -#define EC_ENABLE_TABLET_EVENT - #define EC_ENABLE_TBMC_DEVICE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/ec.h b/src/mainboard/google/poppy/variants/nami/include/variant/ec.h index a5a0196..843161a 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/nami/include/variant/ec.h @@ -69,7 +69,6 @@ #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE /* Enable Tablet switch */ -#define EC_ENABLE_TABLET_EVENT #define EC_ENABLE_TBMC_DEVICE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ diff --git a/src/mainboard/google/poppy/variants/rammus/include/variant/ec.h b/src/mainboard/google/poppy/variants/rammus/include/variant/ec.h index b22fccb..d4a07b5 100644 --- a/src/mainboard/google/poppy/variants/rammus/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/rammus/include/variant/ec.h @@ -73,7 +73,6 @@ #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE /* Enable Tablet switch */ -#define EC_ENABLE_TABLET_EVENT #define EC_ENABLE_TBMC_DEVICE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -- To view, visit https://review.coreboot.org/29637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iee70192916ac6c53bb27b7f73f3ad6d069afd030 Gerrit-Change-Number: 29637 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org>

1 0

Change in coreboot[master]: mb/google/octopus/variants/bobba: Set tcc offset for bobba
by Sumeet R Pawnikar (Code Review) 14 Nov '18

14 Nov '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/29636 Change subject: mb/google/octopus/variants/bobba: Set tcc offset for bobba ...................................................................... mb/google/octopus/variants/bobba: Set tcc offset for bobba Change tcc offset from 0 to 10 degree celsius for bobba. BUG=b:118099582 TEST=Cross verified the value using TAT UI. Change-Id: I68527c27635844f4edb0dda5f6018589d7bae297 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/octopus/variants/bobba/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/29636/1 diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 6ba69ff..dab13a5 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -13,6 +13,9 @@ #| I2C6 | Trackpad | #| I2C7 | Touchscreen | #+-------------------+---------------------------+ + + register "tcc_offset" = "10" + register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, -- To view, visit https://review.coreboot.org/29636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I68527c27635844f4edb0dda5f6018589d7bae297 Gerrit-Change-Number: 29636 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

1 0

Change in coreboot[master]: siemens/mc_apl5: Add new mainboard variant mc_apl5
by Mario Scheithauer (Code Review) 14 Nov '18

14 Nov '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29635 Change subject: siemens/mc_apl5: Add new mainboard variant mc_apl5 ...................................................................... siemens/mc_apl5: Add new mainboard variant mc_apl5 This mainboard is based on mc_apl1. In a first step, it concerns a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl5 mainboard will follow in separate commits. Change-Id: Icdbb116a822ffa7a3bfb7026a5d1164db56a0c46 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/Kconfig.name A src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig A src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb A src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h A src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c A src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c 8 files changed, 521 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/29635/1 diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig index eeb5d9b..638b839 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -20,6 +20,7 @@ default "mc_apl2" if BOARD_SIEMENS_MC_APL2 default "mc_apl3" if BOARD_SIEMENS_MC_APL3 default "mc_apl4" if BOARD_SIEMENS_MC_APL4 + default "mc_apl5" if BOARD_SIEMENS_MC_APL5 config MAINBOARD_PART_NUMBER string @@ -27,6 +28,7 @@ default "MC APL2" if BOARD_SIEMENS_MC_APL2 default "MC APL3" if BOARD_SIEMENS_MC_APL3 default "MC APL4" if BOARD_SIEMENS_MC_APL4 + default "MC APL5" if BOARD_SIEMENS_MC_APL5 config MAX_CPUS int diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name index 592d8aa..3a5b6a3 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig.name +++ b/src/mainboard/siemens/mc_apl1/Kconfig.name @@ -10,6 +10,10 @@ bool "-> MC APL3" select BOARD_SIEMENS_BASEBOARD_MC_APL1 +config BOARD_SIEMENS_MC_APL5 + bool "-> MC APL5" + select BOARD_SIEMENS_BASEBOARD_MC_APL1 + config BOARD_SIEMENS_MC_APL4 bool "-> MC APL4" select BOARD_SIEMENS_BASEBOARD_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig new file mode 100644 index 0000000..fd472f7 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -0,0 +1,16 @@ + +if BOARD_SIEMENS_MC_APL5 + +config BOARD_SIEMENS_MC_APL5_VAR + def_bool y + select DRIVER_INTEL_I210 + select DRIVERS_I2C_RX6110SA + select DRIVER_SIEMENS_NC_FPGA + select NC_FPGA_NOTIFY_CB_READY + select APL_SKIP_SET_POWER_LIMITS + +config DEVICETREE + string + default "variants/mc_apl5/devicetree.cb" + +endif # BOARD_SIEMENS_MC_APL5 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc new file mode 100644 index 0000000..adf9aff --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc @@ -0,0 +1,2 @@ +ramstage-y += mainboard.c +ramstage-y += ptn3460.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb new file mode 100644 index 0000000..f3e8a77 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -0,0 +1,119 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "sci_irq" = "SCIS_IRQ10" + + # Disable unused clkreq of PCIe root ports + register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge + register "pcie_rp_clkreq_pin[1]" = "2" # FPGA + register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY + register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # 0:HS400(Default), 1:HS200, 2:DDR50 + register "emmc_host_max_speed" = "2" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Proximity Sensor | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_STANDARD + }, + }" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 on end # - Gen - Display + device pci 03.0 off end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 off end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 off end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY + device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY + device pci 13.2 off end # - RP 4 - PCIe-A 2 + device pci 13.3 off end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge + device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + # Enable external RTC chip + chip drivers/i2c/rx6110sa + register "pmon_sampling" = "PMON_SAMPL_256_MS" + register "bks_on" = "0" + register "bks_off" = "1" + register "iocut_en" = "1" + register "set_user_date" = "1" + register "user_year" = "04" + register "user_month" = "07" + register "user_day" = "01" + register "user_weekday" = "4" + device i2c 0x32 on end # RTC RX6110 SA + end + end + device pci 16.1 off end # - I2C 1 + device pci 16.2 off end # - I2C 2 + device pci 16.3 off end # - I2C 3 + device pci 17.0 off end # - I2C 4 + device pci 17.1 off end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 off end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 off end # - PWM + device pci 1b.0 off end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1d.0 off end # - UFS + device pci 1e.0 off end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h new file mode 100644 index 0000000..6ae3e2f --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014-2017 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef PTN3460_H_ +#define PTN3460_H_ + +#include <stdint.h> + +#define PTN_SLAVE_ADR 0x20 +#define PTN_I2C_CONTROLLER 0 + +#define PTN_EDID_OFF 0x00 +#define PTN_EDID_LEN 0x80 +#define PTN_CONFIG_OFF 0x80 +#define PTN_FLASH_CFG_OFF 0xE8 +#define PTN_FLASH_CFG_LEN 0x04 +#define PTN_MAX_EDID_NUM 6 + +/* Define some error codes that can be used. */ +#define PTN_NO_ERROR 0x00000000 +#define PTN_BUS_ERROR 0x10000000 +#define PTN_INVALID_EDID 0x20000000 + +struct ptn_3460_config { + /* DiplayPort interface control. */ + uint8_t dp_interface_ctrl; + /* LVDS interface control register 1. */ + uint8_t lvds_interface_ctrl1; + /* LVDS interface control register 2. */ + uint8_t lvds_interface_ctrl2; + /* LVDS interface control register 3. */ + uint8_t lvds_interface_ctrl3; + /* Select which EDID-block is emulated. */ + uint8_t edid_rom_emulation; + /* Select which EDID block to map to 0..0x7F. */ + uint8_t edid_rom_access_ctrl; + /* Smallest PWM frequency for back light. */ + uint8_t pwm_min[3]; + /* Biggest PWM frequency for back light. */ + uint8_t pwm_max[3]; + /* Fast link training control register. */ + uint8_t fast_link_ctrl; + /* Pin configuration control register 1. */ + uint8_t pin_cfg_ctrl1; + /* Pin configuration control register 2. */ + uint8_t pin_cfg_ctrl2; + /* Default PWM bit count in DPCD register. */ + uint8_t pwm_default; + /* Current PWM bit count in DPCD register. */ + uint16_t pwm_value; + /* Default PWM frequency in DPCD register. */ + uint8_t pwm_default_freq; + /* Panel T3 timing value. */ + uint8_t t3_timing; + /* Panel T12 timing value. */ + uint8_t t12_timing; + /* Back light control register. */ + uint8_t backlight_ctrl; + /* Panel T2 delay. */ + uint8_t t2_delay; + /* Panel T4 timing value. */ + uint8_t t4_timing; + /* Panel T5 delay. */ + uint8_t t5_delay; +} __packed; + +struct ptn_3460_flash { + /* Flash command (erase or erase and flash). */ + uint8_t cmd; + /* Magic number needed by the flash algorithm. */ + uint16_t magic; + /* Trigger for starting flash operation. */ + uint8_t trigger; +} __packed; + +int ptn3460_init(const char *hwi_block); +int ptn3460_write_edid(uint8_t edid_num, const uint8_t data[PTN_EDID_LEN]); +int ptn_select_edid(uint8_t edid_num); +#endif /* PTN3460_H_ */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c new file mode 100644 index 0000000..6d22fd9 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <gpio.h> +#include <hwilib.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> +#include <timer.h> +#include <timestamp.h> +#include <baseboard/variants.h> +#include <variant/ptn3460.h> + +#define TX_DWORD3 0xa8c + +void variant_mainboard_final(void) +{ + int status; + struct device *dev = NULL; + + /* + * Set up the DP2LVDS converter. + * ptn3460_init() may only be executed after i2c bus init. + */ + status = ptn3460_init("hwinfo.hex"); + if (status) + printk(BIOS_ERR, "LCD: Set up PTN with status 0x%x\n", status); + else + printk(BIOS_INFO, "LCD: Set up PTN was successful.\n"); + + /* + * PIR6 register mapping for PCIe root ports + * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# + */ + pcr_write16(PID_ITSS, 0x314c, 0x0321); + + /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ + dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); + if (dev) + pci_write_config8(dev, 0xd8, 0x3e); + + /* Enable CLKRUN_EN for power gating LPC */ + lpc_enable_pci_clk_cntl(); + + /* + * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 + * offset 0x341D bit3 and bit0. + * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 + * offset 0x341C bit [3:0]. + */ + pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); + + /* + * Correct the SATA transmit signal via the High Speed I/O Transmit + * Control Register 3. + * Bit [23:16] set the output voltage swing for TX line. + * The value 0x4a sets the swing level to 0.58 V. + */ + pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16)); +} + +static void wait_for_legacy_dev(void *unused) +{ + uint32_t legacy_delay, us_since_boot; + struct stopwatch sw; + + /* Open main hwinfo block. */ + if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + return; + + /* Get legacy delay parameter from hwinfo. */ + if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, + sizeof(legacy_delay)) != sizeof(legacy_delay)) + return; + + us_since_boot = get_us_since_boot(); + /* No need to wait if the time since boot is already long enough.*/ + if (us_since_boot > legacy_delay) + return; + stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); + printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", + legacy_delay - us_since_boot, legacy_delay); + stopwatch_wait_until_expired(&sw); + printk(BIOS_NOTICE, "done!\n"); +} + +static void finalize_boot(void *unused) +{ + /* Set coreboot ready LED. */ + gpio_output(CNV_RGI_DT, 1); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c new file mode 100644 index 0000000..829af2a --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c @@ -0,0 +1,177 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014-2017 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <lib.h> +#include <hwilib.h> +#include <device/i2c_simple.h> +#include <variant/ptn3460.h> + +/** + * This function sets up the DP2LVDS-converter to be used with the appropriate + * lcd panel. + * + * @param *hwi_block Filename in CBFS of the block to use as HW-Info. + * @return 0 on success or HWI-Data/PTN error code. + */ +int ptn3460_init(const char *hwi_block) +{ + struct ptn_3460_config cfg; + int status; + uint8_t disp_con = 0, color_depth = 0; + uint8_t edid_data[PTN_EDID_LEN]; + int i; + + if (!hwi_block || hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", + hwi_block); + return 1; + } + /* Get all needed information from hwinfo block. */ + if (hwilib_get_field(Edid, edid_data, sizeof(edid_data)) != + sizeof(edid_data)) { + printk(BIOS_ERR, "LCD: No EDID data available in %s\n", + hwi_block); + return 1; + } + if ((hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) != + sizeof(disp_con))) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", + hwi_block); + return 1; + } + if (hwilib_get_field(PF_Color_Depth, &color_depth, sizeof(color_depth)) + != sizeof(color_depth)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", + hwi_block); + return 1; + } + /* + * Here, all the desired information for setting up DP2LVDS converter + * is present. Inside the converter, table 6 will be used for the + * timings. + */ + status = ptn3460_write_edid(6, edid_data); + if (status) + return status; + /* Select this table to be emulated. */ + ptn_select_edid(6); + /* Read PTN configuration data. */ + status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_CONFIG_OFF, (uint8_t *)&cfg, + sizeof(cfg)); + if (status) + return (PTN_BUS_ERROR | status); + /* Set up configuration data according to the hwinfo block we get. */ + cfg.dp_interface_ctrl = 0; + cfg.lvds_interface_ctrl1 = 0x00; + if (disp_con == PF_DISPLCON_LVDS_DUAL) + /* Turn on dual LVDS lane and clock. */ + cfg.lvds_interface_ctrl1 |= 0x0b; + if (color_depth == PF_COLOR_DEPTH_6BIT) + /* Use 18 bits per pixel. */ + cfg.lvds_interface_ctrl1 |= 0x20; + + /* 1 % clock spreading, 300 mV LVDS swing. */ + cfg.lvds_interface_ctrl2 = 0x13; + /* No LVDS signal swap. */ + cfg.lvds_interface_ctrl3 = 0x00; + /* Delay T2 (VDD to LVDS active) by 16 ms. */ + cfg.t2_delay = 1; + /* 250 ms from LVDS to backlight active. */ + cfg.t3_timing = 10; + /* 1 second re-power delay. */ + cfg.t12_timing = 20; + /* 150 ms backlight off to LVDS inactive. */ + cfg.t4_timing = 3; + /* Delay T5 (LVDS to VDD inactive) by 16 ms. */ + cfg.t5_delay = 1; + /* Enable backlight control. */ + cfg.backlight_ctrl = 0; + + /* Write back configuration data to PTN3460. */ + for (i = 0; i < sizeof(struct ptn_3460_config); i++) { + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_CONFIG_OFF+i, + *(((uint8_t *)&cfg)+i)); + if (status) + return (PTN_BUS_ERROR | status); + } + + /* Read PTN configuration data. */ + status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_CONFIG_OFF, (uint8_t *)&cfg, sizeof(cfg)); + if (status) + return (PTN_BUS_ERROR | status); + + return PTN_NO_ERROR; +} + +/** + * This function writes one Extended Display Identification Data (EDID) + * structure to PTN3460. + * + * @param edid_num Number of EDID that must be written (0..6). + * @param *data Pointer to a buffer where data to write is stored in. + * @return 0 on success or error code. + */ +int ptn3460_write_edid(uint8_t edid_num, const uint8_t data[PTN_EDID_LEN]) +{ + int status; + int i; + + if (edid_num > PTN_MAX_EDID_NUM) + return PTN_INVALID_EDID; + + /* First enable access to the desired EDID table. */ + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_CONFIG_OFF + 5, edid_num); + if (status) + return (PTN_BUS_ERROR | status); + + /* Now we can simply write EDID-data to ptn3460. */ + for (i = 0; i < PTN_EDID_LEN; i++) { + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_EDID_OFF + i, data[i]); + if (status) + return (PTN_BUS_ERROR | status); + } + + return PTN_NO_ERROR; +} + +/** + * This function selects one of 7 EDID-tables inside PTN3460 which should be + * emulated on DisplayPort and turn emulation ON. + * + * @param edid_num Number of EDID to emulate (0..6). + * @return 0 on success or error code. + */ +int ptn_select_edid(uint8_t edid_num) +{ + int status; + uint8_t val; + + if (edid_num > PTN_MAX_EDID_NUM) + return PTN_INVALID_EDID; + /* Enable emulation of the desired EDID table. */ + val = (edid_num << 1) | 1; + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_CONFIG_OFF + 4, val); + if (status) + return (PTN_BUS_ERROR | status); + else + return PTN_NO_ERROR; +} -- To view, visit https://review.coreboot.org/29635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icdbb116a822ffa7a3bfb7026a5d1164db56a0c46 Gerrit-Change-Number: 29635 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

1 0

Change in coreboot[master]: sb/intel/common: Reset Pre-OP after atomic SPI cycle is finished
by Werner Zeh (Code Review) 14 Nov '18

14 Nov '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/29634 Change subject: sb/intel/common: Reset Pre-OP after atomic SPI cycle is finished ...................................................................... sb/intel/common: Reset Pre-OP after atomic SPI cycle is finished Make sure that the Pre-Op register is cleared when an atomic cycle has been finished without errors. Change-Id: Ied88337125b125474b411e2f39f668171d15bfac Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/southbridge/intel/common/spi.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/29634/1 diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 31cdb33..0aa3970 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -2,6 +2,7 @@ * Copyright (c) 2011 The Chromium OS Authors. * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * Copyright (C) 2011 Stefan Tauner + * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -610,7 +611,7 @@ return -1; } - return 0; + goto spi_xfer_exit; } /* @@ -675,6 +676,7 @@ } } +spi_xfer_exit: /* Clear atomic preop now that xfer is done */ writew_(0, cntlr->preop); -- To view, visit https://review.coreboot.org/29634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ied88337125b125474b411e2f39f668171d15bfac Gerrit-Change-Number: 29634 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

1 0

Change in coreboot[master]: fsp_broadwell_de: Switch to common SPI controller driver
by Werner Zeh (Code Review) 14 Nov '18

14 Nov '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/29633 Change subject: fsp_broadwell_de: Switch to common SPI controller driver ...................................................................... fsp_broadwell_de: Switch to common SPI controller driver The common SPI controller driver in src/southbridge/intel/common does match the SPI controller included in the PCH of Broadwell-DE SoC. Switch to the usage of this driver and delete the dedicated one for the FSP based Broadwell-DE implementation. TEST: Boot mc_bdx1 with SPI driver active in romstage Change-Id: I4fe8057ea1981e350659a5caa9912fb758110115 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/fsp_broadwell_de/Makefile.inc D src/soc/intel/fsp_broadwell_de/spi.c 3 files changed, 2 insertions(+), 630 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/29633/1 diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index ec010b3..7046ff0 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -12,12 +12,13 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select SOUTHBRIDGE_INTEL_COMMON + select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RESET select NO_RELOCATABLE_RAMSTAGE select PARALLEL_MP select SMP select IOAPIC - select SPI_FLASH select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS # Microcode header files are delivered in FSP package diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 5448190..f88cbba 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -12,9 +12,6 @@ subdirs-y += fsp romstage-y += gpio.c -romstage-y += spi.c - -ramstage-y += spi.c ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += northcluster.c diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c deleted file mode 100644 index a778aa9..0000000 --- a/src/soc/intel/fsp_broadwell_de/spi.c +++ /dev/null @@ -1,626 +0,0 @@ -/* - * Copyright (c) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2016 Siemens AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file is derived from the flashrom project. */ -#include <stdint.h> -#include <stdlib.h> -#include <string.h> -#include <delay.h> -#include <commonlib/helpers.h> -#include <arch/io.h> -#include <console/console.h> -#include <device/pci_ids.h> -#include <spi_flash.h> -#include <spi-generic.h> -#include <arch/early_variables.h> - -#ifdef __SMM__ -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#else /* !__SMM__ */ -#include <device/device.h> -#include <device/pci.h> -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#endif /* !__SMM__ */ - -typedef struct spi_slave ich_spi_slave; - -static int ichspi_lock CAR_GLOBAL = 0; - -typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint32_t bbar; - uint8_t _reserved3[12]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; -} __packed ich9_spi_regs; - -typedef struct ich_spi_controller { - int locked; - - uint8_t *opmenu; - int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; - unsigned databytes; - uint8_t *status; - uint16_t *control; - uint32_t *bbar; -} ich_spi_controller; - -static ich_spi_controller cntlr CAR_GLOBAL; - -enum { - SPIS_SCIP = 0x0001, - SPIS_GRANT = 0x0002, - SPIS_CDS = 0x0004, - SPIS_FCERR = 0x0008, - SSFS_AEL = 0x0010, - SPIS_LOCK = 0x8000, - SPIS_RESERVED_MASK = 0x7ff0, - SSFS_RESERVED_MASK = 0x7fe2 -}; - -enum { - SPIC_SCGO = 0x000002, - SPIC_ACS = 0x000004, - SPIC_SPOP = 0x000008, - SPIC_DBC = 0x003f00, - SPIC_DS = 0x004000, - SPIC_SME = 0x008000, - SSFC_SCF_MASK = 0x070000, - SSFC_RESERVED = 0xf80000 -}; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_AEL = 0x0004, - HSFS_BERASE_MASK = 0x0018, - HSFS_BERASE_SHIFT = 3, - HSFS_SCIP = 0x0020, - HSFS_FDOPSS = 0x2000, - HSFS_FDV = 0x4000, - HSFS_FLOCKDN = 0x8000 -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_MASK = 0x0006, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_MASK = 0x3f00, - HSFC_FDBC_SHIFT = 8, - HSFC_FSMIE = 0x8000 -}; - -enum { - SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, - SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, - SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, - SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 -}; - -#define SPI_OFFSET_MASK 0x3ff - -static uint8_t readb_(const void *addr) -{ - uint8_t v = read8(addr); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", - v, ((uint32_t) addr) & SPI_OFFSET_MASK); - } - return v; -} - -static uint16_t readw_(const void *addr) -{ - uint16_t v = read16(addr); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", - v, ((uint32_t) addr) & SPI_OFFSET_MASK); - } - return v; -} - -static uint32_t readl_(const void *addr) -{ - uint32_t v = read32(addr); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", - v, ((uint32_t) addr) & SPI_OFFSET_MASK); - } - return v; -} - -static void writeb_(uint8_t b, void *addr) -{ - write8(addr, b); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", - b, ((uint32_t) addr) & SPI_OFFSET_MASK); - } -} - -static void writew_(uint16_t b, void *addr) -{ - write16(addr, b); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", - b, ((uint32_t) addr) & SPI_OFFSET_MASK); - } -} - -static void writel_(uint32_t b, void *addr) -{ - write32(addr, b); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", - b, ((uint32_t) addr) & SPI_OFFSET_MASK); - } -} - -static void write_reg(const void *value, void *dest, uint32_t size) -{ - const uint8_t *bvalue = value; - uint8_t *bdest = dest; - - while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); - bdest += 4; bvalue += 4; size -= 4; - } - while (size) { - writeb_(*bvalue, bdest); - bdest++; bvalue++; size--; - } -} - -static void read_reg(const void *src, void *value, uint32_t size) -{ - const uint8_t *bsrc = src; - uint8_t *bvalue = value; - - while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); - bsrc += 4; bvalue += 4; size -= 4; - } - while (size) { - *bvalue = readb_(bsrc); - bsrc++; bvalue++; size--; - } -} - -static void ich_set_bbar(uint32_t minaddr) -{ - const uint32_t bbar_mask = 0x00ffff00; - uint32_t ichspi_bbar; - - minaddr &= bbar_mask; - ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; - ichspi_bbar |= minaddr; - writel_(ichspi_bbar, cntlr.bbar); -} - -void spi_init(void) -{ - uint8_t *rcrb; /* Root Complex Register Block */ - uint32_t rcba; /* Root Complex Base Address */ - uint8_t bios_cntl; - ich9_spi_regs *ich9_spi; - -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCI_DEV(0, 31, 0); -#else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(31, 0)); -#endif - - pci_read_config_dword(dev, 0xf0, &rcba); - /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ - rcrb = (uint8_t *)(rcba & 0xffffc000); - ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.bbar = &ich9_spi->bbar; - cntlr.preop = &ich9_spi->preop; - ich_set_bbar(0); - - /* Disable the BIOS write protect so write commands are allowed. */ - pci_read_config_byte(dev, 0xdc, &bios_cntl); - bios_cntl &= ~(1 << 5); - pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); -} - -typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; -} spi_transaction; - -static inline void spi_use_out(spi_transaction *trans, unsigned bytes) -{ - trans->out += bytes; - trans->bytesout -= bytes; -} - -static inline void spi_use_in(spi_transaction *trans, unsigned bytes) -{ - trans->in += bytes; - trans->bytesin -= bytes; -} - -static void spi_setup_type(spi_transaction *trans) -{ - trans->type = 0xFF; - - /* Try to guess spi type from read/write sizes. */ - if (trans->bytesin == 0) { - if (trans->bytesout > 4) - /* - * If bytesin = 0 and bytesout > 4, we presume this is - * a write data operation, which is accompanied by an - * address. - */ - trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; - else - trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - return; - } - - if (trans->bytesout == 1) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - return; - } - - if (trans->bytesout == 4) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - } - - /* Fast read command is called with 5 bytes instead of 4 */ - if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - --trans->bytesout; - } -} - -static int spi_setup_opcode(spi_transaction *trans) -{ - uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; - - trans->opcode = trans->out[0]; - spi_use_out(trans, 1); - if (!ichspi_lock) { - /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr.opmenu); - optypes = readw_(cntlr.optype); - optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr.optype); - return 0; - } else { - /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; - - /* Write Enable is handled as atomic prefix */ - if (trans->opcode == SPI_OPCODE_WREN) - return 0; - - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; - opcode_index++) { - if (opmenu[opcode_index] == trans->opcode) - break; - } - - if (opcode_index == cntlr.menubytes) { - printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", - trans->opcode); - return -1; - } - - optypes = readw_(cntlr.optype); - optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } - if (optype != trans->type) { - printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", - optype); - return -1; - } - return opcode_index; - } -} - -static int spi_setup_offset(spi_transaction *trans) -{ - /* Separate the SPI address and data. */ - switch (trans->type) { - case SPI_OPCODE_TYPE_READ_NO_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: - return 0; - case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); - spi_use_out(trans, 3); - return 1; - default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); - return -1; - } -} - -/* - * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set - * below is True) or 0. In case the wait was for the bit(s) to set - write - * those bits back, which would cause resetting them. - * - * Return the last read status value on success or -1 on failure. - */ -static int ich_status_poll(uint16_t bitmask, int wait_til_set) -{ - int timeout = 40000; /* This will result in 400 ms */ - uint16_t status = 0; - - while (timeout--) { - status = readw_(cntlr.status); - if (wait_til_set ^ ((status & bitmask) == 0)) { - if (wait_til_set) - writew_((status & bitmask), cntlr.status); - return status; - } - udelay(10); - } - - printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); - return -1; -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - uint16_t control; - int16_t opcode_index; - int with_address; - int status; - - spi_transaction trans = { - dout, bytesout, - din, bytesin, - 0xff, 0xff, 0 - }; - - /* There has to always at least be an opcode. */ - if (!bytesout || !dout) { - printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); - return -1; - } - /* Make sure if we read something we have a place to put it. */ - if (bytesin != 0 && !din) { - printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); - return -1; - } - - if (ich_status_poll(SPIS_SCIP, 0) == -1) - return -1; - - writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); - - spi_setup_type(&trans); - opcode_index = spi_setup_opcode(&trans); - if (opcode_index < 0) - return -1; - with_address = spi_setup_offset(&trans); - if (with_address < 0) - return -1; - - if (!ichspi_lock && trans.opcode == SPI_OPCODE_WREN) { - /* - * Treat Write Enable as Atomic Pre-Op if possible - * in order to prevent the Management Engine from - * issuing a transaction between WREN and DATA. - */ - writew_(trans.opcode, cntlr.preop); - return 0; - } - - /* Preset control fields */ - control = SPIC_SCGO | ((opcode_index & 0x07) << 4); - - /* Issue atomic preop cycle if needed */ - if (readw_(cntlr.preop)) - control |= SPIC_ACS; - - if (!trans.bytesout && !trans.bytesin) { - /* SPI addresses are 24 bit only */ - if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - /* - * This is a 'no data' command (like Write Enable), its - * bitesout size was 1, decremented to zero while executing - * spi_setup_opcode() above. Tell the chip to send the - * command. - */ - writew_(control, cntlr.control); - - /* wait for the result */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); - return -1; - } - - goto spi_xfer_exit; - } - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (trans.bytesout > cntlr.databytes) { - printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" - " spi_crop_chunk()?\n"); - return -1; - } - - /* - * Read or write up to databytes bytes at a time until everything has - * been sent. - */ - while (trans.bytesout || trans.bytesin) { - uint32_t data_length; - - /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); - else - data_length = min(trans.bytesin, cntlr.databytes); - - /* Program data into FDATA0 to N */ - if (trans.bytesout) { - write_reg(trans.out, cntlr.data, data_length); - spi_use_out(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - - /* Add proper control fields' values */ - control &= ~((cntlr.databytes - 1) << 8); - control |= SPIC_DS; - control |= (data_length - 1) << 8; - - /* write it */ - writew_(control, cntlr.control); - - /* Wait for Cycle Done Status or Flash Cycle Error. */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); - return -1; - } - - if (trans.bytesin) { - read_reg(cntlr.data, trans.in, data_length); - spi_use_in(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - } - -spi_xfer_exit: - /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr.preop); - - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = member_size(ich9_spi_regs, fdata), -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/29633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4fe8057ea1981e350659a5caa9912fb758110115 Gerrit-Change-Number: 29633 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

1 0

Change in coreboot[master]: ACPI: Fix DSDT's revision field
by Tristan Corrick (Code Review) 14 Nov '18

14 Nov '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/29626 ) Change subject: ACPI: Fix DSDT's revision field ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/29626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f Gerrit-Change-Number: 29626 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Nov 2018 09:06:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: siemens/mc_apl4: Clean up ramstage
by Mario Scheithauer (Code Review) 14 Nov '18

14 Nov '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29632 Change subject: siemens/mc_apl4: Clean up ramstage ...................................................................... siemens/mc_apl4: Clean up ramstage Currently, there is nothing for this mainboard to do in ramstage. Change-Id: Id74a5f3f0a0583dc6bc81044913b8bb83d3b0b93 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc D src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c 3 files changed, 0 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/29632/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig index 3cf7406..ea81c6c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig @@ -4,10 +4,6 @@ config BOARD_SIEMENS_MC_APL4_VAR def_bool y select DRIVER_INTEL_I210 - select DRIVERS_I2C_RX6110SA - select DRIVER_SIEMENS_NC_FPGA - select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS config DEVICETREE string diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc index caf542f..fd45b94 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc @@ -1,3 +1 @@ romstage-y += memory.c - -ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c deleted file mode 100644 index ccf3ab8..0000000 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <bootstate.h> -#include <console/console.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <gpio.h> -#include <hwilib.h> -#include <intelblocks/lpc_lib.h> -#include <intelblocks/pcr.h> -#include <soc/pcr_ids.h> -#include <timer.h> -#include <timestamp.h> -#include <baseboard/variants.h> - -#define TX_DWORD3 0xa8c - -void variant_mainboard_final(void) -{ - struct device *dev = NULL; - - /* - * PIR6 register mapping for PCIe root ports - * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# - */ - pcr_write16(PID_ITSS, 0x314c, 0x0321); - - /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ - dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); - if (dev) - pci_write_config8(dev, 0xd8, 0x3e); - - /* Enable CLKRUN_EN for power gating LPC */ - lpc_enable_pci_clk_cntl(); - - /* - * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 - * offset 0x341D bit3 and bit0. - * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 - * offset 0x341C bit [3:0]. - */ - pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); - - /* - * Correct the SATA transmit signal via the High Speed I/O Transmit - * Control Register 3. - * Bit [23:16] set the output voltage swing for TX line. - * The value 0x4a sets the swing level to 0.58 V. - */ - pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16)); -} - -static void wait_for_legacy_dev(void *unused) -{ - uint32_t legacy_delay, us_since_boot; - struct stopwatch sw; - - /* Open main hwinfo block. */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) - return; - - /* Get legacy delay parameter from hwinfo. */ - if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, - sizeof(legacy_delay)) != sizeof(legacy_delay)) - return; - - us_since_boot = get_us_since_boot(); - /* No need to wait if the time since boot is already long enough.*/ - if (us_since_boot > legacy_delay) - return; - stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); - printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", - legacy_delay - us_since_boot, legacy_delay); - stopwatch_wait_until_expired(&sw); - printk(BIOS_NOTICE, "done!\n"); -} - -static void finalize_boot(void *unused) -{ - /* Set coreboot ready LED. */ - gpio_output(CNV_RGI_DT, 1); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); -- To view, visit https://review.coreboot.org/29632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id74a5f3f0a0583dc6bc81044913b8bb83d3b0b93 Gerrit-Change-Number: 29632 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

1 0

Change in coreboot[master]: mb/google/poppy/variants/nautilus: Control GPP_D0 in 2nd SKU only
by Furquan Shaikh (Code Review) 14 Nov '18

14 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29631 ) Change subject: mb/google/poppy/variants/nautilus: Control GPP_D0 in 2nd SKU only ...................................................................... Patch Set 3: > Patch Set 3: > > > (1 comment) > > Sure. Please hold on to merge this change. I will ask H/W guy to check real signal of GPP_D0 at entering S5 and then mark code-review +1. SG. Thanks! -- To view, visit https://review.coreboot.org/29631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd85693c9155ed960f0c794d4b83fe8863b77134 Gerrit-Change-Number: 29631 Gerrit-PatchSet: 3 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Ben Chan <benchan(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Nov 2018 02:57:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/poppy/variants/nautilus: Control GPP_D0 in 2nd SKU only
by Furquan Shaikh (Code Review) 14 Nov '18

14 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29631 ) Change subject: mb/google/poppy/variants/nautilus: Control GPP_D0 in 2nd SKU only ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/29631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd85693c9155ed960f0c794d4b83fe8863b77134 Gerrit-Change-Number: 29631 Gerrit-PatchSet: 3 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Ben Chan <benchan(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Nov 2018 02:57:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/poppy/variants/nautilus: Control GPP_D0 in 2nd SKU only
by Seunghwan Kim (Code Review) 14 Nov '18

14 Nov '18

Seunghwan Kim has posted comments on this change. ( https://review.coreboot.org/29631 ) Change subject: mb/google/poppy/variants/nautilus: Control GPP_D0 in 2nd SKU only ...................................................................... Patch Set 3: > (1 comment) Sure. Please hold on to merge this change. I will ask H/W guy to check real signal of GPP_D0 at entering S5 and then mark code-review +1. -- To view, visit https://review.coreboot.org/29631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd85693c9155ed960f0c794d4b83fe8863b77134 Gerrit-Change-Number: 29631 Gerrit-PatchSet: 3 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Ben Chan <benchan(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Nov 2018 02:56:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2018