Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29414
Change subject: src/soc/intel/braswell/acpi/southcluster.asl: Remove disabled LPE devices
......................................................................
src/soc/intel/braswell/acpi/southcluster.asl: Remove disabled LPE devices
ACPI code for LPE devices is enabled, but devices are disabled.
Remove the LPE devices when these are disabled.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/soc/intel/braswell/Kconfig
M src/soc/intel/braswell/acpi/southcluster.asl
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29414/1
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 2ba7992..6e3adcd 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -127,4 +127,10 @@
string
default "soc/intel/braswell/bootblock/timestamp.inc"
+config ENABLE_LPE_DEVICES
+ bool "Include ASL code for LPE devices"
+ default y
+ help
+ Enable this if the LPE interfaces are supported
+
endif
diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl
index f7e3168..7ec8c54 100644
--- a/src/soc/intel/braswell/acpi/southcluster.asl
+++ b/src/soc/intel/braswell/acpi/southcluster.asl
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2018 Eltan B.V.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -287,6 +288,8 @@
/* SCC Devices */
#include "scc.asl"
+#if IS_ENABLED(CONFIG_ENABLE_LPE_DEVICES)
/* LPE Device */
#include "lpe.asl"
+#endif
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73
Gerrit-Change-Number: 29414
Gerrit-PatchSet: 1
Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/29394
to look at the new patch set (#5).
Change subject: src/soc/intel/braswell/hda.c: Configure HDA codecs
......................................................................
src/soc/intel/braswell/hda.c: Configure HDA codecs
The support of the HDA did not configure the codecs.
Add hda_init() and hda_enable() to configure the codecs.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/mainboard/google/cyan/Makefile.inc
A src/mainboard/google/cyan/hda_verb.c
M src/mainboard/intel/strago/Makefile.inc
A src/mainboard/intel/strago/hda_verb.c
M src/soc/intel/braswell/hda.c
M src/soc/intel/braswell/include/soc/ramstage.h
M src/soc/intel/braswell/southcluster.c
7 files changed, 120 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29394/5
--
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Gerrit-Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63
Gerrit-Change-Number: 29394
Gerrit-PatchSet: 5
Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
John Su has posted comments on this change. ( https://review.coreboot.org/29413 )
Change subject: /mb/google/octopus/varinats/fleex: Set up tcc offset for fleex
......................................................................
Patch Set 1: Code-Review-1
Wait CL to merge.
(https://review.coreboot.org/c/coreboot/+/29351)
Then,help to review.
--
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Gerrit-MessageType: comment
Gerrit-Change-Id: I481526ab10a16a33fe0cf9528b52b8524e012451
Gerrit-Change-Number: 29413
Gerrit-PatchSet: 1
Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>
Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Thu, 01 Nov 2018 07:01:34 +0000
Gerrit-HasComments: No
Gerrit-HasLabels: Yes
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/29394
to look at the new patch set (#4).
Change subject: src/soc/intel/braswell/hda.c: Configure HDA codecs
......................................................................
src/soc/intel/braswell/hda.c: Configure HDA codecs
The support of the HDA did not configure the codecs.
Add hda_init() and hda_enable() to configure the codecs.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/mainboard/google/cyan/Makefile.inc
A src/mainboard/google/cyan/hda_verb.c
M src/soc/intel/braswell/hda.c
M src/soc/intel/braswell/include/soc/ramstage.h
M src/soc/intel/braswell/southcluster.c
5 files changed, 96 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29394/4
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63
Gerrit-Change-Number: 29394
Gerrit-PatchSet: 4
Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
John Su has uploaded this change for review. ( https://review.coreboot.org/29413
Change subject: /mb/google/octopus/varinats/fleex: Set up tcc offset for fleex
......................................................................
/mb/google/octopus/varinats/fleex: Set up tcc offset for fleex
Change tcc offset from 0 to 10 for fleex.
Refer to b:117789732#1
BUG=b:117789732
TEST=Match the result from TAT UI
Change-Id: I481526ab10a16a33fe0cf9528b52b8524e012451
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
---
M src/mainboard/google/octopus/variants/fleex/overridetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/29413/1
diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
index b557b62..9383662 100644
--- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
@@ -13,6 +13,8 @@
#| I2C7 | Touchscreen |
#+-------------------+---------------------------+
+ register "tcc_offset" = "10"
+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I481526ab10a16a33fe0cf9528b52b8524e012451
Gerrit-Change-Number: 29413
Gerrit-PatchSet: 1
Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/29394
to look at the new patch set (#3).
Change subject: src/soc/intel/braswell/hda.c: Configure HDA codecs
......................................................................
src/soc/intel/braswell/hda.c: Configure HDA codecs
The support of the HDA did not configure the codecs.
Add hda_init() and hda_enable() to configure the codecs.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/mainboard/google/cyan/Makefile.inc
M src/soc/intel/braswell/hda.c
M src/soc/intel/braswell/include/soc/ramstage.h
M src/soc/intel/braswell/southcluster.c
4 files changed, 74 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29394/3
--
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Gerrit-Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63
Gerrit-Change-Number: 29394
Gerrit-PatchSet: 3
Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>