coreboot-gerrit November 2018

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Change in coreboot[master]: sb/intel/bd82x6x/early_usb.c: Fix formating
by build bot (Jenkins) (Code Review) 01 Nov '18

01 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29428 ) Change subject: sb/intel/bd82x6x/early_usb.c: Fix formating ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29428/2/src/southbridge/intel/bd82x6x/early… File src/southbridge/intel/bd82x6x/early_usb.c: https://review.coreboot.org/#/c/29428/2/src/southbridge/intel/bd82x6x/early… PS2, Line 20: #include <northbridge/intel/sandybridge/sandybridge.h> /* For DEFAULT_RCBABASE */ line over 80 characters -- To view, visit https://review.coreboot.org/29428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0db1263ec11240003fe1f7080c758994fc0224d3 Gerrit-Change-Number: 29428 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Nov 2018 18:19:47 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: sb/intel/bd82x6x/early_usb.c: Fix formating
by Elyes HAOUAS (Code Review) 01 Nov '18

01 Nov '18

Elyes HAOUAS has uploaded a new patch set (#2). ( https://review.coreboot.org/29428 ) Change subject: sb/intel/bd82x6x/early_usb.c: Fix formating ...................................................................... sb/intel/bd82x6x/early_usb.c: Fix formating Remove whitespace between the function name and open parenthesis, and fix 81+ characters lines. Change-Id: I0db1263ec11240003fe1f7080c758994fc0224d3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/early_usb.c 1 file changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/29428/2 -- To view, visit https://review.coreboot.org/29428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0db1263ec11240003fe1f7080c758994fc0224d3 Gerrit-Change-Number: 29428 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: sb/intel/bd82x6x/early_usb.c: Fix formating
by Elyes HAOUAS (Code Review) 01 Nov '18

01 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29428 Change subject: sb/intel/bd82x6x/early_usb.c: Fix formating ...................................................................... sb/intel/bd82x6x/early_usb.c: Fix formating Remove whitespace between the function name and open parenthesis, and fix 81+ characters lines. Change-Id: I0db1263ec11240003fe1f7080c758994fc0224d3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/early_usb.c 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/29428/1 diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index d4ff783..527c93f 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -20,8 +20,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> /* For DEFAULT_RCBABASE. */ #include "pch.h" -void -early_usb_init (const struct southbridge_usb_port *portmap) +void early_usb_init(const struct southbridge_usb_port *portmap) { u32 reg32; const u32 rcba_dump[8] = { @@ -35,41 +34,42 @@ /* Activate PMBAR. */ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ + /* Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Unlock registers. */ outw(inw(DEFAULT_PMBASE | UPRWC) | UPRWC_WR_EN, DEFAULT_PMBASE | UPRWC); for (i = 0; i < 14; i++) - write32 (DEFAULT_RCBABASE + (0x3500 + 4 * i), + write32(DEFAULT_RCBABASE + (0x3500 + 4 * i), currents[portmap[i].current]); for (i = 0; i < 10; i++) - write32 (DEFAULT_RCBABASE + (0x3538 + 4 * i), 0); + write32(DEFAULT_RCBABASE + (0x3538 + 4 * i), 0); for (i = 0; i < 8; i++) - write32 (DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]); + write32(DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]); for (i = 0; i < 8; i++) - write32 (DEFAULT_RCBABASE + (0x3580 + 4 * i), 0); + write32(DEFAULT_RCBABASE + (0x3580 + 4 * i), 0); reg32 = 0; for (i = 0; i < 14; i++) if (!portmap[i].enabled) reg32 |= (1 << i); - write32 (DEFAULT_RCBABASE + USBPDO, reg32); + write32(DEFAULT_RCBABASE + USBPDO, reg32); reg32 = 0; for (i = 0; i < 8; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 0) reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); - write32 (DEFAULT_RCBABASE + USBOCM1, reg32); + write32(DEFAULT_RCBABASE + USBOCM1, reg32); reg32 = 0; for (i = 8; i < 14; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 4) reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); - write32 (DEFAULT_RCBABASE + USBOCM2, reg32); + write32(DEFAULT_RCBABASE + USBOCM2, reg32); for (i = 0; i < 22; i++) - write32 (DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0); + write32(DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0); - pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x14, 0), 0xe4, 0x00000000); /* Relock registers. */ outw(0, DEFAULT_PMBASE | UPRWC); -- To view, visit https://review.coreboot.org/29428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0db1263ec11240003fe1f7080c758994fc0224d3 Gerrit-Change-Number: 29428 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: sb/intel: Deduplicate vbnv_cmos_failed
by Patrick Rudolph (Code Review) 01 Nov '18

01 Nov '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/29427 Change subject: sb/intel: Deduplicate vbnv_cmos_failed ...................................................................... sb/intel: Deduplicate vbnv_cmos_failed Move all implementations to into common folder. Allows all Intel based platforms to use VBOOT_VBNV_CMOS. Change-Id: Ia494e6d418af6f907c648376674776c54d95ba71 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/bd82x6x/early_pch_common.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pmutil.c 8 files changed, 28 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/29427/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c index f1ac4f0..6c1df29 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_common.c +++ b/src/southbridge/intel/bd82x6x/early_pch_common.c @@ -23,7 +23,6 @@ #include <arch/acpi.h> #include <console/console.h> #include <rules.h> -#include <security/vboot/vbnv.h> #if ENV_ROMSTAGE uint64_t get_initial_timestamp(void) @@ -63,17 +62,3 @@ } #endif -int rtc_failure(void) -{ -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); -#else - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); -#endif - return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD); -} - -int vbnv_cmos_failed(void) -{ - return rtc_failure(); -} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index e234ca0..bb0d5c4 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -100,9 +100,6 @@ early_usb_init (const struct southbridge_usb_port *portmap); #endif - -/* Return non-zero when RTC failure happened. */ -int rtc_failure(void); #endif /* PM I/O Space */ diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 249d249..c27d339 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -52,4 +52,5 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smi.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c +romstage-y += pmutil.c endif diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index ac72eba..0cab015 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -19,11 +19,14 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> #include <cpu/x86/smm.h> #include <elog.h> #include <pc80/mc146818rtc.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/gpio.h> +#include <security/vboot/vbnv.h> #include "pmutil.h" @@ -234,3 +237,18 @@ return reg16; } + +int rtc_failure(void) +{ +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCI_DEV(0, 31, 0); +#else + struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0)); +#endif + return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD); +} + +int vbnv_cmos_failed(void) +{ + return rtc_failure(); +} diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 26134d9..af7bf97 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -104,6 +104,11 @@ #define TCO_LOCK (1 << 12) #define TCO2_CNT 0x6a +#define GEN_PMCON_3 0xa4 +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + u16 get_pmbase(void); u16 reset_pm1_status(void); @@ -127,4 +132,7 @@ void southbridge_smi_monitor(void); em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); +/* Return non-zero when RTC failure happened. */ +int rtc_failure(void); + #endif /*INTEL_COMMON_PMUTIL_H */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 5b09fed..7289929 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -36,6 +36,7 @@ #include <arch/acpigen.h> #include <cbmem.h> #include <drivers/intel/gma/i915.h> +#include <southbridge/intel/common/pmutil.h> #define NMI_OFF 0 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 489b565..76b9299 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -172,9 +172,6 @@ void enable_gpe(u32 mask); void disable_gpe(u32 mask); -/* Return non-zero when RTC failure happened. */ -int rtc_failure(void); - #if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/device.h> #include <arch/acpi.h> diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index e96d683..0916d2d 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -24,7 +24,6 @@ #include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> -#include <security/vboot/vbnv.h> #include "pch.h" #if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) @@ -555,17 +554,3 @@ outl(gpe0_en, get_pmbase() + gpe0_reg); } -int rtc_failure(void) -{ -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCI_DEV(0, 31, 0); -#else - struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0)); -#endif - return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD); -} - -int vbnv_cmos_failed(void) -{ - return rtc_failure(); -} -- To view, visit https://review.coreboot.org/29427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia494e6d418af6f907c648376674776c54d95ba71 Gerrit-Change-Number: 29427 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: src/soc/intel/braswell/southcluster.c: Configure IO APIC
by Frans Hendriks (Code Review) 01 Nov '18

01 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29423 to look at the new patch set (#3). Change subject: src/soc/intel/braswell/southcluster.c: Configure IO APIC ...................................................................... src/soc/intel/braswell/southcluster.c: Configure IO APIC IO APIC is not configured. Add sc_enable_ioapic() copied from fsp_baytrail Soc. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/include/soc/lpc.h M src/soc/intel/braswell/southcluster.c 2 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29423/3 -- To view, visit https://review.coreboot.org/29423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Gerrit-Change-Number: 29423 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: LinuxBoot: use curl
by Marcello Sylvester Bauer (Code Review) 01 Nov '18

01 Nov '18

Hello Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29426 to look at the new patch set (#3). Change subject: LinuxBoot: use curl ...................................................................... LinuxBoot: use curl Download the linux kernel tarball with curl. Curl is already a dependency for coreboot. Change-Id: I2e0bee3286593bd8e93b4d645242898eb9a14015 Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> --- M payloads/external/LinuxBoot/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29426/3 -- To view, visit https://review.coreboot.org/29426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2e0bee3286593bd8e93b4d645242898eb9a14015 Gerrit-Change-Number: 29426 Gerrit-PatchSet: 3 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/soc/intel/braswell/southcluster.c: Configure IO APIC
by Frans Hendriks (Code Review) 01 Nov '18

01 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29423 to look at the new patch set (#2). Change subject: src/soc/intel/braswell/southcluster.c: Configure IO APIC ...................................................................... src/soc/intel/braswell/southcluster.c: Configure IO APIC IO APIC is not configured. Add sc_enable_ioapic(). BUG=N/A TEST=Intel CherryHill CRB Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/southcluster.c 1 file changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29423/2 -- To view, visit https://review.coreboot.org/29423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Gerrit-Change-Number: 29423 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: LinuxBoot: use curl
by Marcello Sylvester Bauer (Code Review) 01 Nov '18

01 Nov '18

Marcello Sylvester Bauer has uploaded a new patch set (#2). ( https://review.coreboot.org/29426 ) Change subject: LinuxBoot: use curl ...................................................................... LinuxBoot: use curl Download the linux kernel tarball with curl. Curl is already a dependency for coreboot. The default progress bar is enable on purpose. Change-Id: I2e0bee3286593bd8e93b4d645242898eb9a14015 Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> --- M payloads/external/LinuxBoot/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29426/2 -- To view, visit https://review.coreboot.org/29426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2e0bee3286593bd8e93b4d645242898eb9a14015 Gerrit-Change-Number: 29426 Gerrit-PatchSet: 2 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com>

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Change in coreboot[master]: LinuxBoot: use curl
by Marcello Sylvester Bauer (Code Review) 01 Nov '18

01 Nov '18

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/29426 Change subject: LinuxBoot: use curl ...................................................................... LinuxBoot: use curl Download the linux kernel tarball with curl. Curl is already a dependency for coreboot. The default progress bar is enable by purpose. Change-Id: I2e0bee3286593bd8e93b4d645242898eb9a14015 Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> --- M payloads/external/LinuxBoot/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29426/1 diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index c051389..6a5f6b2 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -45,7 +45,7 @@ echo " WWW Download Linux $(CONFIG_LINUXBOOT_KERNEL_VERSION)" mkdir -p $(kernel_dir) ifeq ("$(wildcard $(kernel_dir)/README)","") - wget -qO- $(kernel_tarball) | tar xJ -C $(kernel_dir) --strip 1 + curl $(kernel_tarball) | tar xJ -C $(kernel_dir) --strip 1 endif config: $(kernel_dir)/.config -- To view, visit https://review.coreboot.org/29426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2e0bee3286593bd8e93b4d645242898eb9a14015 Gerrit-Change-Number: 29426 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com>

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Change in coreboot[master]: src/soc/intel/braswell/southcluster.c: Correct configuration of inter...
by build bot (Jenkins) (Code Review) 01 Nov '18

01 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29419 ) Change subject: src/soc/intel/braswell/southcluster.c: Correct configuration of interrupts ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/29419/3/src/soc/intel/braswell/southcluster… File src/soc/intel/braswell/southcluster.c: https://review.coreboot.org/#/c/29419/3/src/soc/intel/braswell/southcluster… PS3, Line 167: /* Set the Interrupt line register as "unknown or unused" */ line over 80 characters https://review.coreboot.org/#/c/29419/3/src/soc/intel/braswell/southcluster… PS3, Line 297: } else suspect code indent for conditional statements (8, 24) -- To view, visit https://review.coreboot.org/29419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I128cb35dd0e348a9cd9fb162651e0aa2b7e4a3ef Gerrit-Change-Number: 29419 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Nov 2018 12:54:35 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit November 2018