coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock
by build bot (Jenkins) (Code Review) 02 Nov '18

02 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25442 ) Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/25442/6/src/soc/intel/denverton_ns/lpc.c File src/soc/intel/denverton_ns/lpc.c: https://review.coreboot.org/#/c/25442/6/src/soc/intel/denverton_ns/lpc.c@419 PS6, Line 419: if(!relax_security) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/25442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd Gerrit-Change-Number: 25442 Gerrit-PatchSet: 6 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Fri, 02 Nov 2018 14:58:05 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: LinuxBoot: fix custom defconfig override
by Philipp Deppenwiese (Code Review) 02 Nov '18

02 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29424 ) Change subject: LinuxBoot: fix custom defconfig override ...................................................................... LinuxBoot: fix custom defconfig override The default ARCH defconfig should not override a custom defconfig. Change-Id: I9de24497ef6296029c66a94124bc11a0bb4d0107 Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> Reviewed-on: https://review.coreboot.org/29424 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M payloads/external/LinuxBoot/Makefile 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index c051389..b8e2c51 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -52,8 +52,7 @@ echo " CONFIG Linux $(CONFIG_LINUXBOOT_KERNEL_VERSION)" ifneq ($(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE),) cp $(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) $(kernel_dir)/.config -endif -ifeq ($(CONFIG_LINUXBOOT_ARCH),386) +else ifeq ($(CONFIG_LINUXBOOT_ARCH),386) cp x86/defconfig $(kernel_dir)/.config else ifeq ($(CONFIG_LINUXBOOT_ARCH),amd64) cp x86_64/defconfig $(kernel_dir)/.config -- To view, visit https://review.coreboot.org/29424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I9de24497ef6296029c66a94124bc11a0bb4d0107 Gerrit-Change-Number: 29424 Gerrit-PatchSet: 2 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/sifive/fu540: Load PLL settings from a struct
by Philipp Hug (Code Review) 02 Nov '18

02 Nov '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/29356 ) Change subject: soc/sifive/fu540: Load PLL settings from a struct ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/29356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5c0cee886bad5758c70f967d2bb998c1e1a736ab Gerrit-Change-Number: 29356 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Nov 2018 14:19:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/sifive/fu540: Load PLL settings from a struct
by Anonymous Coward (Code Review) 02 Nov '18

02 Nov '18

Anonymous Coward (1002162) has removed a vote on this change. Change subject: soc/sifive/fu540: Load PLL settings from a struct ...................................................................... Removed Code-Review+1 by Anonymous Coward (1002162) -- To view, visit https://review.coreboot.org/29356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: deleteVote Gerrit-Change-Id: I5c0cee886bad5758c70f967d2bb998c1e1a736ab Gerrit-Change-Number: 29356 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Anonymous Coward (1002162) Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/sifive/fu540: Load PLL settings from a struct
by Anonymous Coward (Code Review) 02 Nov '18

02 Nov '18

Anonymous Coward (1002162) has posted comments on this change. ( https://review.coreboot.org/29356 ) Change subject: soc/sifive/fu540: Load PLL settings from a struct ...................................................................... Patch Set 2: Code-Review+1 Thanks! -- To view, visit https://review.coreboot.org/29356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5c0cee886bad5758c70f967d2bb998c1e1a736ab Gerrit-Change-Number: 29356 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Anonymous Coward (1002162) Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Nov 2018 14:19:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/icelake: Add PID based on Icelake EDS
by Aamir Bohra (Code Review) 02 Nov '18

02 Nov '18

Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29436 to look at the new patch set (#3). Change subject: soc/intel/icelake: Add PID based on Icelake EDS ...................................................................... soc/intel/icelake: Add PID based on Icelake EDS Change-Id: I2d9e06f06a39dc76a3c1351d7976505d7bd92d10 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/include/soc/pcr_ids.h 2 files changed, 14 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/29436/3 -- To view, visit https://review.coreboot.org/29436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2d9e06f06a39dc76a3c1351d7976505d7bd92d10 Gerrit-Change-Number: 29436 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/icelake: Add PID based on Icelake EDS
by Aamir Bohra (Code Review) 02 Nov '18

02 Nov '18

Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29436 to look at the new patch set (#2). Change subject: soc/intel/icelake: Add PID based on Icelake EDS ...................................................................... soc/intel/icelake: Add PID based on Icelake EDS Change-Id: I2d9e06f06a39dc76a3c1351d7976505d7bd92d10 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/include/soc/pcr_ids.h 2 files changed, 13 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/29436/2 -- To view, visit https://review.coreboot.org/29436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2d9e06f06a39dc76a3c1351d7976505d7bd92d10 Gerrit-Change-Number: 29436 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/common: Include Icelake device IDs
by Aamir Bohra (Code Review) 02 Nov '18

02 Nov '18

Hello Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29435 to look at the new patch set (#2). Change subject: soc/intel/common: Include Icelake device IDs ...................................................................... soc/intel/common: Include Icelake device IDs Add Icelake specific CPU, System Agent, PCH, IGD device IDs. Change-Id: I2c398957ffbc9bb0e5b363740d99433075ca66a3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/icelake/bootblock/report_platform.c 22 files changed, 165 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/29435/2 -- To view, visit https://review.coreboot.org/29435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2c398957ffbc9bb0e5b363740d99433075ca66a3 Gerrit-Change-Number: 29435 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/common: Include Icelake Device Ids
by build bot (Jenkins) (Code Review) 02 Nov '18

02 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29435 ) Change subject: soc/intel/common: Include Icelake Device Ids ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29435/1/src/include/device/pci_ids.h File src/include/device/pci_ids.h: https://review.coreboot.org/#/c/29435/1/src/include/device/pci_ids.h@2967 PS1, Line 2967: #define PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT 0x8A71 please, no space before tabs -- To view, visit https://review.coreboot.org/29435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2c398957ffbc9bb0e5b363740d99433075ca66a3 Gerrit-Change-Number: 29435 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Nov 2018 13:12:54 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/icelake: Add PID based on Icelake EDS
by build bot (Jenkins) (Code Review) 02 Nov '18

02 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29436 ) Change subject: soc/intel/icelake: Add PID based on Icelake EDS ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29436/1/src/soc/intel/icelake/bootblock/pch… File src/soc/intel/icelake/bootblock/pch.c: https://review.coreboot.org/#/c/29436/1/src/soc/intel/icelake/bootblock/pch… PS1, Line 104: if (pmc_reg_value != 0xFFFFFFFF) that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/29436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2d9e06f06a39dc76a3c1351d7976505d7bd92d10 Gerrit-Change-Number: 29436 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Nov 2018 13:12:37 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit November 2018