coreboot-gerrit November 2018

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Change in coreboot[master]: intel/nb/*/gma: Use new common PMBASE API
by Patrick Rudolph (Code Review) 02 Nov '18

02 Nov '18

Patrick Rudolph has uploaded a new patch set (#2). ( https://review.coreboot.org/29439 ) Change subject: intel/nb/*/gma: Use new common PMBASE API ...................................................................... intel/nb/*/gma: Use new common PMBASE API * Introduce common function to enable TCO SCI. * Use new PMBASE functions to get rid of get_pmbase Change-Id: I6b5977b10d1e38b45e09530e9dcabbd5f42facb2 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/… [View More]

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Change in coreboot[master]: intel/nb/*/gma: Use new common PMBASE API
by Patrick Rudolph (Code Review) 02 Nov '18

02 Nov '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/29439 Change subject: intel/nb/*/gma: Use new common PMBASE API ...................................................................... intel/nb/*/gma: Use new common PMBASE API * Introduce common function to enable TCO SCI. * Use new PMBASE functions to get rid of get_pmbase Change-Id: I6b5977b10d1e38b45e09530e9dcabbd5f42facb2 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/… [View More]intel/fsp_sandybridge/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/sandybridge/gma.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h 6 files changed, 34 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/29439/1 diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c index cba5869..801fa6f 100644 --- a/src/northbridge/intel/fsp_sandybridge/gma.c +++ b/src/northbridge/intel/fsp_sandybridge/gma.c @@ -22,6 +22,7 @@ #include <southbridge/intel/fsp_bd82x6x/nvs.h> #include <drivers/intel/gma/opregion.h> #include <drivers/intel/gma/intel_bios.h> +#include <southbridge/intel/common/pmbase.h> #include <cbmem.h> @@ -105,17 +106,11 @@ u16 reg16; /* clear DMISCI status */ - reg16 = inw(DEFAULT_PMBASE + TCO1_STS); - reg16 &= DMISCI_STS; - outw(DEFAULT_PMBASE + TCO1_STS, reg16); + reg16 = read_pmbase16(TCO1_STS); + reg16 &= ~DMISCI_STS; + write_pmbase16(TCO1_STS, reg16); - /* clear acpi tco status */ - outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS); - - /* enable acpi tco scis */ - reg16 = inw(DEFAULT_PMBASE + GPE0_EN); - reg16 |= TCOSCI_EN; - outw(DEFAULT_PMBASE + GPE0_EN, reg16); + southbridge_enable_tco_sci(); } static void gma_init(struct device *dev) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index efc9fa3..2c05d0f 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -27,6 +27,7 @@ #include <cpu/intel/haswell/haswell.h> #include <drivers/intel/gma/opregion.h> #include <southbridge/intel/lynxpoint/nvs.h> +#include <southbridge/intel/common/pmbase.h> #include <stdlib.h> #include <string.h> @@ -444,9 +445,9 @@ u16 reg16; /* clear DMISCI status */ - reg16 = inw(get_pmbase() + TCO1_STS); - reg16 &= DMISCI_STS; - outw(get_pmbase() + TCO1_STS, reg16); + reg16 = read_pmbase16(TCO1_STS); + reg16 &= ~DMISCI_STS; + write_pmbase16(TCO1_STS, reg16); /* clear and enable ACPI TCO SCI */ enable_tco_sci(); diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index b89215d..77467bc 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -30,6 +30,7 @@ #include <pc80/vga_io.h> #include <southbridge/intel/ibexpeak/nvs.h> #include <drivers/intel/gma/opregion.h> +#include <southbridge/intel/common/pmbase.h> #include <cbmem.h> #include "chip.h" @@ -577,17 +578,11 @@ u16 reg16; /* clear DMISCI status */ - reg16 = inw(DEFAULT_PMBASE + TCO1_STS); - reg16 &= DMISCI_STS; - outw(DEFAULT_PMBASE + TCO1_STS, reg16); + reg16 = read_pmbase16(TCO1_STS); + reg16 &= ~DMISCI_STS; + write_pmbase16(TCO1_STS, reg16); - /* clear acpi tco status */ - outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS); - - /* enable acpi tco scis */ - reg16 = inw(DEFAULT_PMBASE + GPE0_EN); - reg16 |= TCOSCI_EN; - outw(DEFAULT_PMBASE + GPE0_EN, reg16); + southbridge_enable_tco_sci(); } static void gma_func0_init(struct device *dev) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index cd8f7b9..f54beb5 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -25,6 +25,7 @@ #include <drivers/intel/gma/libgfxinit.h> #include <southbridge/intel/bd82x6x/nvs.h> #include <drivers/intel/gma/opregion.h> +#include <southbridge/intel/common/pmbase.h> #include <cbmem.h> #include "chip.h" @@ -599,17 +600,11 @@ u16 reg16; /* clear DMISCI status */ - reg16 = inw(DEFAULT_PMBASE + TCO1_STS); - reg16 &= DMISCI_STS; - outw(DEFAULT_PMBASE + TCO1_STS, reg16); + reg16 = read_pmbase16(TCO1_STS); + reg16 &= ~DMISCI_STS; + write_pmbase16(TCO1_STS, reg16); - /* clear acpi tco status */ - outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS); - - /* enable acpi tco scis */ - reg16 = inw(DEFAULT_PMBASE + GPE0_EN); - reg16 |= TCOSCI_EN; - outw(DEFAULT_PMBASE + GPE0_EN, reg16); + southbridge_enable_tco_sci(); } static void gma_func0_init(struct device *dev) diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index ac72eba..7d0aec6 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -197,6 +197,20 @@ printk(BIOS_DEBUG, "\n"); } +/* Used by Intel GMA */ +void southbridge_enable_tco_sci(void) +{ + u16 reg16; + + /* clear acpi tco status */ + write_pmbase32(GPE0_STS, TCOSCI_STS); + + /* enable acpi tco scis */ + reg16 = read_pmbase16(GPE0_EN); + reg16 |= TCOSCI_EN; + write_pmbase16(GPE0_EN, reg16); +} + /** * @brief Set the EOS bit */ diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 26134d9..64a30e4 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -110,6 +110,7 @@ void dump_pm1_status(u16 pm1_sts); void dump_tco_status(u32 tco_sts); u32 reset_tco_status(void); +void southbridge_enable_tco_sci(void); void dump_gpe0_status(u64 gpe0_sts); u64 reset_gpe0_status(void); void dump_smi_status(u32 smi_sts); -- To view, visit https://review.coreboot.org/29439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6b5977b10d1e38b45e09530e9dcabbd5f42facb2 Gerrit-Change-Number: 29439 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> [View Less]

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Change in coreboot[master]: mb/google/sarien: Enable WWAN detection
by Duncan Laurie (Code Review) 02 Nov '18

02 Nov '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/29430 ) Change subject: mb/google/sarien: Enable WWAN detection ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/29430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: … [View More]

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Change in coreboot[master]: mb/google/sarien: Enable WWAN detection
by Lijian Zhao (Code Review) 02 Nov '18

02 Nov '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/29430 ) Change subject: mb/google/sarien: Enable WWAN detection ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29430/2/src/mainboard/google/sarien/variant… File src/mainboard/google/sarien/variants/arcada/gpio.c: https://review.coreboot.org/#/c/29430/2/src/mainboard/google/sarien/variant… PS2, Line 237: 0 > Can you add a … [View More]

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Change in coreboot[master]: mb/google/sarien: Enable WWAN detection
by Lijian Zhao (Code Review) 02 Nov '18

02 Nov '18

Hello Duncan Laurie, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29430 to look at the new patch set (#3). Change subject: mb/google/sarien: Enable WWAN detection ...................................................................... mb/google/sarien: Enable WWAN detection WWAN start-up control requires RESET# assert after FULL_CARD_POWER_OFF# set to high more than 10 ms, so force RESET#(GPP_D21) to low at bootblock stage to match … [View More]

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Change in coreboot[master]: mb/google/sarien: Enable WWAN detection
by Duncan Laurie (Code Review) 02 Nov '18

02 Nov '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/29430 ) Change subject: mb/google/sarien: Enable WWAN detection ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29430/2/src/mainboard/google/sarien/variant… File src/mainboard/google/sarien/variants/arcada/gpio.c: https://review.coreboot.org/#/c/29430/2/src/mainboard/google/sarien/variant… PS2, Line 237: 0 Can you add a comment … [View More]

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Change in coreboot[master]: southbridge/amd/pi/hudson: Get rid of void pointer math
by Richard Spiegel (Code Review) 02 Nov '18

02 Nov '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29438 Change subject: southbridge/amd/pi/hudson: Get rid of void pointer math ...................................................................... southbridge/amd/pi/hudson: Get rid of void pointer math Pointer math with void pointers is illegal in many compilers, though it works with GCC because it assumes size of void to be 1. Change the pointers or add parenthesis to force a proper order that will not … [View More]cause compile errors if compiled with a different compiler, and more importantly, don't have unsuspected side effects. BUG=b:118484178 TEST=Build AMD Bettong. Change-Id: I4167c7eeb9339937b064e81e615ceb65f4689082 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/southbridge/amd/pi/hudson/early_setup.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/29438/1 diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 47d20af..eabdfb9 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -292,19 +292,19 @@ void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) { uintptr_t base = hudson_spibase(); - write16((void *)base + SPI100_SPEED_CONFIG, + write16((void *)(base + SPI100_SPEED_CONFIG), (norm << SPI_NORM_SPEED_NEW_SH) | (fast << SPI_FAST_SPEED_NEW_SH) | (alt << SPI_ALT_SPEED_NEW_SH) | (tpm << SPI_TPM_SPEED_NEW_SH)); - write16((void *)base + SPI100_ENABLE, SPI_USE_SPI100); + write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); } void hudson_disable_4dw_burst(void) { uintptr_t base = hudson_spibase(); - write16((void *)base + SPI100_HOST_PREF_CONFIG, - read16((void *)base + SPI100_HOST_PREF_CONFIG) + write16((void *)(base + SPI100_HOST_PREF_CONFIG), + read16((void *)(base + SPI100_HOST_PREF_CONFIG)) & ~SPI_RD4DW_EN_HOST); } @@ -312,7 +312,7 @@ void hudson_set_readspeed(u16 norm, u16 fast) { uintptr_t base = hudson_spibase(); - write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1) + write16((void *)(base + SPI_CNTRL1), (read16((void *)base + SPI_CNTRL1) & ~SPI_CNTRL1_SPEED_MASK) | (norm << SPI_NORM_SPEED_SH) | (fast << SPI_FAST_SPEED_SH)); @@ -321,8 +321,8 @@ void hudson_read_mode(u32 mode) { uintptr_t base = hudson_spibase(); - write32((void *)base + SPI_CNTRL0, - (read32((void *)base + SPI_CNTRL0) + write32((void *)(base + SPI_CNTRL0), + (read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK) | mode); } -- To view, visit https://review.coreboot.org/29438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4167c7eeb9339937b064e81e615ceb65f4689082 Gerrit-Change-Number: 29438 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> [View Less]

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Change in coreboot[master]: LinuxBoot: use curl
by Philipp Deppenwiese (Code Review) 02 Nov '18

02 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29426 ) Change subject: LinuxBoot: use curl ...................................................................... LinuxBoot: use curl Download the linux kernel tarball with curl. Curl is already a dependency for coreboot. Change-Id: I2e0bee3286593bd8e93b4d645242898eb9a14015 Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> Reviewed-on: https://review.coreboot.org/29426 … [View More]

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Change in coreboot[master]: LinuxBoot: use curl
by Philipp Deppenwiese (Code Review) 02 Nov '18

02 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29426 ) Change subject: LinuxBoot: use curl ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/29426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: … [View More]

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Change in coreboot[master]: LinuxBoot/X86_64: Enable 8250 uart drivers
by Philipp Deppenwiese (Code Review) 02 Nov '18

02 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29425 ) Change subject: LinuxBoot/X86_64: Enable 8250 uart drivers ...................................................................... LinuxBoot/X86_64: Enable 8250 uart drivers Enable 8250 uart drivers on default defconfig. - makes it easier to debug. (qemu -nographic) - Kernel size increases only by 20kB. Change-Id: I8309ecf7afd74b3c4021effedcac47350b442173 Signed-off-by: Marcello Sylvester … [View More]

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coreboot-gerrit November 2018