coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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1699 discussions

Change in coreboot[master]: src/soc/intel/braswell/acpi/southcluster.asl: Remove disabled LPE dev...
by Patrick Rudolph (Code Review) 02 Nov '18

02 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29414 ) Change subject: src/soc/intel/braswell/acpi/southcluster.asl: Remove disabled LPE devices ...................................................................... Patch Set 1: I'd prefer runtime detection and ssdt code to achieve the same functionality. -- To view, visit https://review.coreboot.org/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Nov 2018 07:16:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corr...
by Shaunak Saha (Code Review) 02 Nov '18

02 Nov '18

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/29361 ) Change subject: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corruption ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29361/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/memory.c: https://review.coreboot.org/#/c/29361/1/src/mainboard/google/poppy/variants… PS1, Line 36: 30 > That is a question for Intel. I posted this CL per their request in comment #134 on b:111812662. […] We tested this on the failing platform and saw the improvement. We are in process of testing to other working SKU's also. Also we have asked our memory team to let us know if there can be any side effect for this change. Will update the crosbug and the patch with our findings. -- To view, visit https://review.coreboot.org/29361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iefc3957f915a39a47ad6018459e65b70d1b34091 Gerrit-Change-Number: 29361 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Comment-Date: Fri, 02 Nov 2018 04:50:24 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: util/cbsftool: allow enabling verbose make output
by Vadim Bendebury (Code Review) 02 Nov '18

02 Nov '18

Vadim Bendebury has uploaded a new patch set (#2). ( https://review.coreboot.org/29431 ) Change subject: util/cbsftool: allow enabling verbose make output ...................................................................... util/cbsftool: allow enabling verbose make output Sometimes it is necessary to be able to see exact command lines used when compiling and linking. Use the same scheme as some other Makefile's - enable verbose output when variable V is set to 1. TEST=tried building cbfstool with V=1, observed verbose output. Change-Id: Iff25439aabff79e69d1d94a2c51c60bb0e0d7b80 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- M util/cbfstool/Makefile 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/29431/2 -- To view, visit https://review.coreboot.org/29431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iff25439aabff79e69d1d94a2c51c60bb0e0d7b80 Gerrit-Change-Number: 29431 Gerrit-PatchSet: 2 Gerrit-Owner: Vadim Bendebury <vbendeb(a)chromium.org>

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Change in coreboot[master]: util/cbsftool: allow enabling verbose make output
by Vadim Bendebury (Code Review) 02 Nov '18

02 Nov '18

Vadim Bendebury has uploaded this change for review. ( https://review.coreboot.org/29431 Change subject: util/cbsftool: allow enabling verbose make output ...................................................................... util/cbsftool: allow enabling verbose make output Sometimes it is necessary to be able to see exact command lines used when compiling and linking. Use the same scheme as some other Makefile's - enable verbose output when variable V is not empty. TEST=tried building cbfstool with V=1, observed verbose output. Change-Id: Iff25439aabff79e69d1d94a2c51c60bb0e0d7b80 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- M util/cbfstool/Makefile 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/29431/1 diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile index ba8fdff..f4dca3f 100644 --- a/util/cbfstool/Makefile +++ b/util/cbfstool/Makefile @@ -51,6 +51,8 @@ $(INSTALL) ifwitool $(DESTDIR)$(BINDIR) $(INSTALL) cbfs-compression-tool $(DESTDIR)$(BINDIR) +ifneq ($(V),1) .SILENT: +endif include Makefile.inc -- To view, visit https://review.coreboot.org/29431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iff25439aabff79e69d1d94a2c51c60bb0e0d7b80 Gerrit-Change-Number: 29431 Gerrit-PatchSet: 1 Gerrit-Owner: Vadim Bendebury <vbendeb(a)chromium.org>

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Change in coreboot[master]: mb/google/poppy/variants/nami: Enable radium touchscreen support
by Furquan Shaikh (Code Review) 02 Nov '18

02 Nov '18

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/29365 ) Change subject: mb/google/poppy/variants/nami: Enable radium touchscreen support ...................................................................... mb/google/poppy/variants/nami: Enable radium touchscreen support Enable the radium touchscreen support BUG=b:117960394 BRANCH=master TEST= 1. emerge-nami coreboot chromeos-bootimage 2. boot up on ekko DUT to check touchscreen device by evtest /dev/input/event3: Raydium Touchscreen Change-Id: I16167d5d3ce6eac9d64832b52bb1945999a63a90 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29365 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/poppy/variants/nami/devicetree.cb 1 file changed, 17 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Ren Kuo: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index d505099..bd8e4bd 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -317,6 +317,23 @@ register "stop_off_delay_ms" = "2" device i2c 10 on end end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "reset_delay_ms" = "1" + register "reset_off_delay_ms" = "2" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "100" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C3)" + register "stop_delay_ms" = "20" + register "stop_off_delay_ms" = "2" + device i2c 39 on end + end chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" -- To view, visit https://review.coreboot.org/29365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I16167d5d3ce6eac9d64832b52bb1945999a63a90 Gerrit-Change-Number: 29365 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variants/nami: Enable radium touchscreen support
by Ren Kuo (Code Review) 02 Nov '18

02 Nov '18

Ren Kuo has removed YH Lin from this change. ( https://review.coreboot.org/29365 ) Change subject: mb/google/poppy/variants/nami: Enable radium touchscreen support ...................................................................... Removed reviewer YH Lin. -- To view, visit https://review.coreboot.org/29365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: deleteReviewer Gerrit-Change-Id: I16167d5d3ce6eac9d64832b52bb1945999a63a90 Gerrit-Change-Number: 29365 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/sarien: Enable WWAN detection
by Lijian Zhao (Code Review) 02 Nov '18

02 Nov '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/29430 Change subject: mb/google/sarien: Enable WWAN detection ...................................................................... mb/google/sarien: Enable WWAN detection WWAN start-up control requires RESET# assert after FULL_CARD_POWER_OFF# set to high after at least 10 ms, so force RESET#(GPP_D21) to low at bootblock stage to match the sequence. BUG=N/A TEST=Boot up Sarien/Arcada board, check WWAN get detected as USB devices through lsusb. Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/29430/1 diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index 86da3ec..22db02f 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -234,6 +234,7 @@ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 3656afb..e203bcc 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -234,6 +234,7 @@ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ -- To view, visit https://review.coreboot.org/29430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133 Gerrit-Change-Number: 29430 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corr...
by Nick Vaccaro (Code Review) 02 Nov '18

02 Nov '18

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/29361 ) Change subject: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corruption ...................................................................... Patch Set 1: Verification tests underway now. -- To view, visit https://review.coreboot.org/29361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iefc3957f915a39a47ad6018459e65b70d1b34091 Gerrit-Change-Number: 29361 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Nov 2018 23:46:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11
by Nick Vaccaro (Code Review) 02 Nov '18

02 Nov '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/29429 Change subject: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11 ...................................................................... mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11 GPP_C11 was set to DEEP, causing problems with S3. Changed GPP_C11 configuration to use PLTRST instead. BUG=b:114196791 TEST=Build, flash, boot nocturne, log in to kernel and execute the following two commands and verify it passes : echo 0 > /var/lib/power_manager/suspend_to_idle && restart powerd sudo suspend_stress_test -c 2 Change-Id: I008532fce963c51a435378001440ac72b5ebfffc Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/29429/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index 16ff982..9aa7706 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -135,7 +135,7 @@ /* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> FPMCU_INT */ - PAD_CFG_GPI_APIC(GPP_C11, 20K_PU, DEEP), + PAD_CFG_GPI_APIC(GPP_C11, 20K_PU, PLTRST), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */ -- To view, visit https://review.coreboot.org/29429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I008532fce963c51a435378001440ac72b5ebfffc Gerrit-Change-Number: 29429 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

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Change in coreboot[master]: src: Remove asterisks from variable name annotation
by build bot (Jenkins) (Code Review) 01 Nov '18

01 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29235 ) Change subject: src: Remove asterisks from variable name annotation ...................................................................... Patch Set 8: (19 comments) https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h File src/northbridge/amd/amdht/h3finit.h: https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 229: * @param[in,out] u8 LinkWidthIn = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 230: * @param[in,out] u8 LinkWidthOut = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 231: * @param[in,out] u32 FreqCap = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 232: * @param[in,out] u32 FeatureCap = modify to change the link's feature capability line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 269: * @param[in,out] u8 ABLinkWidthLimit = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 270: * @param[in,out] u8 BALinkWidthLimit = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 271: * @param[in,out] u32 PCBFreqCap = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 302: * @param[in,out] u8 DownstreamLinkWidthLimit = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 303: * @param[in,out] u8 UpstreamLinkWidthLimit = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 304: * @param[in,out] u32 PCBFreqCap = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 403: * @param[in,out] u8 LinkWidthIn = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 404: * @param[in,out] u8 LinkWidthOut = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 405: * @param[in,out] u16 LinkFrequency = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 434: * @param[in,out] u8 LinkWidthIn = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 435: * @param[in,out] u8 LinkWidthOut = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 436: * @param[in,out] u16 LinkFrequency = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3finit.h… PS8, Line 462: * @param[in] u8 pEventData0 = useful data associated with the event. line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3ncmn.c File src/northbridge/amd/amdht/h3ncmn.c: https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3ncmn.c@… PS8, Line 1201: * @param[in] targetNode = The node that shall be the recipient of the traffic line over 80 characters https://review.coreboot.org/#/c/29235/8/src/northbridge/amd/amdht/h3ncmn.c@… PS8, Line 1202: * @param[in] targetLink = The link that shall be the recipient of the traffic line over 80 characters -- To view, visit https://review.coreboot.org/29235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I65da8efa9a67b2915fbc0276ce800104198abcee Gerrit-Change-Number: 29235 Gerrit-PatchSet: 8 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Nov 2018 21:11:52 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit November 2018