coreboot-gerrit November 2018

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Change in coreboot[master]: LinuxBoot: X86_64 enable serial console
by Marcello Sylvester Bauer (Code Review) 01 Nov '18

01 Nov '18

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/29425 Change subject: LinuxBoot: X86_64 enable serial console ...................................................................... LinuxBoot: X86_64 enable serial console Enable serial console on default defconfig. - makes it easier to debug. (qemu -nographic) - Kernel size increase only by 20kB. Change-Id: I8309ecf7afd74b3c4021effedcac47350b442173 Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> --- M payloads/external/LinuxBoot/x86_64/defconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/29425/1 diff --git a/payloads/external/LinuxBoot/x86_64/defconfig b/payloads/external/LinuxBoot/x86_64/defconfig index 71c5d77..39ae162 100644 --- a/payloads/external/LinuxBoot/x86_64/defconfig +++ b/payloads/external/LinuxBoot/x86_64/defconfig @@ -99,6 +99,13 @@ CONFIG_MD=y CONFIG_BLK_DEV_DM=y CONFIG_DM_CRYPT=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_EXAR is not set +# CONFIG_SERIAL_8250_LPSS is not set +# CONFIG_SERIAL_8250_MID is not set +# CONFIG_SERIAL_8250_PNP is not set +CONFIG_SERIAL_8250=y CONFIG_HW_RANDOM_TIMERIOMEM=y # CONFIG_HW_RANDOM_AMD is not set # CONFIG_HW_RANDOM_VIA is not set -- To view, visit https://review.coreboot.org/29425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8309ecf7afd74b3c4021effedcac47350b442173 Gerrit-Change-Number: 29425 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com>

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Change in coreboot[master]: LinuxBoot: fix custom defconfig override
by Marcello Sylvester Bauer (Code Review) 01 Nov '18

01 Nov '18

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/29424 Change subject: LinuxBoot: fix custom defconfig override ...................................................................... LinuxBoot: fix custom defconfig override The default ARCH defconfig should not override a custom defconfig. Change-Id: I9de24497ef6296029c66a94124bc11a0bb4d0107 Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> --- M payloads/external/LinuxBoot/Makefile 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/29424/1 diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index c051389..b8e2c51 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -52,8 +52,7 @@ echo " CONFIG Linux $(CONFIG_LINUXBOOT_KERNEL_VERSION)" ifneq ($(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE),) cp $(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) $(kernel_dir)/.config -endif -ifeq ($(CONFIG_LINUXBOOT_ARCH),386) +else ifeq ($(CONFIG_LINUXBOOT_ARCH),386) cp x86/defconfig $(kernel_dir)/.config else ifeq ($(CONFIG_LINUXBOOT_ARCH),amd64) cp x86_64/defconfig $(kernel_dir)/.config -- To view, visit https://review.coreboot.org/29424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9de24497ef6296029c66a94124bc11a0bb4d0107 Gerrit-Change-Number: 29424 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com>

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Change in coreboot[master]: src/soc/intel/braswell/southcluster.c: Configure IO APIC
by build bot (Jenkins) (Code Review) 01 Nov '18

01 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29423 ) Change subject: src/soc/intel/braswell/southcluster.c: Configure IO APIC ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/29423/1/src/soc/intel/braswell/southcluster… File src/soc/intel/braswell/southcluster.c: https://review.coreboot.org/#/c/29423/1/src/soc/intel/braswell/southcluster… PS1, Line 132: for (i=0; i<3; i++) { spaces required around that '=' (ctx:VxV) https://review.coreboot.org/#/c/29423/1/src/soc/intel/braswell/southcluster… PS1, Line 132: for (i=0; i<3; i++) { spaces required around that '<' (ctx:VxV) -- To view, visit https://review.coreboot.org/29423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Gerrit-Change-Number: 29423 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Nov 2018 11:50:50 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/soc/intel/braswell/southcluster.c: Configure IO APIC
by Frans Hendriks (Code Review) 01 Nov '18

01 Nov '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29423 Change subject: src/soc/intel/braswell/southcluster.c: Configure IO APIC ...................................................................... src/soc/intel/braswell/southcluster.c: Configure IO APIC IO APIC is not configured. Add sc_enable_ioapic(). BUG=N/A TEST=Intel CherryHill CRB Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/southcluster.c 1 file changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29423/1 diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index ca87d63..16ef09a 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -18,6 +18,7 @@ #include <arch/io.h> #include <arch/acpi.h> #include <arch/acpigen.h> +#include <arch/ioapic.h> #include <bootstate.h> #include <cbmem.h> #include "chip.h" @@ -72,6 +73,9 @@ add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); + add_mmio_resource(dev, 0xfff, 0xffffffff - CONFIG_CBFS_SIZE + 1, + CONFIG_CBFS_SIZE); /* BIOS ROM */ + add_mmio_resource(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */ } /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ @@ -93,6 +97,49 @@ return 0; } +static void sc_enable_ioapic(struct device *dev) +{ + int i; + u32 reg32; + volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); + volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f); + + /* + * Enable ACPI I/O and power management. + * Set SCI IRQ to IRQ9 + */ + write32(ilb_base + ILB_OIC, 0x100); /* AEN */ + reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */ + write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */ + + *ioapic_index = 0; + *ioapic_data = (1 << 25); + + /* affirm full set of redirection table entries ("write once") */ + *ioapic_index = 1; + reg32 = *ioapic_data; + *ioapic_index = 1; + *ioapic_data = reg32; + + *ioapic_index = 0; + reg32 = *ioapic_data; + printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); + if (reg32 != (1 << 25)) + die("APIC Error\n"); + + printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); + for (i=0; i<3; i++) { + *ioapic_index = i; + printk(BIOS_SPEW, " reg 0x%04x:", i); + reg32 = *ioapic_data; + printk(BIOS_SPEW, " 0x%08x\n", reg32); + } + + *ioapic_index = 3; /* Select Boot Configuration register. */ + *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ +} + /* * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. @@ -168,6 +215,14 @@ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); + + /* IO APIC initialization. */ + sc_enable_ioapic(dev); + /* Set up the PIRQ PIC routing based on static config. */ for (i = 0; i < NUM_PIRQS; i++) write8((void *)(pr_base + i*sizeof(ir->pic[i])), -- To view, visit https://review.coreboot.org/29423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Gerrit-Change-Number: 29423 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: sb/intel/common/pciehp.h: Add missing license header
by Nico Huber (Code Review) 01 Nov '18

01 Nov '18

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/29404 ) Change subject: sb/intel/common/pciehp.h: Add missing license header ...................................................................... sb/intel/common/pciehp.h: Add missing license header Change-Id: Ia669b25683c138d96be00db90d01cf406db4c2eb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/29404 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/common/pciehp.h 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/southbridge/intel/common/pciehp.h b/src/southbridge/intel/common/pciehp.h index 7bf47f3..aa2b444 100644 --- a/src/southbridge/intel/common/pciehp.h +++ b/src/southbridge/intel/common/pciehp.h @@ -1,2 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H +#define SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H + void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number); void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus); + +#endif -- To view, visit https://review.coreboot.org/29404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ia669b25683c138d96be00db90d01cf406db4c2eb Gerrit-Change-Number: 29404 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/common/pciehp.h: Add missing license header
by Nico Huber (Code Review) 01 Nov '18

01 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/29404 ) Change subject: sb/intel/common/pciehp.h: Add missing license header ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/29404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia669b25683c138d96be00db90d01cf406db4c2eb Gerrit-Change-Number: 29404 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Nov 2018 11:26:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src: Add missing include <stdint.h>
by Nico Huber (Code Review) 01 Nov '18

01 Nov '18

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/29403 ) Change subject: src: Add missing include <stdint.h> ...................................................................... src: Add missing include <stdint.h> Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/29403 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/arch/x86/include/arch/registers.h M src/cpu/ti/am335x/uart.h M src/drivers/i2c/max98373/chip.h M src/drivers/i2c/rt5663/chip.h M src/drivers/i2c/w83795/chip.h M src/drivers/intel/fsp2_0/include/fsp/upd.h M src/drivers/net/chip.h M src/drivers/parade/ps8625/ps8625.h M src/drivers/siemens/nc_fpga/nc_fpga.h M src/include/cpu/amd/vr.h M src/include/device/path.h M src/include/swab.h M src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h M src/mainboard/google/urara/urara_boardid.h M src/mainboard/pcengines/apu1/gpio_ftns.h M src/northbridge/intel/e7505/raminit.h M src/northbridge/intel/haswell/pei_data.h M src/northbridge/intel/sandybridge/pei_data.h M src/security/tpm/tss/tcg-1.2/tss_commands.h M src/security/tpm/tss/tcg-1.2/tss_internal.h M src/security/tpm/tss_errors.h M src/soc/broadcom/cygnus/include/soc/tz.h M src/soc/cavium/cn81xx/include/soc/cpu.h M src/soc/cavium/common/include/soc/bootblock.h M src/soc/intel/apollolake/include/soc/usb.h M src/soc/intel/broadwell/chip.h M src/soc/intel/cannonlake/include/soc/ebda.h M src/soc/intel/denverton_ns/chip.h M src/soc/intel/icelake/include/soc/ebda.h M src/soc/intel/quark/include/soc/i2c.h M src/soc/intel/skylake/include/soc/ebda.h M src/soc/nvidia/tegra210/include/soc/flow_ctrl.h M src/soc/qualcomm/ipq806x/include/soc/ebi2.h M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/fsp_bd82x6x/chip.h M src/southbridge/intel/fsp_i89xx/chip.h M src/southbridge/intel/i82801dx/chip.h M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801ix/chip.h M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/lynxpoint/chip.h M src/superio/nuvoton/npcd378/npcd378.h 42 files changed, 90 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h index 08f83ac..1d3b90a 100644 --- a/src/arch/x86/include/arch/registers.h +++ b/src/arch/x86/include/arch/registers.h @@ -17,6 +17,8 @@ #define __ARCH_REGISTERS_H #if !defined(__ASSEMBLER__) +#include <stdint.h> + #define DOWNTO8(A) \ union { \ struct { \ diff --git a/src/cpu/ti/am335x/uart.h b/src/cpu/ti/am335x/uart.h index 000a45d..fe9197f 100644 --- a/src/cpu/ti/am335x/uart.h +++ b/src/cpu/ti/am335x/uart.h @@ -15,6 +15,8 @@ #ifndef AM335X_UART_H #define AM335X_UART_H +#include <stdint.h> + #define AM335X_UART0_BASE 0x44e09000 #define AM335X_UART1_BASE 0x48020000 #define AM335X_UART2_BASE 0x48024000 diff --git a/src/drivers/i2c/max98373/chip.h b/src/drivers/i2c/max98373/chip.h index ad81395..dcaf357 100644 --- a/src/drivers/i2c/max98373/chip.h +++ b/src/drivers/i2c/max98373/chip.h @@ -16,6 +16,9 @@ /* * Maxim MAX98373 audio codec devicetree bindings */ + +#include <stdint.h> + struct drivers_i2c_max98373_config { /* I2C Bus Frequency in Hertz (default 400kHz) */ uint32_t bus_speed; diff --git a/src/drivers/i2c/rt5663/chip.h b/src/drivers/i2c/rt5663/chip.h index 1b367c9..5720b18 100644 --- a/src/drivers/i2c/rt5663/chip.h +++ b/src/drivers/i2c/rt5663/chip.h @@ -16,6 +16,9 @@ /* * Realtek RT5663 audio codec devicetree bindings */ + +#include <stdint.h> + struct drivers_i2c_rt5663_config { /* I2C Bus Frequency in Hertz (default 400kHz) */ unsigned int bus_speed; diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h index b48c523..e3426de 100644 --- a/src/drivers/i2c/w83795/chip.h +++ b/src/drivers/i2c/w83795/chip.h @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <stdint.h> + struct drivers_i2c_w83795_config { uint8_t fanin_ctl1; uint8_t fanin_ctl2; diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h index 15094df..19c5423 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/upd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h @@ -12,6 +12,8 @@ #ifndef _FSP2_0_UPD_H_ #define _FSP2_0_UPD_H_ +#include <stdint.h> + struct FSP_UPD_HEADER { /// /// UPD Region Signature. This signature will be diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h index 383614f..985a85a 100644 --- a/src/drivers/net/chip.h +++ b/src/drivers/net/chip.h @@ -14,6 +14,8 @@ #ifndef __DRIVERS_R8168_CHIP_H__ #define __DRIVERS_R8168_CHIP_H__ +#include <stdint.h> + struct drivers_net_config { uint16_t customized_leds; unsigned wake; /* Wake pin for ACPI _PRW */ diff --git a/src/drivers/parade/ps8625/ps8625.h b/src/drivers/parade/ps8625/ps8625.h index 1fbb01c..a5132f1 100644 --- a/src/drivers/parade/ps8625/ps8625.h +++ b/src/drivers/parade/ps8625/ps8625.h @@ -16,6 +16,8 @@ #ifndef __PS8625_H__ #define __PS8625_H__ +#include <stdint.h> + struct parade_write { uint8_t offset; uint8_t reg; diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.h b/src/drivers/siemens/nc_fpga/nc_fpga.h index fe5f612..f1982d2 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.h +++ b/src/drivers/siemens/nc_fpga/nc_fpga.h @@ -16,6 +16,8 @@ #ifndef _SIEMENS_NC_FPGA_H_ #define _SIEMENS_NC_FPGA_H_ +#include <stdint.h> + #define NC_MAGIC_OFFSET 0x020 #define NC_FPGA_MAGIC 0x4E433746 #define NC_CAP1_OFFSET 0x080 diff --git a/src/include/cpu/amd/vr.h b/src/include/cpu/amd/vr.h index e5ab840..8c62e44 100644 --- a/src/include/cpu/amd/vr.h +++ b/src/include/cpu/amd/vr.h @@ -7,6 +7,8 @@ #ifndef CPU_AMD_VR_H #define CPU_AMD_VR_H +#include <stdint.h> + #define VRC_INDEX 0xAC1C // Index register #define VRC_DATA 0xAC1E // Data register #define VR_UNLOCK 0xFC53 // Virtual register unlock code diff --git a/src/include/device/path.h b/src/include/device/path.h index 0d9c681..6736bed 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -1,6 +1,8 @@ #ifndef DEVICE_PATH_H #define DEVICE_PATH_H +#include <stdint.h> + enum device_path_type { DEVICE_PATH_NONE = 0, DEVICE_PATH_ROOT, diff --git a/src/include/swab.h b/src/include/swab.h index 7d781a0..956cfa5 100644 --- a/src/include/swab.h +++ b/src/include/swab.h @@ -1,6 +1,3 @@ -#ifndef _SWAB_H -#define _SWAB_H - /* * linux/byteorder/swab.h * Byte-swapping, independently from CPU endianness @@ -18,6 +15,12 @@ /* casts are necessary for constants, because we never know how for sure * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. */ + +#ifndef _SWAB_H +#define _SWAB_H + +#include <stdint.h> + #define swab16(x) \ ((unsigned short)( \ (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \ diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index 903ebaa..8f1e24c 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -17,6 +17,8 @@ * Copyed over from qemu soure tree, include/hw/nvram/fw_cfg.h */ +#include <stdint.h> + #define FW_CFG_SIGNATURE 0x00 #define FW_CFG_ID 0x01 #define FW_CFG_UUID 0x02 diff --git a/src/mainboard/google/urara/urara_boardid.h b/src/mainboard/google/urara/urara_boardid.h index 7c7c045..fbd9179 100644 --- a/src/mainboard/google/urara/urara_boardid.h +++ b/src/mainboard/google/urara/urara_boardid.h @@ -16,6 +16,8 @@ #ifndef __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__ #define __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__ +#include <stdint.h> + /* * List of URARA derivatives board ID definitions. They are stored in uint8_t * across the code, using #defines here not to imply any specific size. diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.h b/src/mainboard/pcengines/apu1/gpio_ftns.h index 8eadebd..fce8afe 100644 --- a/src/mainboard/pcengines/apu1/gpio_ftns.h +++ b/src/mainboard/pcengines/apu1/gpio_ftns.h @@ -16,6 +16,8 @@ #ifndef GPIO_FTNS_H #define GPIO_FTNS_H +#include <stdint.h> + uintptr_t find_gpio_base(void); void configure_gpio(uintptr_t base_addr, u32 gpio, u8 iomux_ftn, u8 setting); u8 read_gpio(uintptr_t base_addr, u32 gpio); diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index 1581b82..cdfc92a 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -14,6 +14,8 @@ #ifndef RAMINIT_H #define RAMINIT_H +#include <stdint.h> + #define MAX_DIMM_SOCKETS_PER_CHANNEL 4 #define MAX_NUM_CHANNELS 2 #define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL) diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index 319b9e7..dfc34d8 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -30,6 +30,8 @@ #ifndef PEI_DATA_H #define PEI_DATA_H +#include <stdint.h> + typedef void (*tx_byte_func)(unsigned char byte); #define PEI_VERSION 15 diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 00534ca..0a60707 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -30,6 +30,8 @@ #ifndef PEI_DATA_H #define PEI_DATA_H +#include <stdint.h> + typedef struct { uint16_t mode; // 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto uint16_t hs_port_switch_mask; // 4 bit mask, 1: switchable, 0: not switchable diff --git a/src/security/tpm/tss/tcg-1.2/tss_commands.h b/src/security/tpm/tss/tcg-1.2/tss_commands.h index 9d30bfc..acdc8be 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_commands.h +++ b/src/security/tpm/tss/tcg-1.2/tss_commands.h @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <stdint.h> + const struct s_tpm_extend_cmd{ uint8_t buffer[34]; uint16_t pcrNum; diff --git a/src/security/tpm/tss/tcg-1.2/tss_internal.h b/src/security/tpm/tss/tcg-1.2/tss_internal.h index 01912bb..e999cb9 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_internal.h +++ b/src/security/tpm/tss/tcg-1.2/tss_internal.h @@ -6,6 +6,8 @@ #ifndef TCG_TSS_INTERNAL_H_ #define TCG_TSS_INTERNAL_H_ +#include <stdint.h> + /* * These numbers derive from adding the sizes of command fields as shown in the * TPM commands manual. diff --git a/src/security/tpm/tss_errors.h b/src/security/tpm/tss_errors.h index c80ffa1..316661c 100644 --- a/src/security/tpm/tss_errors.h +++ b/src/security/tpm/tss_errors.h @@ -12,6 +12,8 @@ #ifndef TSS_ERRORS_H_ #define TSS_ERRORS_H_ +#include <stdint.h> + #define TPM_E_BASE 0x0 #define TPM_E_NON_FATAL 0x800 diff --git a/src/soc/broadcom/cygnus/include/soc/tz.h b/src/soc/broadcom/cygnus/include/soc/tz.h index a6777fd..1d5d234 100644 --- a/src/soc/broadcom/cygnus/include/soc/tz.h +++ b/src/soc/broadcom/cygnus/include/soc/tz.h @@ -14,6 +14,8 @@ #ifndef __SOC_BROADCOM_CYGNUS_TZ_H__ #define __SOC_BROADCOM_CYGNUS_TZ_H__ +#include <stdint.h> + #define TZ_STATE_SECURE 0 #define TZ_STATE_NON_SECURE 1 diff --git a/src/soc/cavium/cn81xx/include/soc/cpu.h b/src/soc/cavium/cn81xx/include/soc/cpu.h index b2472d7..1c6a30d 100644 --- a/src/soc/cavium/cn81xx/include/soc/cpu.h +++ b/src/soc/cavium/cn81xx/include/soc/cpu.h @@ -17,6 +17,8 @@ #ifndef __SOC_CAVIUM_CN81XX_CPU_H__ #define __SOC_CAVIUM_CN81XX_CPU_H__ +#include <stdint.h> + /** * Number of the Core on which the program is currently running. * diff --git a/src/soc/cavium/common/include/soc/bootblock.h b/src/soc/cavium/common/include/soc/bootblock.h index 76fd4a15..1df444f 100644 --- a/src/soc/cavium/common/include/soc/bootblock.h +++ b/src/soc/cavium/common/include/soc/bootblock.h @@ -16,6 +16,8 @@ #ifndef SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_ #define SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_ +#include <stdint.h> + void bootblock_mainboard_early_init(void); void bootblock_soc_early_init(void); void bootblock_soc_init(void); diff --git a/src/soc/intel/apollolake/include/soc/usb.h b/src/soc/intel/apollolake/include/soc/usb.h index 7220023..7dd9ec0 100644 --- a/src/soc/intel/apollolake/include/soc/usb.h +++ b/src/soc/intel/apollolake/include/soc/usb.h @@ -18,6 +18,8 @@ #ifndef _SOC_APOLLOLAKE_USB_H_ #define _SOC_APOLLOLAKE_USB_H_ +#include <stdint.h> + #define APOLLOLAKE_USB2_PORT_MAX 8 struct usb2_eye_per_port { diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 46c2c1d..0885c2d 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -17,6 +17,8 @@ #ifndef _SOC_INTEL_BROADWELL_CHIP_H_ #define _SOC_INTEL_BROADWELL_CHIP_H_ +#include <stdint.h> + struct soc_intel_broadwell_config { /* * Interrupt Routing configuration diff --git a/src/soc/intel/cannonlake/include/soc/ebda.h b/src/soc/intel/cannonlake/include/soc/ebda.h index 15a9d28..ad62394 100644 --- a/src/soc/intel/cannonlake/include/soc/ebda.h +++ b/src/soc/intel/cannonlake/include/soc/ebda.h @@ -16,6 +16,8 @@ #ifndef SOC_EBDA_H #define SOC_EBDA_H +#include <stdint.h> + struct ebda_config { uint32_t signature; /* 0x00 - EBDA signature */ uint32_t tolum_base; /* 0x04 - coreboot memory start */ diff --git a/src/soc/intel/denverton_ns/chip.h b/src/soc/intel/denverton_ns/chip.h index bfa6a01..f2a67dd 100644 --- a/src/soc/intel/denverton_ns/chip.h +++ b/src/soc/intel/denverton_ns/chip.h @@ -17,6 +17,8 @@ #ifndef SOC_INTEL_DENVERTON_NS_CHIP_H #define SOC_INTEL_DENVERTON_NS_CHIP_H +#include <stdint.h> + struct soc_intel_denverton_ns_config { /** * Interrupt Routing configuration diff --git a/src/soc/intel/icelake/include/soc/ebda.h b/src/soc/intel/icelake/include/soc/ebda.h index 9c44a50..f4d89e9 100644 --- a/src/soc/intel/icelake/include/soc/ebda.h +++ b/src/soc/intel/icelake/include/soc/ebda.h @@ -16,6 +16,8 @@ #ifndef SOC_EBDA_H #define SOC_EBDA_H +#include <stdint.h> + struct ebda_config { uint32_t signature; /* 0x00 - EBDA signature */ uint32_t tolum_base; /* 0x04 - coreboot memory start */ diff --git a/src/soc/intel/quark/include/soc/i2c.h b/src/soc/intel/quark/include/soc/i2c.h index 85ae7b9..f3c585f 100644 --- a/src/soc/intel/quark/include/soc/i2c.h +++ b/src/soc/intel/quark/include/soc/i2c.h @@ -16,6 +16,8 @@ #ifndef _QUARK_I2C_H_ #define _QUARK_I2C_H_ +#include <stdint.h> + typedef volatile struct _I2C_REGS { volatile uint32_t ic_con; /* 00: Control Register */ volatile uint32_t ic_tar; /* 04: Master Target Address */ diff --git a/src/soc/intel/skylake/include/soc/ebda.h b/src/soc/intel/skylake/include/soc/ebda.h index 15a9d28..ad62394 100644 --- a/src/soc/intel/skylake/include/soc/ebda.h +++ b/src/soc/intel/skylake/include/soc/ebda.h @@ -16,6 +16,8 @@ #ifndef SOC_EBDA_H #define SOC_EBDA_H +#include <stdint.h> + struct ebda_config { uint32_t signature; /* 0x00 - EBDA signature */ uint32_t tolum_base; /* 0x04 - coreboot memory start */ diff --git a/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h b/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h index 2dd1f9f..602c75c 100644 --- a/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h +++ b/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h @@ -16,6 +16,8 @@ #ifndef _TEGRA210_FLOW_CTRL_H_ #define _TEGRA210_FLOW_CTRL_H_ +#include <stdint.h> + void flowctrl_cpu_off(int cpu); void flowctrl_cpu_on(int cpu); void flowctrl_cpu_suspend(int cpu); diff --git a/src/soc/qualcomm/ipq806x/include/soc/ebi2.h b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h index 3e99c3b..5dcd9b8 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/ebi2.h +++ b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h @@ -19,6 +19,8 @@ #ifndef __SOC_QUALCOMM_IPQ806X_EBI2_H_ #define __SOC_QUALCOMM_IPQ806X_EBI2_H_ +#include <stdint.h> + #define EBI2CR_BASE (0x1A600000) struct ebi2cr_regs { diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index ce8a804..29f6881 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H +#include <stdint.h> + struct southbridge_intel_bd82x6x_config { /** * GPI Routing configuration diff --git a/src/southbridge/intel/fsp_bd82x6x/chip.h b/src/southbridge/intel/fsp_bd82x6x/chip.h index 9d6a9e4..8da3936 100644 --- a/src/southbridge/intel/fsp_bd82x6x/chip.h +++ b/src/southbridge/intel/fsp_bd82x6x/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_FSP_BD82X6X_CHIP_H #define SOUTHBRIDGE_INTEL_FSP_BD82X6X_CHIP_H +#include <stdint.h> + struct southbridge_intel_fsp_bd82x6x_config { /** * Interrupt Routing configuration diff --git a/src/southbridge/intel/fsp_i89xx/chip.h b/src/southbridge/intel/fsp_i89xx/chip.h index 69e1dc7..bea3e07 100644 --- a/src/southbridge/intel/fsp_i89xx/chip.h +++ b/src/southbridge/intel/fsp_i89xx/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_I89XX_CHIP_H #define SOUTHBRIDGE_INTEL_I89XX_CHIP_H +#include <stdint.h> + struct southbridge_intel_fsp_i89xx_config { /** * Interrupt Routing configuration diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h index f77413d..a0961ee 100644 --- a/src/southbridge/intel/i82801dx/chip.h +++ b/src/southbridge/intel/i82801dx/chip.h @@ -17,6 +17,8 @@ #ifndef I82801DX_CHIP_H #define I82801DX_CHIP_H +#include <stdint.h> + struct southbridge_intel_i82801dx_config { int enable_usb; int enable_native_ide; diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index e89fcc4..3a20ab1 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H +#include <stdint.h> + struct southbridge_intel_i82801gx_config { /** * Interrupt Routing configuration diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 307b751..0b3e0b5 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -17,6 +17,8 @@ #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H +#include <stdint.h> + enum { THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3, THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7 diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index 533254a..1712b81 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -17,6 +17,8 @@ #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H +#include <stdint.h> + enum { THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3, THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7 diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index d11ce5f..09f1c90 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H #define SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H +#include <stdint.h> + struct southbridge_intel_lynxpoint_config { /** * Interrupt Routing configuration diff --git a/src/superio/nuvoton/npcd378/npcd378.h b/src/superio/nuvoton/npcd378/npcd378.h index 53541a9..cf0b804 100644 --- a/src/superio/nuvoton/npcd378/npcd378.h +++ b/src/superio/nuvoton/npcd378/npcd378.h @@ -17,6 +17,8 @@ #ifndef SUPERIO_NUVOTON_NPCD378_H #define SUPERIO_NUVOTON_NPCD378_H +#include <stdint.h> + /* HWM at LDN8 */ #define NPCD837_HWM_WRITE_LOCK_CTRL 0x4 #define NPCD837_HWM_WRITE_LOCK_BIT 0x1 -- To view, visit https://review.coreboot.org/29403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Gerrit-Change-Number: 29403 Gerrit-PatchSet: 9 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src: Add missing include <stdint.h>
by Nico Huber (Code Review) 01 Nov '18

01 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/29403 ) Change subject: src: Add missing include <stdint.h> ...................................................................... Patch Set 8: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/29403/8/src/soc/cavium/cn81xx/include/soc/c… File src/soc/cavium/cn81xx/include/soc/cpu.h: https://review.coreboot.org/#/c/29403/8/src/soc/cavium/cn81xx/include/soc/c… PS8, Line 27: size_t stddef.h btw. ;) -- To view, visit https://review.coreboot.org/29403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Gerrit-Change-Number: 29403 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Nov 2018 11:25:03 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: src: Add missing include <stdint.h>
by Elyes HAOUAS (Code Review) 01 Nov '18

01 Nov '18

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29403 to look at the new patch set (#8). Change subject: src: Add missing include <stdint.h> ...................................................................... src: Add missing include <stdint.h> Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/include/arch/registers.h M src/cpu/ti/am335x/uart.h M src/drivers/i2c/max98373/chip.h M src/drivers/i2c/rt5663/chip.h M src/drivers/i2c/w83795/chip.h M src/drivers/intel/fsp2_0/include/fsp/upd.h M src/drivers/net/chip.h M src/drivers/parade/ps8625/ps8625.h M src/drivers/siemens/nc_fpga/nc_fpga.h M src/include/cpu/amd/vr.h M src/include/device/path.h M src/include/swab.h M src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h M src/mainboard/google/urara/urara_boardid.h M src/mainboard/pcengines/apu1/gpio_ftns.h M src/northbridge/intel/e7505/raminit.h M src/northbridge/intel/haswell/pei_data.h M src/northbridge/intel/sandybridge/pei_data.h M src/security/tpm/tss/tcg-1.2/tss_commands.h M src/security/tpm/tss/tcg-1.2/tss_internal.h M src/security/tpm/tss_errors.h M src/soc/broadcom/cygnus/include/soc/tz.h M src/soc/cavium/cn81xx/include/soc/cpu.h M src/soc/cavium/common/include/soc/bootblock.h M src/soc/intel/apollolake/include/soc/usb.h M src/soc/intel/broadwell/chip.h M src/soc/intel/cannonlake/include/soc/ebda.h M src/soc/intel/denverton_ns/chip.h M src/soc/intel/icelake/include/soc/ebda.h M src/soc/intel/quark/include/soc/i2c.h M src/soc/intel/skylake/include/soc/ebda.h M src/soc/nvidia/tegra210/include/soc/flow_ctrl.h M src/soc/qualcomm/ipq806x/include/soc/ebi2.h M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/fsp_bd82x6x/chip.h M src/southbridge/intel/fsp_i89xx/chip.h M src/southbridge/intel/i82801dx/chip.h M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801ix/chip.h M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/lynxpoint/chip.h M src/superio/nuvoton/npcd378/npcd378.h 42 files changed, 90 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/29403/8 -- To view, visit https://review.coreboot.org/29403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Gerrit-Change-Number: 29403 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src: Add missing include <stdint.h>
by Elyes HAOUAS (Code Review) 01 Nov '18

01 Nov '18

Elyes HAOUAS has abandoned this change. ( https://review.coreboot.org/29405 ) Change subject: src: Add missing include <stdint.h> ...................................................................... Abandoned merged with Change-Id: Idf10a097457 -- To view, visit https://review.coreboot.org/29405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Iaf0fa38daf858bcd668962f14ffcbaf359113413 Gerrit-Change-Number: 29405 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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