coreboot-gerrit November 2018

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Change in coreboot[master]: soc/intel/icelake: Add PID based on Icelake EDS
by Aamir Bohra (Code Review) 02 Nov '18

02 Nov '18

Hello Subrata Banik, I'd like you to do a code review. Please visit https://review.coreboot.org/29436 to review the following change. Change subject: soc/intel/icelake: Add PID based on Icelake EDS ...................................................................... soc/intel/icelake: Add PID based on Icelake EDS Change-Id: I2d9e06f06a39dc76a3c1351d7976505d7bd92d10 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/include/soc/pcr_ids.h 2 files changed, 15 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/29436/1 diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 2fc94f4..bfdcd7e 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -34,9 +34,7 @@ #include <soc/pm.h> #include <soc/smbus.h> -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP 0x1400 -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H 0x0980 - +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0600 #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8 @@ -56,20 +54,6 @@ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 -static uint32_t get_pmc_reg_base(void) -{ - uint8_t pch_series; - - pch_series = get_pch_series(); - - if (pch_series == PCH_H) - return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H; - else if (pch_series == PCH_LP) - return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP; - else - return 0; -} - static void soc_config_pwrmbase(void) { uint32_t reg32; @@ -113,26 +97,22 @@ static void soc_config_acpibase(void) { uint32_t pmc_reg_value; - uint32_t pmc_base_reg; - pmc_base_reg = get_pmc_reg_base(); - if (!pmc_base_reg) - die("Invalid PMC base address\n"); + pmc_reg_value = pcr_read32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + + PCR_PSFX_TO_SHDW_BAR4); - pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + - PCR_PSFX_TO_SHDW_BAR4); - - if (pmc_reg_value != 0xFFFFFFFF) { + if (pmc_reg_value != 0xFFFFFFFF) + { /* Disable Io Space before changing the address */ - pcr_rmw32(PID_PSF3, pmc_base_reg + + pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + PCR_PSFX_T0_SHDW_PCIEN, ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); /* Program ABASE in PSF3 PMC space BAR4*/ - pcr_write32(PID_PSF3, pmc_base_reg + + pcr_write32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + PCR_PSFX_TO_SHDW_BAR4, ACPI_BASE_ADDRESS); /* Enable IO Space */ - pcr_rmw32(PID_PSF3, pmc_base_reg + + pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + PCR_PSFX_T0_SHDW_PCIEN, ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); } diff --git a/src/soc/intel/icelake/include/soc/pcr_ids.h b/src/soc/intel/icelake/include/soc/pcr_ids.h index b75bf67..a6ad30b 100644 --- a/src/soc/intel/icelake/include/soc/pcr_ids.h +++ b/src/soc/intel/icelake/include/soc/pcr_ids.h @@ -20,11 +20,13 @@ */ #define PID_EMMC 0x52 #define PID_SDX 0x53 -#define PID_GPIOCOM4 0x6a -#define PID_GPIOCOM3 0x6b -#define PID_GPIOCOM2 0x6c -#define PID_GPIOCOM1 0x6d + #define PID_GPIOCOM0 0x6e +#define PID_GPIOCOM1 0x6d +#define PID_GPIOCOM2 0x6c +#define PID_GPIOCOM4 0x6a +#define PID_GPIOCOM5 0x69 + #define PID_DMI 0x88 #define PID_PSTH 0x89 #define PID_CSME0 0x90 @@ -35,7 +37,7 @@ #define PID_PSF4 0xbd #define PID_SCS 0xc0 #define PID_RTC 0xc3 -#define PID_ITSS 0xc2 +#define PID_ITSS 0xc4 #define PID_LPC 0xc7 #define PID_SERIALIO 0xcb -- To view, visit https://review.coreboot.org/29436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2d9e06f06a39dc76a3c1351d7976505d7bd92d10 Gerrit-Change-Number: 29436 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/common: Include Icelake Device Ids
by Aamir Bohra (Code Review) 02 Nov '18

02 Nov '18

Hello Subrata Banik, I'd like you to do a code review. Please visit https://review.coreboot.org/29435 to review the following change. Change subject: soc/intel/common: Include Icelake Device Ids ...................................................................... soc/intel/common: Include Icelake Device Ids Add Icelake specific CPU, System Agent, PCH, IGD device IDs. Change-Id: I2c398957ffbc9bb0e5b363740d99433075ca66a3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/icelake/bootblock/report_platform.c 22 files changed, 165 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/29435/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index f6bcd7c..7908413 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2692,6 +2692,13 @@ #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370 0xa306 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370 0xa30c +#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC 0x3480 +#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0 0x3481 +#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC 0x3482 +#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC 0x3483 +#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC 0x3484 +#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC 0x3487 +#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC 0x3486 /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -2769,6 +2776,22 @@ #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14 0x9db5 #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15 0x9db6 #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16 0x9db7 +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP1 0x34b8 +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP2 0x34b9 +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP3 0x34bA +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP4 0x34bB +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP5 0x34bC +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP6 0x34bD +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP7 0x34bE +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP8 0x34bF +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP9 0x34b0 +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP10 0x34b1 +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP11 0x34b2 +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP12 0x34b3 +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP13 0x34b4 +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP14 0x34b5 +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP15 0x34b6 +#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP16 0x34b7 #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1 0xa338 #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2 0xa339 @@ -2806,6 +2829,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA 0x282a #define PCI_DEVICE_ID_INTEL_CNP_H_SATA 0xa352 #define PCI_DEVICE_ID_INTEL_CNP_LP_SATA 0x9dd3 +#define PCI_DEVICE_ID_INTEL_ICP_U_SATA 0x34d3 /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -2815,6 +2839,7 @@ #define PCI_DEVICE_ID_INTEL_GLK_PMC 0x3194 #define PCI_DEVICE_ID_INTEL_CNL_PMC 0x9da1 #define PCI_DEVICE_ID_INTEL_CNP_H_PMC 0xa321 +#define PCI_DEVICE_ID_INTEL_ICP_PMC 0x34a1 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -2853,6 +2878,12 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_I2C1 0xa369 #define PCI_DEVICE_ID_INTEL_CNP_H_I2C2 0xa36a #define PCI_DEVICE_ID_INTEL_CNP_H_I2C3 0xa36b +#define PCI_DEVICE_ID_INTEL_ICP_I2C0 0x34e8 +#define PCI_DEVICE_ID_INTEL_ICP_I2C1 0x34e9 +#define PCI_DEVICE_ID_INTEL_ICP_I2C2 0x34ea +#define PCI_DEVICE_ID_INTEL_ICP_I2C3 0x34eb +#define PCI_DEVICE_ID_INTEL_ICP_I2C4 0x34c5 +#define PCI_DEVICE_ID_INTEL_ICP_I2C5 0x34c6 /* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 @@ -2878,6 +2909,9 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_UART0 0xa328 #define PCI_DEVICE_ID_INTEL_CNP_H_UART1 0xa329 #define PCI_DEVICE_ID_INTEL_CNP_H_UART2 0xa347 +#define PCI_DEVICE_ID_INTEL_ICP_UART0 0x34a8 +#define PCI_DEVICE_ID_INTEL_ICP_UART1 0x34a9 +#define PCI_DEVICE_ID_INTEL_ICP_UART2 0x34c7 /* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 @@ -2894,6 +2928,10 @@ #define PCI_DEVICE_ID_INTEL_CNL_SPI1 0x9dab #define PCI_DEVICE_ID_INTEL_CNL_SPI2 0x9dfb #define PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI 0x9da4 +#define PCI_DEVICE_ID_INTEL_ICP_SPI0 0x34aa +#define PCI_DEVICE_ID_INTEL_ICP_SPI1 0x34ab +#define PCI_DEVICE_ID_INTEL_ICP_SPI2 0x9dfb +#define PCI_DEVICE_ID_INTEL_ICP_HWSEQ_SPI 0x34a4 /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906 @@ -2925,6 +2963,22 @@ #define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5 #define PCI_DEVICE_ID_INTEL_CFL_H_GT2 0x3e9b #define PCI_DEVICE_ID_INTEL_CFL_S_GT2 0x3e92 +#define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT 0x8A70 +#define PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT 0x8A71 +#define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT 0x8A40 +#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_0 0x8A50 +#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_1 0x8A5D +#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_1 0x8A5B +#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_2 0x8A5C +#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_2 0x8A5A +#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_3 0x8A51 +#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_3 0x8A52 +#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_4 0x8A53 +#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_4 0x8A54 +#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_5 0x8A55 +#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5 0x8A56 +#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_6 0x8A57 +#define PCI_DEVICE_ID_INTEL_ICL_GT3_ULT 0x8A62 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -2947,6 +3001,10 @@ #define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0 #define PCI_DEVICE_ID_INTEL_CFL_ID_H 0x3ec4 #define PCI_DEVICE_ID_INTEL_CFL_ID_S 0x3ec2 +#define PCI_DEVICE_ID_INTEL_ICL_ID_U 0x8A12 +#define PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2 0x8A02 +#define PCI_DEVICE_ID_INTEL_ICL_ID_Y 0x8A10 +#define PCI_DEVICE_ID_INTEL_ICL_ID_Y_2 0x8A00 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 @@ -2954,6 +3012,7 @@ #define PCI_DEVICE_ID_INTEL_KBP_H_SMBUS 0xa1a3 #define PCI_DEVICE_ID_INTEL_CNL_SMBUS 0x9da3 #define PCI_DEVICE_ID_INTEL_CNP_H_SMBUS 0xa323 +#define PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS 0x34a3 /* Intel XHCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 @@ -2963,18 +3022,21 @@ #define PCI_DEVICE_ID_INTEL_KBP_H_XHCI 0xa2af #define PCI_DEVICE_ID_INTEL_CNL_LP_XHCI 0x9ded #define PCI_DEVICE_ID_INTEL_CNP_H_XHCI 0xa36d +#define PCI_DEVICE_ID_INTEL_ICP_LP_XHCI 0x34ed /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 #define PCI_DEVICE_ID_INTEL_GLK_P2SB 0x3192 #define PCI_DEVICE_ID_INTEL_CNL_P2SB 0x9da0 #define PCI_DEVICE_ID_INTEL_CNP_H_P2SB 0xa320 +#define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec #define PCI_DEVICE_ID_INTEL_GLK_SRAM 0x31ec #define PCI_DEVICE_ID_INTEL_CNL_SRAM 0x9def #define PCI_DEVICE_ID_INTEL_CNP_H_SRAM 0xa36f +#define PCI_DEVICE_ID_INTEL_ICL_SRAM 0x34ef /* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 @@ -2983,6 +3045,7 @@ #define PCI_DEVICE_ID_INTEL_SKL_AUDIO 0x9d70 #define PCI_DEVICE_ID_INTEL_KBL_AUDIO 0x9d71 #define PCI_DEVICE_ID_INTEL_CNP_H_AUDIO 0xa348 +#define PCI_DEVICE_ID_INTEL_ICL_AUDIO 0x34c8 /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a @@ -2990,6 +3053,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_CSE0 0x9de0 #define PCI_DEVICE_ID_INTEL_SKL_CSE0 0x9d3a #define PCI_DEVICE_ID_INTEL_CNP_H_CSE0 0xa360 +#define PCI_DEVICE_ID_INTEL_ICL_CSE0 0x34e0 /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -2997,6 +3061,7 @@ #define PCI_DEVICE_ID_INTEL_SPT_LP_XDCI 0x9d30 #define PCI_DEVICE_ID_INTEL_CNL_LP_XDCI 0x9dee #define PCI_DEVICE_ID_INTEL_CNP_H_XDCI 0xa36e +#define PCI_DEVICE_ID_INTEL_ICP_LP_XDCI 0x34ee /* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca @@ -3004,6 +3069,7 @@ #define PCI_DEVICE_ID_INTEL_SKL_SD 0x9d2d #define PCI_DEVICE_ID_INTEL_CNL_SD 0x9df5 #define PCI_DEVICE_ID_INTEL_CNP_H_SD 0xa375 +#define PCI_DEVICE_ID_INTEL_ICL_SD 0x34f8 /* Intel EMMC device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index af49c0a..5f5c8cf 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -73,6 +73,8 @@ { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 }, + { X86_VENDOR_INTEL, CPUID_ICELAKE_A0 }, + { X86_VENDOR_INTEL, CPUID_ICELAKE_B0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 9b8a73f..9c35342 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -519,6 +519,7 @@ PCI_DEVICE_ID_INTEL_CNL_CSE0, PCI_DEVICE_ID_INTEL_SKL_CSE0, PCI_DEVICE_ID_INTEL_CNP_H_CSE0, + PCI_DEVICE_ID_INTEL_ICL_CSE0, 0, }; diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 4bfe96e..65c86cc 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -32,6 +32,7 @@ PCI_DEVICE_ID_INTEL_GLK_AUDIO, PCI_DEVICE_ID_INTEL_SKL_AUDIO, PCI_DEVICE_ID_INTEL_CNP_H_AUDIO, + PCI_DEVICE_ID_INTEL_ICL_AUDIO, 0, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 4382319..19a78e7 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -134,6 +134,22 @@ PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM, PCI_DEVICE_ID_INTEL_CFL_H_GT2, PCI_DEVICE_ID_INTEL_CFL_S_GT2, + PCI_DEVICE_ID_INTEL_ICL_GT0_ULT, + PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT, + PCI_DEVICE_ID_INTEL_ICL_GT1_ULT, + PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_0, + PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_1, + PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_1, + PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_2, + PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_2, + PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_3, + PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_3, + PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_4, + PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_4, + PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_5, + PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5, + PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_6, + PCI_DEVICE_ID_INTEL_ICL_GT3_ULT, 0, }; diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 50f847e..f1b5e05 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -76,6 +76,7 @@ PCI_DEVICE_ID_INTEL_KBL_AUDIO, PCI_DEVICE_ID_INTEL_CNL_AUDIO, PCI_DEVICE_ID_INTEL_CNP_H_AUDIO, + PCI_DEVICE_ID_INTEL_ICL_AUDIO, 0 }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 4b67280..01a9bc3 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -217,6 +217,12 @@ PCI_DEVICE_ID_INTEL_CNP_H_I2C1, PCI_DEVICE_ID_INTEL_CNP_H_I2C2, PCI_DEVICE_ID_INTEL_CNP_H_I2C3, + PCI_DEVICE_ID_INTEL_ICP_I2C0, + PCI_DEVICE_ID_INTEL_ICP_I2C1, + PCI_DEVICE_ID_INTEL_ICP_I2C2, + PCI_DEVICE_ID_INTEL_ICP_I2C3, + PCI_DEVICE_ID_INTEL_ICP_I2C4, + PCI_DEVICE_ID_INTEL_ICP_I2C5, 0, }; diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index c5677e4..b0fd857 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -41,6 +41,8 @@ #define CPUID_COFFEELAKE_D0 0x806ea #define CPUID_COFFEELAKE_U0 0x906ea +#define CPUID_ICELAKE_A0 0x706e0 +#define CPUID_ICELAKE_B0 0x706e1 /* * MP Init callback function to Find CPU Topology. This function is common * among all SOCs and thus its in Common CPU block. diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index bb3b4f2..fa56696 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -146,6 +146,13 @@ PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, + PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, + PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, + PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, + PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, + PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, + PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, + PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, 0 }; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 69e1f97..e93223f 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -167,6 +167,7 @@ PCI_DEVICE_ID_INTEL_GLK_P2SB, PCI_DEVICE_ID_INTEL_CNL_P2SB, PCI_DEVICE_ID_INTEL_CNP_H_P2SB, + PCI_DEVICE_ID_INTEL_ICL_P2SB, 0, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 2ec37e2..3ebb4f6 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -190,6 +190,22 @@ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP22, PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP23, PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP24, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP9, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP10, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP11, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP12, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP13, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP14, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP15, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP16, 0 }; diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 8dca629..e418db0 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -127,6 +127,7 @@ PCI_DEVICE_ID_INTEL_APL_PMC, PCI_DEVICE_ID_INTEL_GLK_PMC, PCI_DEVICE_ID_INTEL_CNP_H_PMC, + PCI_DEVICE_ID_INTEL_ICP_PMC, 0 }; diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index d7c8c00..a600cb9 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -78,6 +78,7 @@ PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA, PCI_DEVICE_ID_INTEL_CNP_H_SATA, PCI_DEVICE_ID_INTEL_CNP_LP_SATA, + PCI_DEVICE_ID_INTEL_ICP_U_SATA, 0 }; diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 81fff29..812146f 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -71,6 +71,7 @@ PCI_DEVICE_ID_INTEL_GLK_SD, PCI_DEVICE_ID_INTEL_SKL_SD, PCI_DEVICE_ID_INTEL_CNP_H_SD, + PCI_DEVICE_ID_INTEL_ICL_SD, 0 }; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 9bb9436..83dfedf 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -92,6 +92,7 @@ PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS, PCI_DEVICE_ID_INTEL_SPT_H_SMBUS, PCI_DEVICE_ID_INTEL_KBP_H_SMBUS, + PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS, 0 }; diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 3a51466..6038f46 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -67,6 +67,10 @@ PCI_DEVICE_ID_INTEL_CNL_SPI1, PCI_DEVICE_ID_INTEL_CNL_SPI2, PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_ICP_SPI0, + PCI_DEVICE_ID_INTEL_ICP_SPI1, + PCI_DEVICE_ID_INTEL_ICP_SPI2, + PCI_DEVICE_ID_INTEL_ICP_HWSEQ_SPI, 0 }; diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index e38d478..507ff58 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -49,6 +49,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_APL_SRAM, PCI_DEVICE_ID_INTEL_GLK_SRAM, + PCI_DEVICE_ID_INTEL_ICL_SRAM, 0, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 62ea122..9608359 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -306,6 +306,10 @@ PCI_DEVICE_ID_INTEL_CFL_ID_U, PCI_DEVICE_ID_INTEL_CFL_ID_H, PCI_DEVICE_ID_INTEL_CFL_ID_S, + PCI_DEVICE_ID_INTEL_ICL_ID_U, + PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2, + PCI_DEVICE_ID_INTEL_ICL_ID_Y, + PCI_DEVICE_ID_INTEL_ICL_ID_Y_2, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 5fb7da6..f7235cf 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -265,6 +265,9 @@ PCI_DEVICE_ID_INTEL_CNP_H_UART0, PCI_DEVICE_ID_INTEL_CNP_H_UART1, PCI_DEVICE_ID_INTEL_CNP_H_UART2, + PCI_DEVICE_ID_INTEL_ICP_UART0, + PCI_DEVICE_ID_INTEL_ICP_UART1, + PCI_DEVICE_ID_INTEL_ICP_UART2, 0, }; diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 47a116e..d2e8769 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -42,6 +42,7 @@ PCI_DEVICE_ID_INTEL_GLK_XDCI, PCI_DEVICE_ID_INTEL_SPT_LP_XDCI, PCI_DEVICE_ID_INTEL_CNP_H_XDCI, + PCI_DEVICE_ID_INTEL_ICP_LP_XDCI, 0 }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index be97aa7..9641177 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -43,6 +43,7 @@ PCI_DEVICE_ID_INTEL_SPT_H_XHCI, PCI_DEVICE_ID_INTEL_KBP_H_XHCI, PCI_DEVICE_ID_INTEL_CNP_H_XHCI, + PCI_DEVICE_ID_INTEL_ICP_LP_XHCI, 0 }; diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index 9df6a1e..0696525 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -38,6 +38,8 @@ { CPUID_COFFEELAKE_D0, "Coffeelake D0" }, { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0"}, { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" }, + { CPUID_ICELAKE_A0, "Icelake A0" }, + { CPUID_ICELAKE_B0, "Icelake B0" }, }; static struct { @@ -51,6 +53,10 @@ { PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)"}, { PCI_DEVICE_ID_INTEL_CFL_ID_H, "Coffeelake-H" }, { PCI_DEVICE_ID_INTEL_CFL_ID_S, "Coffeelake-S" }, + { PCI_DEVICE_ID_INTEL_ICL_ID_U, "Icelake-U" }, + { PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2, "Icelake-U-2-2" }, + { PCI_DEVICE_ID_INTEL_ICL_ID_Y, "Icelake-Y" }, + { PCI_DEVICE_ID_INTEL_ICL_ID_Y_2, "Icelake-Y" }, }; static struct { @@ -62,6 +68,13 @@ { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, "Cannonlake-H Q370" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, "Cannonlake-H QM370" }, + { PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, "Icelake-U Base" }, + { PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, "Icelake-Y Base" }, + { PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, "Icelake-U Premium" }, + { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, "Icelake-U Super" }, + { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, "Icelake-U Super" }, + { PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, "Icelake-Y Super" }, + { PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, "Icelake-Y Premium" }, }; static struct { @@ -80,6 +93,21 @@ { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT1"}, { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake-S GT2" }, + { PCI_DEVICE_ID_INTEL_ICL_GT0_ULT, "Icelake ULT GT0" }, + { PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT, "Icelake ULT GT0.5" }, + { PCI_DEVICE_ID_INTEL_ICL_GT1_ULT, "Icelake U GT1" }, + { PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_0, "Icelake Y GT2" }, + { PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_1, "Icelake Y GT2" }, + { PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_1, "Icelake U GT2" }, + { PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_2, "Icelake Y GT2" }, + { PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_2, "Icelake U GT2" }, + { PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_3, "Icelake Y GT2" }, + { PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_3, "Icelake U GT2" }, + { PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_4, "Icelake Y GT2" }, + { PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_4, "Icelake U GT2" }, + { PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_5, "Icelake Y GT2" }, + { PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5, "Icelake U GT2" }, + { PCI_DEVICE_ID_INTEL_ICL_GT3_ULT, "Icelake U GT3" }, }; static uint8_t get_dev_revision(pci_devfn_t dev) -- To view, visit https://review.coreboot.org/29435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2c398957ffbc9bb0e5b363740d99433075ca66a3 Gerrit-Change-Number: 29435 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code
by Frans Hendriks (Code Review) 02 Nov '18

02 Nov '18

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/29417 ) Change subject: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code ...................................................................... Patch Set 1: > Patch Set 1: > > Please use runtime detection and ssdt code to achieve the same functionality. The standard Intel FSP disables both SPI1 and PWM. All system using this FSP will not have the SPI1 and PWM enabled. Adding runtime detection will take boot time, where the result will be constant on these system. I dont know if Google Cyan use standard FSP binary. If so I suggest removing the SPI1 and PWM ASL code. For Google Cyan the SP1 and PWM ASL code can be added to mainboard directory when required. I suggest to move this code to Google Cyan? -- To view, visit https://review.coreboot.org/29417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606 Gerrit-Change-Number: 29417 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Nov 2018 12:59:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/lenovo/x220: Add x1 as a variant
by Bill XIE (Code Review) 02 Nov '18

02 Nov '18

Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29434 to look at the new patch set (#3). Change subject: mb/lenovo/x220: Add x1 as a variant ...................................................................... mb/lenovo/x220: Add x1 as a variant ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a clone of X220, with additional USB3 controller on pci-e (as i7 variant of x220), and a powered ESATA port wired to ata4 (Linux' annotation). Tested: - CPU i5-2520M - Slotted DIMM 8GiB - Camera - Mini pci-e on wlan slot - Msata on wwan slot - On board SDHCI connected to pci-e - USB3 controller connected to pci-e - NVRAM options for North and South bridges - S3 - TPM1 on LPC - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from SeaBIOS, or Linux payload (Heads) Not tested: - Fingerprint reader on USB2 - Onboard USB2 interfaces (wlan slot, wwan slot) Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Signed-off-by: Bill XIE <persmule(a)gmail.com> --- M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x220/Kconfig.name M src/mainboard/lenovo/x220/Makefile.inc A src/mainboard/lenovo/x220/variants/x1/devicetree.cb A src/mainboard/lenovo/x220/variants/x1/gpio.c R src/mainboard/lenovo/x220/variants/x220/devicetree.cb R src/mainboard/lenovo/x220/variants/x220/gpio.c 7 files changed, 450 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/29434/3 -- To view, visit https://review.coreboot.org/29434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Gerrit-Change-Number: 29434 Gerrit-PatchSet: 3 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mb/lenovo/x220: Add x1 as a variant
by Bill XIE (Code Review) 02 Nov '18

02 Nov '18

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/29434 Change subject: mb/lenovo/x220: Add x1 as a variant ...................................................................... mb/lenovo/x220: Add x1 as a variant ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a clone of X220, with additional USB3 controller on pci-e (as i7 variant of x220, and a powered ESATA port wired to ata4 (Linux' annotation). Tested: - CPU i5-2520M - Slotted DIMM 8GiB - Camera - Mini pci-e on wlan slot - Msata on wwan slot - On board SDHCI connected to pci-e - USB3 controller connected to pci-e - NVRAM options for North and South bridges - S3 - TPM1 on LPC - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from SeaBIOS, or Linux payload (Heads) Not tested: - Fingerprint reader on USB2 - Onboard USB2 interfaces (wlan slot, wwan slot) Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Signed-off-by: Bill XIE <persmule(a)gmail.com> --- M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x220/Kconfig.name M src/mainboard/lenovo/x220/Makefile.inc A src/mainboard/lenovo/x220/variants/x1/devicetree.cb A src/mainboard/lenovo/x220/variants/x1/gpio.c R src/mainboard/lenovo/x220/variants/x220/devicetree.cb R src/mainboard/lenovo/x220/variants/x220/gpio.c 7 files changed, 450 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/29434/1 diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index a710c84..9a18e9b 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I +if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -30,9 +30,22 @@ string default lenovo/x220 +config VARIANT_DIR + string + default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I + default "x1" if BOARD_LENOVO_X1 + + config MAINBOARD_PART_NUMBER string - default "ThinkPad X220" + default "ThinkPad X220" if BOARD_LENOVO_X220 + default "ThinkPad X220i" if BOARD_LENOVO_X220I + default "ThinkPad X1" if BOARD_LENOVO_X1 + +config DEVICETREE + string + default "variants/x220/devicetree.cb" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I + default "variants/x1/devicetree.cb" if BOARD_LENOVO_X1 config MAX_CPUS int @@ -49,6 +62,7 @@ config VGA_BIOS_FILE string default "pci8086,0116.rom" if BOARD_LENOVO_X220I + # FIXME: x1 with i3 cpu may also use "pci8086,0116.rom" default "pci8086,0126.rom" config VGA_BIOS_ID @@ -62,6 +76,11 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex - default 0x21db + default 0x21db if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I + default 0x21e8 if BOARD_LENOVO_X1 -endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I +# Override the default variant behavior, since the data.vbt is the same +config INTEL_GMA_VBT_FILE + default "src/mainboard/$(MAINBOARDDIR)/data.vbt" + +endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 diff --git a/src/mainboard/lenovo/x220/Kconfig.name b/src/mainboard/lenovo/x220/Kconfig.name index 0f9d3fc..988ac4f 100644 --- a/src/mainboard/lenovo/x220/Kconfig.name +++ b/src/mainboard/lenovo/x220/Kconfig.name @@ -3,3 +3,6 @@ config BOARD_LENOVO_X220I bool "ThinkPad X220i" + +config BOARD_LENOVO_X1 + bool "ThinkPad X1" diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index 2dab950..ee968e2 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -14,6 +14,6 @@ ## smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -romstage-y += gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x220/variants/x1/devicetree.cb b/src/mainboard/lenovo/x220/variants/x1/devicetree.cb new file mode 100644 index 0000000..678c6c3 --- /dev/null +++ b/src/mainboard/lenovo/x220/variants/x1/devicetree.cb @@ -0,0 +1,203 @@ +chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + + # Enable DisplayPort Hotplug with 6ms pulse + + register "gpu_dp_b_hotplug" = "0x04" + register "gpu_dp_c_hotplug" = "0x04" + register "gpu_dp_d_hotplug" = "0x04" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "3" + register "gpu_panel_power_up_delay" = "250" # T1+T2: 25ms + register "gpu_panel_power_down_delay" = "250" # T5+T6: 35ms + register "gpu_panel_power_backlight_on_delay" = "2500" # T3: 250ms + register "gpu_panel_power_backlight_off_delay" = "2500" # T4: 250ms + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gpu_cpu_backlight" = "0x1312" + register "gpu_pch_backlight" = "0x13121312" + + device cpu_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + register "pci_mmio_size" = "1024" + + device domain 0 on + device pci 00.0 on + subsystemid 0x17aa 0x21e8 + end # host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on + subsystemid 0x17aa 0x21e8 + end # vga controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "alt_gp_smi_en" = "0x0000" + register "gpi1_routing" = "2" + register "gpi13_routing" = "2" + + # Enable SATA ports 0 (HDD bay) & 2 (msata) & 3 (esatap) + register "sata_port_map" = "0x1d" + # Set max SATA speed to 6.0 Gb/s + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x7c1601" + register "gen2_dec" = "0x0c15e1" + register "gen4_dec" = "0x0c06a1" + + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + + register "c2_latency" = "101" # c2 not supported + register "p_cnt_throttling_supported" = "1" + + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on + subsystemid 0x17aa 0x21ce + end # Intel Gigabit Ethernet + device pci 1a.0 on + subsystemid 0x17aa 0x21e8 + end # USB2 EHCI #2 + device pci 1b.0 on + subsystemid 0x17aa 0x21e8 + end # High Definition Audio + device pci 1c.0 on + subsystemid 0x17aa 0x21e8 + end # PCIe Port #1 + device pci 1c.1 on + subsystemid 0x17aa 0x21e8 + end # PCIe Port #2 (wlan) + device pci 1c.2 on + subsystemid 0x17aa 0x21e8 + end # PCIe Port #3 + device pci 1c.3 on + subsystemid 0x17aa 0x21e8 + end # PCIe Port #4 + device pci 1c.4 on + subsystemid 0x17aa 0x21e8 + chip drivers/ricoh/rce822 # Ricoh cardreader + register "sdwppol" = "1" + register "disable_mask" = "0x87" + device pci 00.0 on + subsystemid 0x17aa 0x21e8 + end + end + end # PCIe Port #5 (SD) + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on + subsystemid 0x17aa 0x21e8 + end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on + subsystemid 0x17aa 0x21e8 + end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on #LPC bridge + subsystemid 0x17aa 0x21e8 + chip ec/lenovo/pmh7 + device pnp ff.1 on # dummy + end + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa6" + register "config1" = "0x01" + register "config2" = "0xe0" + register "config3" = "0xc0" + + register "has_keyboard_backlight" = "0" + + register "beepmask0" = "0xfe" + register "beepmask1" = "0x96" + register "has_power_management_beeps" = "1" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0x3c" + register "event6_enable" = "0x00" + register "event7_enable" = "0x81" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x3d" + + # BDC detection is broken on this board: + # BDC shorts pin14 and pin1 + # BDC's connector pin14 is left floating + # BDC's connector pin1 is routed to SB GPIO 54 + register "has_bdc_detection" = "0" + + register "has_wwan_detection" = "1" + register "wwan_gpio_num" = "70" + register "wwan_gpio_lvl" = "0" + end + end # LPC bridge + device pci 1f.2 on + subsystemid 0x17aa 0x21e8 + end # SATA Controller 1 + device pci 1f.3 on + subsystemid 0x17aa 0x21e8 + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on + subsystemid 0x17aa 0x21e8 + end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/x220/variants/x1/gpio.c b/src/mainboard/lenovo/x220/variants/x1/gpio.c new file mode 100644 index 0000000..e10bb1b --- /dev/null +++ b/src/mainboard/lenovo/x220/variants/x1/gpio.c @@ -0,0 +1,220 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/variants/x220/devicetree.cb similarity index 100% rename from src/mainboard/lenovo/x220/devicetree.cb rename to src/mainboard/lenovo/x220/variants/x220/devicetree.cb diff --git a/src/mainboard/lenovo/x220/gpio.c b/src/mainboard/lenovo/x220/variants/x220/gpio.c similarity index 100% rename from src/mainboard/lenovo/x220/gpio.c rename to src/mainboard/lenovo/x220/variants/x220/gpio.c -- To view, visit https://review.coreboot.org/29434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Gerrit-Change-Number: 29434 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)gmail.com>

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Change in coreboot[master]: soc/intel/skylake: Add FSP CAR support for kabylake
by PraveenX Hodagatta Pranesh (Code Review) 02 Nov '18

02 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29433 to look at the new patch set (#2). Change subject: soc/intel/skylake: Add FSP CAR support for kabylake ...................................................................... soc/intel/skylake: Add FSP CAR support for kabylake Kabylake RVP11 uses FSPT to support Intel security features like bootguard verify boot and measured boot. This patch add FSP CAR support for kabylake by programming tempraminit parameters in fspcar.c and also add FSP_T_XIP default if FSP_CAR is selected in order to relocate FSPT binary while adding it in CBFS so that it can be executed in place. BUG=None TEST=Build and Boot to UEFI payload on kabylake RVP11 board and verified for successful FSP CAR setup. Change-Id: Id180ff9191d734c581ba7bf3879eaa730a799b52 Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc A src/soc/intel/skylake/fspcar.c 3 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/29433/2 -- To view, visit https://review.coreboot.org/29433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id180ff9191d734c581ba7bf3879eaa730a799b52 Gerrit-Change-Number: 29433 Gerrit-PatchSet: 2 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: soc/intel/skylake: Add FSP CAR support for kabylake
by PraveenX Hodagatta Pranesh (Code Review) 02 Nov '18

02 Nov '18

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/29433 Change subject: soc/intel/skylake: Add FSP CAR support for kabylake ...................................................................... soc/intel/skylake: Add FSP CAR support for kabylake Kabylake RVP11 uses FSPT to support Intel security features like bootguard verify boot and measured boot. This patch add FSP CAR support for kabylake by programming tempraminit parameters in bootblock.c and also add FSP_T_XIP default if FSP_CAR is selected in order to relocate FSPT binary while adding it in CBFS so that it can be executed in place. BUG=None TEST=Build and Boot to UEFI payload on kabylake RVP11 board and verified for successful FSP CAR setup. Change-Id: Id180ff9191d734c581ba7bf3879eaa730a799b52 Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/bootblock/bootblock.c 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/29433/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 1449d3d..2db8217 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -77,6 +77,7 @@ select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC + select FSP_T_XIP if FSP_CAR config CPU_INTEL_NUM_FIT_ENTRIES int diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index a2bcaaf..309cf35 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -18,6 +18,24 @@ #include <intelblocks/gspi.h> #include <intelblocks/uart.h> #include <soc/bootblock.h> +#include <FsptUpd.h> + +const FSPT_UPD temp_ram_init_params = { + .FspUpdHeader = { + .Signature = 0x545F4450554C424B, /* 'KBLUPD_T' */ + .Revision = 1, + .Reserved = {0}, + }, + .FsptCoreUpd = { + .MicrocodeRegionBase = + (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC, + .MicrocodeRegionSize = + (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN, + .CodeRegionBase = + (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), + .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, + }, +}; asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { -- To view, visit https://review.coreboot.org/29433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id180ff9191d734c581ba7bf3879eaa730a799b52 Gerrit-Change-Number: 29433 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Add HM175 SKL PCH-H SKU device id
by PraveenX Hodagatta Pranesh (Code Review) 02 Nov '18

02 Nov '18

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/29432 Change subject: soc/intel/skylake: Add HM175 SKL PCH-H SKU device id ...................................................................... soc/intel/skylake: Add HM175 SKL PCH-H SKU device id This patch also add PCH device id in platform reporting. BUG=None TEST=Booted kabylake RVP11 with HM175 SKL PCH-H and verified the device id in serial logs. Change-Id: I8c04bf8d9c27caad800427a5c29da869da1d445d Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/skylake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/29432/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index f6bcd7c..9abf2ba 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2673,6 +2673,7 @@ #define PCI_DEVICE_ID_INTEL_SPT_H_C236 0xa150 #define PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM 0xa14e #define PCI_DEVICE_ID_INTEL_SPT_H_QM170 0xa14d +#define PCI_DEVICE_ID_INTEL_SPT_H_HM175 0xa152 #define PCI_DEVICE_ID_INTEL_KBP_H_H270 0xa2c4 #define PCI_DEVICE_ID_INTEL_KBP_H_Z270 0xa2c5 #define PCI_DEVICE_ID_INTEL_KBP_H_Q270 0xa2c6 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index bb3b4f2..039b6e3 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -127,6 +127,7 @@ PCI_DEVICE_ID_INTEL_SPT_H_C236, PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM, PCI_DEVICE_ID_INTEL_SPT_H_QM170, + PCI_DEVICE_ID_INTEL_SPT_H_HM175, PCI_DEVICE_ID_INTEL_KBP_H_Q270, PCI_DEVICE_ID_INTEL_KBP_H_H270, PCI_DEVICE_ID_INTEL_KBP_H_Z270, diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index b59d351..b9bc733 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -71,6 +71,7 @@ { PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM, "Skylake PCH-H Premium" }, { PCI_DEVICE_ID_INTEL_SPT_H_C236, "Skylake PCH-H C236" }, { PCI_DEVICE_ID_INTEL_SPT_H_QM170, "Skylake PCH-H QM170" }, + { PCI_DEVICE_ID_INTEL_SPT_H_HM175, "Skylake PCH-H HM175" }, { PCI_DEVICE_ID_INTEL_KBP_H_Q270, "Kabylake-H Q270" }, { PCI_DEVICE_ID_INTEL_KBP_H_H270, "Kabylake-H H270" }, { PCI_DEVICE_ID_INTEL_KBP_H_Z270, "Kabylake-H Z270" }, -- To view, visit https://review.coreboot.org/29432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8c04bf8d9c27caad800427a5c29da869da1d445d Gerrit-Change-Number: 29432 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com>

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Change in coreboot[master]: src/soc/intel/braswell/southcluster.c: Configure IO APIC
by Patrick Rudolph (Code Review) 02 Nov '18

02 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29423 ) Change subject: src/soc/intel/braswell/southcluster.c: Configure IO APIC ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/29423/3/src/soc/intel/braswell/southcluster… File src/soc/intel/braswell/southcluster.c: https://review.coreboot.org/#/c/29423/3/src/soc/intel/braswell/southcluster… PS3, Line 76: CONFIG_CBFS_SIZE That's only correct if vboot is disabled. You need to use the whole bios region. Is it required for proper operation ? https://review.coreboot.org/#/c/29423/3/src/soc/intel/braswell/southcluster… PS3, Line 104: )(IO_APIC_ADDR) Adding a macro to access IO_APIC (like the RCBA macro) would make the code more readable. -- To view, visit https://review.coreboot.org/29423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Gerrit-Change-Number: 29423 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Nov 2018 07:22:40 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code
by Patrick Rudolph (Code Review) 02 Nov '18

02 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29417 ) Change subject: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code ...................................................................... Patch Set 1: Please use runtime detection and ssdt code to achieve the same functionality. -- To view, visit https://review.coreboot.org/29417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606 Gerrit-Change-Number: 29417 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Nov 2018 07:17:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit November 2018