coreboot-gerrit November 2018

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Change in coreboot[master]: mediatek/mt8183: Add MT6358 PMIC support
by Tristan Hsieh (Code Review) 01 Nov '18

01 Nov '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/29422 Change subject: mediatek/mt8183: Add MT6358 PMIC support ...................................................................... mediatek/mt8183: Add MT6358 PMIC support BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic247faf73517f6512f9c9a69ba0254c749d68d4c Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/include/soc/mt6358.h A src/soc/mediatek/mt8183/mt6358.c M src/soc/mediatek/mt8183/soc.c 4 files changed, 444 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/29422/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index e8efe90..d79b487 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -34,7 +34,7 @@ ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c -ramstage-y += ../common/pmic_wrap.c pmic_wrap.c +ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h new file mode 100644 index 0000000..c23ee38 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MT6358_H__ +#define __SOC_MEDIATEK_MT6358_H__ + +enum { + PMIC_SWCID = 0x000A, + PMIC_VM_MODE = 0x004e, + PMIC_TOP_RST_MISC = 0x014C, + PMIC_TOP_RST_MISC_SET = 0x014E, + PMIC_TOP_RST_MISC_CLR = 0x0150, + PMIC_TOP_TMA_KEY = 0x03A8, + PMIC_PWRHOLD = 0x0A08, + PMIC_CPSDSA4 = 0x0A2E, + PMIC_VDRAM1_VOSEL_SLEEP = 0x160a, + PMIC_SMPS_ANA_CON0 = 0x1808, +}; + +struct pmic_setting { + unsigned short addr; + unsigned short val; + unsigned short mask; + unsigned char shift; +}; + +void mt6358_init(void); +u16 pmic_read_interface(u16 reg, u16 mask, u16 shift); +void pmic_config_interface(u16 reg, u16 val, u16 mask, u16 shift); +void pmic_set_power_hold(bool enable); +#endif /* __SOC_MEDIATEK_MT6358_H__ */ diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c new file mode 100644 index 0000000..3c2effd --- /dev/null +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -0,0 +1,398 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <soc/pmic_wrap.h> +#include <soc/mt6358.h> + +static struct pmic_setting init_setting[] = { + {0x03A8, 0x9CA7, 0xFFFF, 0}, + {0x1E, 0xA, 0xA, 0}, + {0x22, 0x1F00, 0x1F00, 0}, + {0x2E, 0x1, 0x1, 0}, + {0x30, 0x1, 0x1, 0}, + {0x36, 0x8888, 0xFFFF, 0}, + {0x3A, 0x8888, 0xFFFF, 0}, + {0x3C, 0x8888, 0xFFFF, 0}, + {0x3E, 0x888, 0xFFF, 0}, + {0x94, 0x0, 0xFFFF, 0}, + {0x10C, 0x18, 0x18, 0}, + {0x112, 0x4, 0x4, 0}, + {0x118, 0x8, 0x8, 0}, + {0x12A, 0x100, 0x180, 0}, + {0x134, 0x80, 0x2890, 0}, + {0x14C, 0x20, 0x20, 0}, + {0x198, 0x0, 0x1FF, 0}, + {0x790, 0x280, 0x780, 0}, + {0x7AC, 0x0, 0x2000, 0}, + {0x98A, 0x40, 0x40, 0}, + {0xA08, 0x1, 0x1, 0}, + {0xA38, 0x0, 0x100, 0}, + {0xA3C, 0x81E0, 0x81E0, 0}, + {0xA44, 0xFFFF, 0xFFFF, 0}, + {0xA46, 0xE000, 0xE000, 0}, + {0xA62, 0x400, 0x400, 0}, + {0xC8A, 0x4, 0xC, 0}, + {0xF8C, 0xAAA, 0xAAA, 0}, + {0x1188, 0x0, 0x8000, 0}, + {0x119E, 0x6000, 0x7000, 0}, + {0x11A2, 0x0, 0x3000, 0}, + {0x11B0, 0x4000, 0x4000, 0}, + {0x11B4, 0x0, 0x100, 0}, + {0x123A, 0x8040, 0x83FF, 0}, + {0x123E, 0x4, 0x4, 0}, + {0x1242, 0x1, 0x1, 0}, + {0x1260, 0x0, 0x154, 0}, + {0x1312, 0x8, 0x8, 0}, + {0x1334, 0x0, 0x100, 0}, + {0x1346, 0x100, 0x100, 0}, + {0x138A, 0x10, 0x7F, 0}, + {0x138C, 0x15, 0x7F, 0}, + {0x138E, 0x1030, 0x3030, 0}, + {0x140A, 0x10, 0x7F, 0}, + {0x140C, 0x15, 0x7F, 0}, + {0x140E, 0x1030, 0x3030, 0}, + {0x148A, 0x10, 0x7F, 0}, + {0x148E, 0x1030, 0x3030, 0}, + {0x14A2, 0x20, 0x20, 0}, + {0x150A, 0x10, 0x7F, 0}, + {0x150E, 0x1030, 0x3030, 0}, + {0x158A, 0x8, 0x7F, 0}, + {0x158C, 0x90C, 0x7F7F, 0}, + {0x158E, 0x1030, 0x3030, 0}, + {0x159C, 0x8, 0xC, 0}, + {0x15A2, 0x20, 0x20, 0}, + {0x168A, 0x50, 0x7F, 0}, + {0x168C, 0x1964, 0x7F7F, 0}, + {0x168E, 0x2020, 0x3030, 0}, + {0x16A2, 0x20, 0x20, 0}, + {0x16AA, 0x48, 0x7F, 0}, + {0x170C, 0x1964, 0x7F7F, 0}, + {0x170E, 0x2020, 0x3030, 0}, + {0x172A, 0x3C, 0x7F, 0}, + {0x178C, 0x202, 0x7F7F, 0}, + {0x178E, 0x70, 0x73, 0}, + {0x1790, 0xC, 0xC, 0}, + {0x1798, 0x2810, 0x3F3F, 0}, + {0x179A, 0x800, 0x3F00, 0}, + {0x179E, 0x1, 0x1, 0}, + {0x1808, 0x2000, 0x3000, 0}, + {0x180C, 0x60, 0x60, 0}, + {0x1814, 0x3FF0, 0x7FFF, 0}, + {0x1816, 0x3, 0x7, 0}, + {0x181A, 0x6081, 0xFFBF, 0}, + {0x181C, 0x503, 0x787, 0}, + {0x181E, 0xA662, 0xFFFF, 0}, + {0x1820, 0xA662, 0xFFFF, 0}, + {0x1824, 0xDB6, 0xFFF, 0}, + {0x1828, 0x160, 0x160, 0}, + {0x1830, 0x3FF0, 0x7FFF, 0}, + {0x1832, 0x3, 0x7, 0}, + {0x1836, 0x6081, 0xFFBF, 0}, + {0x1838, 0x503, 0x787, 0}, + {0x183A, 0xA262, 0xFFFF, 0}, + {0x183C, 0xA262, 0xFFFF, 0}, + {0x1840, 0xDB6, 0xFFF, 0}, + {0x1854, 0x0, 0x7, 0}, + {0x1856, 0x0, 0x1C00, 0}, + {0x185C, 0x0, 0x7, 0}, + {0x185E, 0x0, 0x1C00, 0}, + {0x1888, 0x420, 0xE7C, 0}, + {0x188A, 0x801, 0x3C07, 0}, + {0x188C, 0x1F, 0x3F, 0}, + {0x188E, 0x129A, 0xFFFF, 0}, + {0x1894, 0x58, 0x1F8, 0}, + {0x1896, 0x1C, 0x7C, 0}, + {0x1898, 0x1805, 0x3C07, 0}, + {0x189A, 0xF, 0xF, 0}, + {0x189C, 0x221A, 0xFFFF, 0}, + {0x18A0, 0x2E, 0x3F, 0}, + {0x18A2, 0x0, 0x40, 0}, + {0x18A4, 0x2C06, 0x3C07, 0}, + {0x18A6, 0xF, 0xF, 0}, + {0x18A8, 0x221A, 0xFFFF, 0}, + {0x18AC, 0x2E, 0x3F, 0}, + {0x18AE, 0x0, 0x40, 0}, + {0x18B0, 0x1805, 0x3C07, 0}, + {0x18B2, 0xF, 0xF, 0}, + {0x18B4, 0x221A, 0xFFFF, 0}, + {0x18B8, 0x2E, 0x3F, 0}, + {0x18BC, 0x50, 0x4F0, 0}, + {0x18BE, 0x3C, 0xFC, 0}, + {0x18C0, 0x0, 0x300, 0}, + {0x18C2, 0x8886, 0xFFFF, 0}, + {0x18D8, 0x700, 0xF00, 0}, + {0x1A0E, 0x3, 0x3, 0}, + {0x1A10, 0x1, 0x1, 0}, + {0x1A12, 0x0, 0x1, 0}, + {0x1A14, 0x0, 0x1, 0}, + {0x1A16, 0x0, 0x1, 0}, + {0x1A18, 0x0, 0x1, 0}, + {0x1A1A, 0x0, 0x1, 0}, + {0x1A1C, 0x0, 0x1, 0}, + {0x1A1E, 0x0, 0x1, 0}, + {0x1A20, 0x0, 0x1, 0}, + {0x1A22, 0x0, 0x1, 0}, + {0x1A24, 0x0, 0x1, 0}, + {0x1A26, 0x0, 0x1, 0}, + {0x1A28, 0x0, 0x1, 0}, + {0x1A2A, 0x0, 0x1, 0}, + {0x1A2C, 0x0, 0x1, 0}, + {0x1A2E, 0x0, 0x1, 0}, + {0x1A30, 0x0, 0x1, 0}, + {0x1A32, 0x0, 0x1, 0}, + {0x1A34, 0x0, 0x1, 0}, + {0x1A36, 0x0, 0x1, 0}, + {0x1A38, 0x0, 0x1, 0}, + {0x1A3A, 0x0, 0x1, 0}, + {0x1A3C, 0x0, 0x1, 0}, + {0x1A3E, 0x0, 0x1, 0}, + {0x1A40, 0x0, 0x1, 0}, + {0x1A42, 0x0, 0x1, 0}, + {0x1A44, 0x0, 0x1, 0}, + {0x1A46, 0x0, 0x1, 0}, + {0x1A48, 0x0, 0x1, 0}, + {0x1A4A, 0x0, 0x1, 0}, + {0x1A4C, 0x0, 0x1, 0}, + {0x1A4E, 0x0, 0x1, 0}, + {0x1B48, 0x10, 0x7F, 0}, + {0x1B4A, 0xF15, 0x7F7F, 0}, + {0x1B8A, 0x10, 0x7F, 0}, + {0x1B8C, 0xF15, 0x7F7F, 0}, + {0x1BA8, 0x38, 0x7F, 0}, + {0x1BAA, 0x70F, 0x7F7F, 0}, + {0x1BAC, 0x0, 0x3, 0}, + {0x1BCA, 0x10, 0x7F, 0}, + {0x1BCC, 0x70F, 0x7F7F, 0}, + {0x1EA2, 0x1B, 0x1F, 0}, + {0x1EA4, 0xC00, 0x1C00, 0}, + {0x1EA6, 0xC00, 0x1C00, 0}, + {0x1EA8, 0xC00, 0x1C00, 0}, + {0x03A8, 0x0, 0xFFFF, 0}, + + /* MT6358 HW tracking init */ + {0x1B66, 0x1000, 0x7F7F, 0}, + {0x1B68, 0x6340, 0x7F7F, 0}, + {0x1B64, 0x6, 0x6, 0}, + {0x1B6E, 0x1000, 0x7F7F, 0}, + {0x1B70, 0x6340, 0x7F7F, 0}, + {0x1B6C, 0x6, 0x6, 0}, +}; + +static struct pmic_setting lp_setting[] = { + /* Suspend */ + {0x1390, 0x1, 0x1, 0}, + {0x1490, 0x1, 0x1, 0}, + {0x1510, 0x1, 0x1, 0}, + {0x1590, 0x1, 0x1, 0}, + {0x1690, 0x1, 0x1, 0}, + {0x1710, 0x1, 0x1, 1}, + {0x1716, 0x1, 0x1, 1}, + {0x1610, 0x1, 0x1, 1}, + {0x1616, 0x1, 0x1, 1}, + {0x1410, 0x1, 0x1, 0}, + {0x1BD0, 0x1, 0x1, 0}, + {0x1BAE, 0x1, 0x1, 1}, + {0x1BB4, 0x1, 0x1, 1}, + {0x1B4E, 0x1, 0x1, 0}, + {0x1A8A, 0x1, 0x1, 1}, + {0x1A90, 0x1, 0x1, 1}, + {0x1C1E, 0x1, 0x1, 2}, + {0x1C24, 0x0, 0x1, 2}, + {0x1C32, 0x1, 0x1, 2}, + {0x1C38, 0x0, 0x1, 2}, + {0x1C46, 0x1, 0x1, 0}, + {0x1D1E, 0x1, 0x1, 0}, + {0x1D1E, 0x1, 0x1, 0}, + {0x1D8A, 0x1, 0x1, 0}, + {0x1C5A, 0x1, 0x1, 0}, + {0x1C6E, 0x1, 0x1, 0}, + {0x1C9E, 0x1, 0x1, 0}, + {0x1C8A, 0x1, 0x1, 0}, + {0x1B90, 0x1, 0x1, 0}, + {0x1CB2, 0x1, 0x1, 0}, + {0x1D34, 0x1, 0x1, 0}, + {0x1D34, 0x1, 0x1, 0}, + {0x1A9E, 0x1, 0x1, 1}, + {0x1AA4, 0x1, 0x1, 1}, + {0x1AB2, 0x1, 0x1, 1}, + {0x1AB8, 0x1, 0x1, 1}, + {0x1AC6, 0x1, 0x1, 1}, + {0x1ACC, 0x1, 0x1, 1}, + {0x1ADA, 0x1, 0x1, 0}, + {0x1AEE, 0x1, 0x1, 0}, + {0x1C0A, 0x1, 0x1, 2}, + {0x1C10, 0x0, 0x1, 2}, + {0x1B0A, 0x1, 0x1, 1}, + {0x1B10, 0x1, 0x1, 1}, + {0x1CC6, 0x1, 0x1, 0}, + {0x1CDA, 0x1, 0x1, 0}, + {0x1B1E, 0x1, 0x1, 0}, + {0x1D4A, 0x1, 0x1, 0}, + {0x1D5E, 0x1, 0x1, 0}, + {0x1D0A, 0x1, 0x1, 0}, + {0x1B32, 0x1, 0x1, 1}, + {0x1B38, 0x1, 0x1, 1}, + {0x1B32, 0x1, 0x1, 1}, + {0x1B38, 0x1, 0x1, 1}, + {0x1DA0, 0x1, 0x1, 1}, + {0x1DA6, 0x0, 0x1, 1}, + + /* Deep idle setting */ + {0x1390, 0x1, 0x1, 0}, + {0x1490, 0x1, 0x1, 0}, + {0x1510, 0x1, 0x1, 0}, + {0x1590, 0x1, 0x1, 0}, + {0x1690, 0x1, 0x1, 0}, + {0x1710, 0x1, 0x1, 3}, + {0x1716, 0x1, 0x1, 3}, + {0x1610, 0x1, 0x1, 3}, + {0x1616, 0x1, 0x1, 3}, + {0x1410, 0x1, 0x1, 0}, + {0x1BD0, 0x1, 0x1, 0}, + {0x1BAE, 0x1, 0x1, 3}, + {0x1BB4, 0x1, 0x1, 3}, + {0x1B4E, 0x1, 0x1, 0}, + {0x1A8A, 0x1, 0x1, 3}, + {0x1A90, 0x1, 0x1, 3}, + {0x1C1E, 0x1, 0x1, 2}, + {0x1C24, 0x0, 0x1, 2}, + {0x1C32, 0x1, 0x1, 2}, + {0x1C38, 0x0, 0x1, 2}, + {0x1C46, 0x1, 0x1, 0}, + {0x1D1E, 0x1, 0x1, 0}, + {0x1D1E, 0x1, 0x1, 0}, + {0x1D8A, 0x1, 0x1, 0}, + {0x1C5A, 0x1, 0x1, 0}, + {0x1C6E, 0x1, 0x1, 0}, + {0x1C9E, 0x1, 0x1, 0}, + {0x1C8A, 0x1, 0x1, 0}, + {0x1B90, 0x1, 0x1, 0}, + {0x1CB2, 0x1, 0x1, 0}, + {0x1D34, 0x1, 0x1, 0}, + {0x1D34, 0x1, 0x1, 0}, + {0x1A9E, 0x1, 0x1, 3}, + {0x1AA4, 0x1, 0x1, 3}, + {0x1AB2, 0x1, 0x1, 3}, + {0x1AB8, 0x1, 0x1, 3}, + {0x1AC6, 0x1, 0x1, 0}, + {0x1ADA, 0x1, 0x1, 0}, + {0x1AEE, 0x1, 0x1, 0}, + {0x1C0A, 0x1, 0x1, 2}, + {0x1C10, 0x0, 0x1, 2}, + {0x1B0A, 0x1, 0x1, 3}, + {0x1B10, 0x1, 0x1, 3}, + {0x1CC6, 0x1, 0x1, 0}, + {0x1CDA, 0x1, 0x1, 0}, + {0x1B1E, 0x1, 0x1, 0}, + {0x1D4A, 0x1, 0x1, 0}, + {0x1D5E, 0x1, 0x1, 0}, + {0x1D0A, 0x1, 0x1, 0}, + {0x1B32, 0x1, 0x1, 3}, + {0x1B38, 0x1, 0x1, 3}, + {0x1B32, 0x1, 0x1, 3}, + {0x1B38, 0x1, 0x1, 3}, + {0x1DA0, 0x1, 0x1, 3}, + {0x1DA6, 0x0, 0x1, 3}, +}; + +u16 pmic_read_interface(u16 reg, u16 mask, u16 shift) +{ + u16 rdata; + + pwrap_read(reg, &rdata); + rdata &= (mask << shift); + rdata = (rdata >> shift); + + return rdata; +} + +void pmic_config_interface(u16 reg, u16 val, u16 mask, u16 shift) +{ + u16 old, new; + + pwrap_read(reg, &old); + + new = old & ~(mask << shift); + new |= (val << shift); + pwrap_write(reg, new); +} + +void pmic_set_power_hold(bool enable) +{ + pmic_config_interface(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0); +} + +static void pmic_wdt_set(void) +{ + /* [5]=1, RG_WDTRSTB_DEB */ + pmic_config_interface( + PMIC_TOP_RST_MISC_SET, 0x0020, 0xFFFF, 0); + /* [1]=0, RG_WDTRSTB_MODE */ + pmic_config_interface( + PMIC_TOP_RST_MISC_CLR, 0x0002, 0xFFFF, 0); + /* [0]=1, RG_WDTRSTB_EN */ + pmic_config_interface(PMIC_TOP_RST_MISC_SET, 0x0001, 0xFFFF, 0); +} + +static void mt6358_init_setting(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(init_setting); i++) + pmic_config_interface( + init_setting[i].addr, init_setting[i].val, + init_setting[i].mask, init_setting[i].shift); +} + +static void wk_sleep_voltage_by_ddr(void) +{ + u16 ddr_type; + + ddr_type = pmic_read_interface( + PMIC_VM_MODE, 0x3, 0); + + if (ddr_type == 0x2) + pmic_config_interface(PMIC_VDRAM1_VOSEL_SLEEP, + 0x3A, 0x7F, 0); +} + +static void wk_power_down_seq(void) +{ + /* Write TMA KEY with magic number */ + pmic_config_interface(PMIC_TOP_TMA_KEY, 0x9CA7, 0xFFFF, 0); + /* Set VPROC12 sequence to VA12 */ + pmic_config_interface(PMIC_CPSDSA4, 0xA, 0x1F, 0); + pmic_config_interface(PMIC_TOP_TMA_KEY, 0x0, 0xFFFF, 0); +} + +static void mt6358_lp_setting(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(lp_setting); i++) + pmic_config_interface( + lp_setting[i].addr, lp_setting[i].val, + lp_setting[i].mask, lp_setting[i].shift); +} + +void mt6358_init(void) +{ + if (pwrap_init()) + die("ERROR - Failed to initial pmic wrap!"); + + pmic_set_power_hold(true); + pmic_wdt_set(); + mt6358_init_setting(); + wk_sleep_voltage_by_ddr(); + wk_power_down_seq(); + mt6358_lp_setting(); +} diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c index b51e7d4..9a51b90 100644 --- a/src/soc/mediatek/mt8183/soc.c +++ b/src/soc/mediatek/mt8183/soc.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <soc/emi.h> #include <soc/mmu_operations.h> +#include <soc/mt6358.h> #include <symbols.h> @@ -27,6 +28,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + mt6358_init(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/29422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic247faf73517f6512f9c9a69ba0254c749d68d4c Gerrit-Change-Number: 29422 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: mediatek/mt8183: Add PMIC wrapper support
by Tristan Hsieh (Code Review) 01 Nov '18

01 Nov '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/29421 Change subject: mediatek/mt8183: Add PMIC wrapper support ...................................................................... mediatek/mt8183: Add PMIC wrapper support BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Idbdb15f11227ded3f5d18fe6504c8c646973b733 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/pmic_wrap.h A src/soc/mediatek/mt8183/pmic_wrap.c 4 files changed, 883 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/29421/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 5650465..e8efe90 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -34,6 +34,7 @@ ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c +ramstage-y += ../common/pmic_wrap.c pmic_wrap.c ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index 1ba9cc8..78c6cf4 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -29,6 +29,7 @@ RGU_BASE = IO_PHYS + 0x00007000, GPT_BASE = IO_PHYS + 0x00008000, APMIXED_BASE = IO_PHYS + 0x0000C000, + PWRAP_BASE = IO_PHYS + 0x0000D000, EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CH_BASE = IO_PHYS + 0x00228000, diff --git a/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h new file mode 100644 index 0000000..a995038 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h @@ -0,0 +1,570 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MT8183_PMIC_WRAP_H__ +#define __SOC_MEDIATEK_MT8183_PMIC_WRAP_H__ + +#include <soc/addressmap.h> +#include <soc/pmic_wrap_common.h> +#include <types.h> + +struct mt8183_pwrap_regs { + u32 mux_sel; + u32 wrap_en; + u32 dio_en; + u32 si_sample_ctrl; + u32 si_sample_ctrl_ulposc; + u32 rddmy; + u32 cshext_write; + u32 cshext_read; + u32 cslext_write; + u32 cslext_read; + u32 ext_ck_write; + u32 ext_ck_read; + u32 staupd_ctrl; + u32 staupd_grpen; + u32 eint_sta0_adr; + u32 eint_sta1_adr; + u32 eint_sta; + u32 eint_clr; + u32 eint_ctrl; + u32 staupd_man_trig; + u32 staupd_sta; + u32 wrap_sta; + u32 harb_init; + u32 harb_hprio; + u32 hiprio_arb_en; + u32 harb_sta0; + u32 harb_sta1; + u32 harb_sta2; + u32 man_en; + u32 man_cmd; + u32 man_rdata; + u32 man_vldclr; + u32 wacs0_en; + u32 init_done0; + u32 wacs1_en; + u32 init_done1; + u32 wacs2_en; + u32 init_done2; + u32 wacs3_en; + u32 init_done3; + u32 wacs_p2p_en; + u32 init_done_p2p; + u32 wacs_md32_en; + u32 init_done_md32; + u32 int0_en; + u32 int0_flg_raw; + u32 int0_flg; + u32 int0_clr; + u32 int1_en; + u32 int1_flg_raw; + u32 int1_flg; + u32 int1_clr; + u32 sig_adr; + u32 sig_mode; + u32 sig_value; + u32 sig_errval; + u32 crc_en; + u32 timer_en; + u32 timer_sta; + u32 wdt_unit; + u32 wdt_src_en_0; + u32 wdt_src_en_1; + u32 wdt_flg_0; + u32 wdt_flg_1; + u32 debug_int_sel; + u32 dvfs_adr0; + u32 dvfs_wdata0; + u32 dvfs_adr1; + u32 dvfs_wdata1; + u32 dvfs_adr2; + u32 dvfs_wdata2; + u32 dvfs_adr3; + u32 dvfs_wdata3; + u32 dvfs_adr4; + u32 dvfs_wdata4; + u32 dvfs_adr5; + u32 dvfs_wdata5; + u32 dvfs_adr6; + u32 dvfs_wdata6; + u32 dvfs_adr7; + u32 dvfs_wdata7; + u32 dvfs_adr8; + u32 dvfs_wdata8; + u32 dvfs_adr9; + u32 dvfs_wdata9; + u32 dvfs_adr10; + u32 dvfs_wdata10; + u32 dvfs_adr11; + u32 dvfs_wdata11; + u32 dvfs_adr12; + u32 dvfs_wdata12; + u32 dvfs_adr13; + u32 dvfs_wdata13; + u32 dvfs_adr14; + u32 dvfs_wdata14; + u32 dvfs_adr15; + u32 dvfs_wdata15; + u32 dcxo_enable; + u32 dcxo_conn_adr0; + u32 dcxo_conn_wdata0; + u32 dcxo_conn_adr1; + u32 dcxo_conn_wdata1; + u32 dcxo_nfc_adr0; + u32 dcxo_nfc_wdata0; + u32 dcxo_nfc_adr1; + u32 dcxo_nfc_wdata1; + u32 spminf_sta_0; + u32 spminf_sta_1; + u32 spminf_backup_sta; + u32 scpinf_sta; + u32 cipher_key_sel; + u32 cipher_iv_sel; + u32 cipher_en; + u32 cipher_rdy; + u32 cipher_mode; + u32 cipher_swrst; + u32 dcm_en; + u32 dcm_spi_dbc_prd; + u32 dcm_dbc_prd; + u32 int_gps_auxadc_cmd_addr; + u32 int_gps_auxadc_cmd; + u32 int_gps_auxadc_rdata_addr; + u32 ext_gps_auxadc_rdata_addr; + u32 gpsinf_0_sta; + u32 gpsinf_1_sta; + u32 md_adcinf_ctrl; + u32 md_auxadc_rdata_latest_addr; + u32 md_auxadc_rdata_wp_addr; + u32 md_auxadc_rdata[32]; + u32 md_adcinf_0_sta_0; + u32 md_adcinf_0_sta_1; + u32 md_adcinf_1_sta_0; + u32 md_adcinf_1_sta_1; + u32 swrst; + u32 spm_sleep_gating_ctrl; + u32 scp_sleep_gating_ctrl; + u32 priority_user_sel_0; + u32 priority_user_sel_1; + u32 priority_user_sel_2; + u32 priority_user_sel_3; + u32 priority_user_sel_4; + u32 arbiter_out_sel_0; + u32 arbiter_out_sel_1; + u32 arbiter_out_sel_2; + u32 arbiter_out_sel_3; + u32 arbiter_out_sel_4; + u32 starv_counter_0; + u32 starv_counter_1; + u32 starv_counter_2; + u32 starv_counter_3; + u32 starv_counter_4; + u32 starv_counter_5; + u32 starv_counter_6; + u32 starv_counter_7; + u32 starv_counter_8; + u32 starv_counter_9; + u32 starv_counter_10; + u32 starv_counter_11; + u32 starv_counter_12; + u32 starv_counter_13; + u32 starv_counter_14; + u32 starv_counter_15; + u32 starv_counter_16; + u32 starv_counter_0_status; + u32 starv_counter_1_status; + u32 starv_counter_2_status; + u32 starv_counter_3_status; + u32 starv_counter_4_status; + u32 starv_counter_5_status; + u32 starv_counter_6_status; + u32 starv_counter_7_status; + u32 starv_counter_8_status; + u32 starv_counter_9_status; + u32 starv_counter_10_status; + u32 starv_counter_11_status; + u32 starv_counter_12_status; + u32 starv_counter_13_status; + u32 starv_counter_14_status; + u32 starv_counter_15_status; + u32 starv_counter_16_status; + u32 starv_counter_clr; + u32 starv_prio_status; + u32 monitor_ctrl_0; + u32 monitor_ctrl_1; + u32 monitor_ctrl_2; + u32 monitor_ctrl_3; + u32 channel_sequence_0; + u32 channel_sequence_1; + u32 channel_sequence_2; + u32 channel_sequence_3; + u32 cmd_sequence_0; + u32 cmd_sequence_1; + u32 cmd_sequence_2; + u32 cmd_sequence_3; + u32 cmd_sequence_4; + u32 cmd_sequence_5; + u32 cmd_sequence_6; + u32 cmd_sequence_7; + u32 wdata_sequence_0; + u32 wdata_sequence_1; + u32 wdata_sequence_2; + u32 wdata_sequence_3; + u32 wdata_sequence_4; + u32 wdata_sequence_5; + u32 wdata_sequence_6; + u32 wdata_sequence_7; + u32 debug_sw_driver_0; + u32 debug_sw_driver_1; + u32 debug_sw_driver_2; + u32 debug_sw_driver_3; + u32 debug_sw_driver_4; + u32 debug_sw_driver_5; + u32 bwc_options; + u32 reserved1[524]; + u32 wacs0_cmd; + u32 wacs0_rdata; + u32 wacs0_vldclr; + u32 reserved2; + u32 wacs1_cmd; + u32 wacs1_rdata; + u32 wacs1_vldclr; + u32 reserved3; + u32 wacs2_cmd; + u32 wacs2_rdata; + u32 wacs2_vldclr; + u32 reserved4; + u32 wacs3_cmd; + u32 wacs3_rdata; + u32 wacs3_vldclr; +}; + +check_member(mt8183_pwrap_regs, mux_sel, 0x0); +check_member(mt8183_pwrap_regs, wrap_en, 0x4); +check_member(mt8183_pwrap_regs, dio_en, 0x8); +check_member(mt8183_pwrap_regs, si_sample_ctrl, 0xC); +check_member(mt8183_pwrap_regs, si_sample_ctrl_ulposc, 0x10); +check_member(mt8183_pwrap_regs, rddmy, 0x14); +check_member(mt8183_pwrap_regs, cshext_write, 0x18); +check_member(mt8183_pwrap_regs, cshext_read, 0x1C); +check_member(mt8183_pwrap_regs, cslext_write, 0x20); +check_member(mt8183_pwrap_regs, cslext_read, 0x24); +check_member(mt8183_pwrap_regs, ext_ck_write, 0x28); +check_member(mt8183_pwrap_regs, ext_ck_read, 0x2C); +check_member(mt8183_pwrap_regs, staupd_ctrl, 0x30); +check_member(mt8183_pwrap_regs, staupd_grpen, 0x34); +check_member(mt8183_pwrap_regs, eint_sta0_adr, 0x38); +check_member(mt8183_pwrap_regs, eint_sta1_adr, 0x3C); +check_member(mt8183_pwrap_regs, eint_sta, 0x40); +check_member(mt8183_pwrap_regs, eint_clr, 0x44); +check_member(mt8183_pwrap_regs, eint_ctrl, 0x48); +check_member(mt8183_pwrap_regs, staupd_man_trig, 0x4C); +check_member(mt8183_pwrap_regs, staupd_sta, 0x50); +check_member(mt8183_pwrap_regs, wrap_sta, 0x54); +check_member(mt8183_pwrap_regs, harb_init, 0x58); +check_member(mt8183_pwrap_regs, harb_hprio, 0x5C); +check_member(mt8183_pwrap_regs, hiprio_arb_en, 0x60); +check_member(mt8183_pwrap_regs, harb_sta0, 0x64); +check_member(mt8183_pwrap_regs, harb_sta1, 0x68); +check_member(mt8183_pwrap_regs, harb_sta2, 0x6C); +check_member(mt8183_pwrap_regs, man_en, 0x70); +check_member(mt8183_pwrap_regs, man_cmd, 0x74); +check_member(mt8183_pwrap_regs, man_rdata, 0x78); +check_member(mt8183_pwrap_regs, man_vldclr, 0x7C); +check_member(mt8183_pwrap_regs, wacs0_en, 0x80); +check_member(mt8183_pwrap_regs, init_done0, 0x84); +check_member(mt8183_pwrap_regs, wacs1_en, 0x88); +check_member(mt8183_pwrap_regs, init_done1, 0x8C); +check_member(mt8183_pwrap_regs, wacs2_en, 0x90); +check_member(mt8183_pwrap_regs, init_done2, 0x94); +check_member(mt8183_pwrap_regs, wacs3_en, 0x98); +check_member(mt8183_pwrap_regs, init_done3, 0x9C); +check_member(mt8183_pwrap_regs, wacs_p2p_en, 0xA0); +check_member(mt8183_pwrap_regs, init_done_p2p, 0xA4); +check_member(mt8183_pwrap_regs, wacs_md32_en, 0xA8); +check_member(mt8183_pwrap_regs, init_done_md32, 0xAC); +check_member(mt8183_pwrap_regs, int0_en, 0xB0); +check_member(mt8183_pwrap_regs, int0_flg_raw, 0xB4); +check_member(mt8183_pwrap_regs, int0_flg, 0xB8); +check_member(mt8183_pwrap_regs, int0_clr, 0xBC); +check_member(mt8183_pwrap_regs, int1_en, 0xC0); +check_member(mt8183_pwrap_regs, int1_flg_raw, 0xC4); +check_member(mt8183_pwrap_regs, int1_flg, 0xC8); +check_member(mt8183_pwrap_regs, int1_clr, 0xCC); +check_member(mt8183_pwrap_regs, sig_adr, 0xD0); +check_member(mt8183_pwrap_regs, sig_mode, 0xD4); +check_member(mt8183_pwrap_regs, sig_value, 0xD8); +check_member(mt8183_pwrap_regs, sig_errval, 0xDC); +check_member(mt8183_pwrap_regs, crc_en, 0xE0); +check_member(mt8183_pwrap_regs, timer_en, 0xE4); +check_member(mt8183_pwrap_regs, timer_sta, 0xE8); +check_member(mt8183_pwrap_regs, wdt_unit, 0xEC); +check_member(mt8183_pwrap_regs, wdt_src_en_0, 0xF0); +check_member(mt8183_pwrap_regs, wdt_src_en_1, 0xF4); +check_member(mt8183_pwrap_regs, wdt_flg_0, 0xF8); +check_member(mt8183_pwrap_regs, wdt_flg_1, 0xFC); +check_member(mt8183_pwrap_regs, debug_int_sel, 0x100); +check_member(mt8183_pwrap_regs, dvfs_adr0, 0x104); +check_member(mt8183_pwrap_regs, dvfs_wdata0, 0x108); +check_member(mt8183_pwrap_regs, dvfs_adr1, 0x10C); +check_member(mt8183_pwrap_regs, dvfs_wdata1, 0x110); +check_member(mt8183_pwrap_regs, dvfs_adr2, 0x114); +check_member(mt8183_pwrap_regs, dvfs_wdata2, 0x118); +check_member(mt8183_pwrap_regs, dvfs_adr3, 0x11C); +check_member(mt8183_pwrap_regs, dvfs_wdata3, 0x120); +check_member(mt8183_pwrap_regs, dvfs_adr4, 0x124); +check_member(mt8183_pwrap_regs, dvfs_wdata4, 0x128); +check_member(mt8183_pwrap_regs, dvfs_adr5, 0x12C); +check_member(mt8183_pwrap_regs, dvfs_wdata5, 0x130); +check_member(mt8183_pwrap_regs, dvfs_adr6, 0x134); +check_member(mt8183_pwrap_regs, dvfs_wdata6, 0x138); +check_member(mt8183_pwrap_regs, dvfs_adr7, 0x13C); +check_member(mt8183_pwrap_regs, dvfs_wdata7, 0x140); +check_member(mt8183_pwrap_regs, dvfs_adr8, 0x144); +check_member(mt8183_pwrap_regs, dvfs_wdata8, 0x148); +check_member(mt8183_pwrap_regs, dvfs_adr9, 0x14C); +check_member(mt8183_pwrap_regs, dvfs_wdata9, 0x150); +check_member(mt8183_pwrap_regs, dvfs_adr10, 0x154); +check_member(mt8183_pwrap_regs, dvfs_wdata10, 0x158); +check_member(mt8183_pwrap_regs, dvfs_adr11, 0x15C); +check_member(mt8183_pwrap_regs, dvfs_wdata11, 0x160); +check_member(mt8183_pwrap_regs, dvfs_adr12, 0x164); +check_member(mt8183_pwrap_regs, dvfs_wdata12, 0x168); +check_member(mt8183_pwrap_regs, dvfs_adr13, 0x16C); +check_member(mt8183_pwrap_regs, dvfs_wdata13, 0x170); +check_member(mt8183_pwrap_regs, dvfs_adr14, 0x174); +check_member(mt8183_pwrap_regs, dvfs_wdata14, 0x178); +check_member(mt8183_pwrap_regs, dvfs_adr15, 0x17C); +check_member(mt8183_pwrap_regs, dvfs_wdata15, 0x180); +check_member(mt8183_pwrap_regs, dcxo_enable, 0x184); +check_member(mt8183_pwrap_regs, dcxo_conn_adr0, 0x188); +check_member(mt8183_pwrap_regs, dcxo_conn_wdata0, 0x18C); +check_member(mt8183_pwrap_regs, dcxo_conn_adr1, 0x190); +check_member(mt8183_pwrap_regs, dcxo_conn_wdata1, 0x194); +check_member(mt8183_pwrap_regs, dcxo_nfc_adr0, 0x198); +check_member(mt8183_pwrap_regs, dcxo_nfc_wdata0, 0x19C); +check_member(mt8183_pwrap_regs, dcxo_nfc_adr1, 0x1A0); +check_member(mt8183_pwrap_regs, dcxo_nfc_wdata1, 0x1A4); +check_member(mt8183_pwrap_regs, spminf_sta_0, 0x1A8); +check_member(mt8183_pwrap_regs, spminf_sta_1, 0x1AC); +check_member(mt8183_pwrap_regs, spminf_backup_sta, 0x1B0); +check_member(mt8183_pwrap_regs, scpinf_sta, 0x1B4); +check_member(mt8183_pwrap_regs, cipher_key_sel, 0x1B8); +check_member(mt8183_pwrap_regs, cipher_iv_sel, 0x1BC); +check_member(mt8183_pwrap_regs, cipher_en, 0x1C0); +check_member(mt8183_pwrap_regs, cipher_rdy, 0x1C4); +check_member(mt8183_pwrap_regs, cipher_mode, 0x1C8); +check_member(mt8183_pwrap_regs, cipher_swrst, 0x1CC); +check_member(mt8183_pwrap_regs, dcm_en, 0x1D0); +check_member(mt8183_pwrap_regs, dcm_spi_dbc_prd, 0x1D4); +check_member(mt8183_pwrap_regs, dcm_dbc_prd, 0x1D8); +check_member(mt8183_pwrap_regs, int_gps_auxadc_cmd_addr, 0x1DC); +check_member(mt8183_pwrap_regs, int_gps_auxadc_cmd, 0x1E0); +check_member(mt8183_pwrap_regs, int_gps_auxadc_rdata_addr, 0x1E4); +check_member(mt8183_pwrap_regs, ext_gps_auxadc_rdata_addr, 0x1E8); +check_member(mt8183_pwrap_regs, gpsinf_0_sta, 0x1EC); +check_member(mt8183_pwrap_regs, gpsinf_1_sta, 0x1F0); +check_member(mt8183_pwrap_regs, md_adcinf_ctrl, 0x1F4); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_latest_addr, 0x1F8); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_wp_addr, 0x1FC); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[0], 0x200); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[1], 0x204); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[2], 0x208); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[3], 0x20C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[4], 0x210); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[5], 0x214); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[6], 0x218); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[7], 0x21C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[8], 0x220); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[9], 0x224); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[10], 0x228); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[11], 0x22C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[12], 0x230); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[13], 0x234); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[14], 0x238); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[15], 0x23C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[16], 0x240); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[17], 0x244); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[18], 0x248); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[19], 0x24C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[20], 0x250); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[21], 0x254); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[22], 0x258); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[23], 0x25C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[24], 0x260); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[25], 0x264); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[26], 0x268); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[27], 0x26C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[28], 0x270); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[29], 0x274); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[30], 0x278); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[31], 0x27C); +check_member(mt8183_pwrap_regs, md_adcinf_0_sta_0, 0x280); +check_member(mt8183_pwrap_regs, md_adcinf_0_sta_1, 0x284); +check_member(mt8183_pwrap_regs, md_adcinf_1_sta_0, 0x288); +check_member(mt8183_pwrap_regs, md_adcinf_1_sta_1, 0x28C); +check_member(mt8183_pwrap_regs, swrst, 0x290); +check_member(mt8183_pwrap_regs, spm_sleep_gating_ctrl, 0x294); +check_member(mt8183_pwrap_regs, scp_sleep_gating_ctrl, 0x298); +check_member(mt8183_pwrap_regs, priority_user_sel_0, 0x29C); +check_member(mt8183_pwrap_regs, priority_user_sel_1, 0x2A0); +check_member(mt8183_pwrap_regs, priority_user_sel_2, 0x2A4); +check_member(mt8183_pwrap_regs, priority_user_sel_3, 0x2A8); +check_member(mt8183_pwrap_regs, priority_user_sel_4, 0x2AC); +check_member(mt8183_pwrap_regs, arbiter_out_sel_0, 0x2B0); +check_member(mt8183_pwrap_regs, arbiter_out_sel_1, 0x2B4); +check_member(mt8183_pwrap_regs, arbiter_out_sel_2, 0x2B8); +check_member(mt8183_pwrap_regs, arbiter_out_sel_3, 0x2BC); +check_member(mt8183_pwrap_regs, arbiter_out_sel_4, 0x2C0); +check_member(mt8183_pwrap_regs, starv_counter_0, 0x2C4); +check_member(mt8183_pwrap_regs, starv_counter_1, 0x2C8); +check_member(mt8183_pwrap_regs, starv_counter_2, 0x2CC); +check_member(mt8183_pwrap_regs, starv_counter_3, 0x2D0); +check_member(mt8183_pwrap_regs, starv_counter_4, 0x2D4); +check_member(mt8183_pwrap_regs, starv_counter_5, 0x2D8); +check_member(mt8183_pwrap_regs, starv_counter_6, 0x2DC); +check_member(mt8183_pwrap_regs, starv_counter_7, 0x2E0); +check_member(mt8183_pwrap_regs, starv_counter_8, 0x2E4); +check_member(mt8183_pwrap_regs, starv_counter_9, 0x2E8); +check_member(mt8183_pwrap_regs, starv_counter_10, 0x2EC); +check_member(mt8183_pwrap_regs, starv_counter_11, 0x2F0); +check_member(mt8183_pwrap_regs, starv_counter_12, 0x2F4); +check_member(mt8183_pwrap_regs, starv_counter_13, 0x2F8); +check_member(mt8183_pwrap_regs, starv_counter_14, 0x2FC); +check_member(mt8183_pwrap_regs, starv_counter_15, 0x300); +check_member(mt8183_pwrap_regs, starv_counter_16, 0x304); +check_member(mt8183_pwrap_regs, starv_counter_0_status, 0x308); +check_member(mt8183_pwrap_regs, starv_counter_1_status, 0x30C); +check_member(mt8183_pwrap_regs, starv_counter_2_status, 0x310); +check_member(mt8183_pwrap_regs, starv_counter_3_status, 0x314); +check_member(mt8183_pwrap_regs, starv_counter_4_status, 0x318); +check_member(mt8183_pwrap_regs, starv_counter_5_status, 0x31C); +check_member(mt8183_pwrap_regs, starv_counter_6_status, 0x320); +check_member(mt8183_pwrap_regs, starv_counter_7_status, 0x324); +check_member(mt8183_pwrap_regs, starv_counter_8_status, 0x328); +check_member(mt8183_pwrap_regs, starv_counter_9_status, 0x32C); +check_member(mt8183_pwrap_regs, starv_counter_10_status, 0x330); +check_member(mt8183_pwrap_regs, starv_counter_11_status, 0x334); +check_member(mt8183_pwrap_regs, starv_counter_12_status, 0x338); +check_member(mt8183_pwrap_regs, starv_counter_13_status, 0x33C); +check_member(mt8183_pwrap_regs, starv_counter_14_status, 0x340); +check_member(mt8183_pwrap_regs, starv_counter_15_status, 0x344); +check_member(mt8183_pwrap_regs, starv_counter_16_status, 0x348); +check_member(mt8183_pwrap_regs, starv_counter_clr, 0x34C); +check_member(mt8183_pwrap_regs, starv_prio_status, 0x350); +check_member(mt8183_pwrap_regs, monitor_ctrl_0, 0x354); +check_member(mt8183_pwrap_regs, monitor_ctrl_1, 0x358); +check_member(mt8183_pwrap_regs, monitor_ctrl_2, 0x35C); +check_member(mt8183_pwrap_regs, monitor_ctrl_3, 0x360); +check_member(mt8183_pwrap_regs, channel_sequence_0, 0x364); +check_member(mt8183_pwrap_regs, channel_sequence_1, 0x368); +check_member(mt8183_pwrap_regs, channel_sequence_2, 0x36C); +check_member(mt8183_pwrap_regs, channel_sequence_3, 0x370); +check_member(mt8183_pwrap_regs, cmd_sequence_0, 0x374); +check_member(mt8183_pwrap_regs, cmd_sequence_1, 0x378); +check_member(mt8183_pwrap_regs, cmd_sequence_2, 0x37C); +check_member(mt8183_pwrap_regs, cmd_sequence_3, 0x380); +check_member(mt8183_pwrap_regs, cmd_sequence_4, 0x384); +check_member(mt8183_pwrap_regs, cmd_sequence_5, 0x388); +check_member(mt8183_pwrap_regs, cmd_sequence_6, 0x38C); +check_member(mt8183_pwrap_regs, cmd_sequence_7, 0x390); +check_member(mt8183_pwrap_regs, wdata_sequence_0, 0x394); +check_member(mt8183_pwrap_regs, wdata_sequence_1, 0x398); +check_member(mt8183_pwrap_regs, wdata_sequence_2, 0x39C); +check_member(mt8183_pwrap_regs, wdata_sequence_3, 0x3A0); +check_member(mt8183_pwrap_regs, wdata_sequence_4, 0x3A4); +check_member(mt8183_pwrap_regs, wdata_sequence_5, 0x3A8); +check_member(mt8183_pwrap_regs, wdata_sequence_6, 0x3AC); +check_member(mt8183_pwrap_regs, wdata_sequence_7, 0x3B0); +check_member(mt8183_pwrap_regs, debug_sw_driver_0, 0x3B4); +check_member(mt8183_pwrap_regs, debug_sw_driver_1, 0x3B8); +check_member(mt8183_pwrap_regs, debug_sw_driver_2, 0x3BC); +check_member(mt8183_pwrap_regs, debug_sw_driver_3, 0x3C0); +check_member(mt8183_pwrap_regs, debug_sw_driver_4, 0x3C4); +check_member(mt8183_pwrap_regs, debug_sw_driver_5, 0x3C8); +check_member(mt8183_pwrap_regs, bwc_options, 0x3CC); +check_member(mt8183_pwrap_regs, reserved1, 0x3D0); +check_member(mt8183_pwrap_regs, wacs0_cmd, 0xC00); +check_member(mt8183_pwrap_regs, wacs0_rdata, 0xC04); +check_member(mt8183_pwrap_regs, wacs0_vldclr, 0xC08); +check_member(mt8183_pwrap_regs, reserved2, 0xC0C); +check_member(mt8183_pwrap_regs, wacs1_cmd, 0xC10); +check_member(mt8183_pwrap_regs, wacs1_rdata, 0xC14); +check_member(mt8183_pwrap_regs, wacs1_vldclr, 0xC18); +check_member(mt8183_pwrap_regs, reserved3, 0xC1C); +check_member(mt8183_pwrap_regs, wacs2_cmd, 0xC20); +check_member(mt8183_pwrap_regs, wacs2_rdata, 0xC24); +check_member(mt8183_pwrap_regs, wacs2_vldclr, 0xC28); +check_member(mt8183_pwrap_regs, reserved4, 0xC2C); +check_member(mt8183_pwrap_regs, wacs3_cmd, 0xC30); +check_member(mt8183_pwrap_regs, wacs3_rdata, 0xC34); +check_member(mt8183_pwrap_regs, wacs3_vldclr, 0xC38); + +static struct mt8183_pwrap_regs * const mtk_pwrap = (void *)PWRAP_BASE; + +enum { + WACS2 = 1 << 2 +}; + +/* PMIC registers */ +enum { + PMIC_BASE = 0x0000, + PMIC_SMT_CON1 = PMIC_BASE + 0x0030, + PMIC_DRV_CON1 = PMIC_BASE + 0x0038, + PMIC_FILTER_CON0 = PMIC_BASE + 0x0040, + PMIC_GPIO_PULLEN0_CLR = PMIC_BASE + 0x0098, + PMIC_RG_SPI_CON0 = PMIC_BASE + 0x0408, + PMIC_RG_SPI_RECORD0 = PMIC_BASE + 0x040A, + PMIC_DEW_DIO_EN = PMIC_BASE + 0x040C, + PMIC_DEW_READ_TEST = PMIC_BASE + 0x040E, + PMIC_DEW_WRITE_TEST = PMIC_BASE + 0x0410, + PMIC_DEW_CRC_EN = PMIC_BASE + 0x0414, + PMIC_DEW_CRC_VAL = PMIC_BASE + 0x0416, + PMIC_DEW_RDDMY_NO = PMIC_BASE + 0x0426, + PMIC_CPU_INT_STA = PMIC_BASE + 0x042E, + PMIC_RG_SPI_CON2 = PMIC_BASE + 0x0432, + PMIC_RG_SPI_CON3 = PMIC_BASE + 0x0434, + PMIC_RG_SPI_CON4 = PMIC_BASE + 0x0436, + PMIC_RG_SPI_CON5 = PMIC_BASE + 0x0438, + PMIC_RG_SPI_CON6 = PMIC_BASE + 0x043A, + PMIC_RG_SPI_CON7 = PMIC_BASE + 0x043C, + PMIC_RG_SPI_CON8 = PMIC_BASE + 0x043E, + PMIC_RG_SPI_CON13 = PMIC_BASE + 0x0448, + PMIC_SPISLV_KEY = PMIC_BASE + 0x044A, + PMIC_PPCCTL0 = PMIC_BASE + 0x0A08, + PMIC_AUXADC_ADC17 = PMIC_BASE + 0x10AA, + PMIC_AUXADC_ADC31 = PMIC_BASE + 0x10C6, + PMIC_AUXADC_ADC32 = PMIC_BASE + 0x10C8, + PMIC_AUXADC_ADC35 = PMIC_BASE + 0x10CE, + PMIC_AUXADC_RQST0 = PMIC_BASE + 0x1108, + PMIC_AUXADC_RQST1 = PMIC_BASE + 0x110A, +}; + +enum { + E_CLK_EDGE = 1, + E_CLK_LAST_SETTING +}; + +enum pmic_regck { + REG_CLOCK_18MHZ = 1, + REG_CLOCK_SAFE_MODE +}; + +enum { + GPS_MAIN = 0x40, + GPS_SUBSYS = 0x80 +}; +#endif /* __SOC_MEDIATEK_MT8183_PMIC_WRAP_H__ */ diff --git a/src/soc/mediatek/mt8183/pmic_wrap.c b/src/soc/mediatek/mt8183/pmic_wrap.c new file mode 100644 index 0000000..bad979a --- /dev/null +++ b/src/soc/mediatek/mt8183/pmic_wrap.c @@ -0,0 +1,311 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <soc/infracfg.h> +#include <soc/pll.h> +#include <soc/pmic_wrap.h> + +static void pwrap_soft_reset(void) +{ + write32(&mt8183_infracfg->infra_globalcon_rst2_set, 0x1); + write32(&mt8183_infracfg->infra_globalcon_rst2_clr, 0x1); +} + +static void pwrap_spi_clk_set(void) +{ + write32(&mtk_topckgen->clk_cfg_5_clr, 0x93000000); + write32(&mtk_topckgen->clk_cfg_5_set, 0x1 << 24); + write32(&mtk_topckgen->clk_cfg_update, 0x1 << 23); + + write32(&mt8183_infracfg->module_sw_cg_0_set, 0x0000000F); + write32(&mt8183_infracfg->module_sw_cg_2_set, 0x00000100); + + pwrap_soft_reset(); + + write32(&mt8183_infracfg->module_sw_cg_0_clr, 0x0000000F); + write32(&mt8183_infracfg->module_sw_cg_2_clr, 0x00000100); +} + +static s32 pwrap_init_dio(u16 dio_en) +{ + u32 rdata = 0x0; + + pwrap_write_nochk(PMIC_DEW_DIO_EN, dio_en); + do { + rdata = read32(&mtk_pwrap->wacs2_rdata); + } while (wait_for_idle_and_sync(rdata)); + + write32(&mtk_pwrap->dio_en, dio_en); + return 0; +} + +static void pwrap_lock_spislvreg(void) +{ + pwrap_write_nochk(PMIC_SPISLV_KEY, 0x0); +} + +static void pwrap_initstaupd(void) +{ + write32(&mtk_pwrap->staupd_grpen, 0xf5); + + /* CRC */ + pwrap_write_nochk(PMIC_DEW_CRC_EN, 0x1); + write32(&mtk_pwrap->crc_en, 0x1); + write32(&mtk_pwrap->sig_adr, PMIC_DEW_CRC_VAL); + + write32(&mtk_pwrap->eint_sta0_adr, PMIC_CPU_INT_STA); + + /* MD ADC Interface */ + write32(&mtk_pwrap->md_auxadc_rdata_latest_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + write32(&mtk_pwrap->md_auxadc_rdata_wp_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + for (size_t i = 0; i < 32; i++) + write32(&mtk_pwrap->md_auxadc_rdata[i], + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + + write32(&mtk_pwrap->int_gps_auxadc_cmd_addr, + (PMIC_AUXADC_RQST1 << 16) + PMIC_AUXADC_RQST0); + write32(&mtk_pwrap->int_gps_auxadc_cmd, (GPS_MAIN << 16) + GPS_SUBSYS); + write32(&mtk_pwrap->int_gps_auxadc_rdata_addr, + (PMIC_AUXADC_ADC32 << 16) + PMIC_AUXADC_ADC17); + + write32(&mtk_pwrap->ext_gps_auxadc_rdata_addr, PMIC_AUXADC_ADC31); +} + +static void pwrap_starve_set(void) +{ + write32(&mtk_pwrap->harb_hprio, 0xf); + write32(&mtk_pwrap->starv_counter_0, 0x402); + write32(&mtk_pwrap->starv_counter_1, 0x403); + write32(&mtk_pwrap->starv_counter_2, 0x403); + write32(&mtk_pwrap->starv_counter_3, 0x403); + write32(&mtk_pwrap->starv_counter_4, 0x40f); + write32(&mtk_pwrap->starv_counter_5, 0x420); + write32(&mtk_pwrap->starv_counter_6, 0x428); + write32(&mtk_pwrap->starv_counter_7, 0x428); + write32(&mtk_pwrap->starv_counter_8, 0x413); + write32(&mtk_pwrap->starv_counter_9, 0x417); + write32(&mtk_pwrap->starv_counter_10, 0x417); + write32(&mtk_pwrap->starv_counter_11, 0x47c); + write32(&mtk_pwrap->starv_counter_12, 0x47c); + write32(&mtk_pwrap->starv_counter_13, 0x740); + write32(&mtk_pwrap->starv_counter_16, 0x740); +} + +static void pwrap_enable(void) +{ + write32(&mtk_pwrap->hiprio_arb_en, 0x3fa75); + write32(&mtk_pwrap->wacs0_en, 0x1); + write32(&mtk_pwrap->wacs2_en, 0x1); + write32(&mtk_pwrap->wacs_p2p_en, 0x1); + write32(&mtk_pwrap->wacs_md32_en, 0x1); + write32(&mtk_pwrap->staupd_ctrl, 0x5); + write32(&mtk_pwrap->wdt_unit, 0xf); + write32(&mtk_pwrap->wdt_src_en_0, 0xffffffff); + write32(&mtk_pwrap->wdt_src_en_1, 0xffffffff); + write32(&mtk_pwrap->timer_en, 0x1); + write32(&mtk_pwrap->int0_en, 0xffffffff); + write32(&mtk_pwrap->int1_en, 0xeef7ffff); +} + +static s32 pwrap_init_sistrobe(void) +{ + u16 rdata; + int si_sample_ctrl; + int test_data[30] = { + 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, + 0x9669, 0x6996, 0x9669, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, + 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x1B27, + 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, + 0x1B27, 0x1B27}; + + for (si_sample_ctrl = 0; si_sample_ctrl < 16; si_sample_ctrl++) { + write32(&mtk_pwrap->si_sample_ctrl, si_sample_ctrl << 5); + + pwrap_read_nochk(PMIC_DEW_READ_TEST, &rdata); + if (rdata == DEFAULT_VALUE_READ_TEST) + break; + } + + if (si_sample_ctrl == 16) + return E_CLK_EDGE; + + if (si_sample_ctrl == 15) + return E_CLK_LAST_SETTING; + + for (int si_dly = 0; si_dly < 10; si_dly++) { + pwrap_write_nochk(PMIC_RG_SPI_CON2, si_dly); + + int error = 0; + for (size_t i = 0; i < 30; i++) { + pwrap_write_nochk(PMIC_DEW_WRITE_TEST, test_data[i]); + pwrap_read_nochk(PMIC_DEW_WRITE_TEST, &rdata); + if ((rdata & 0x7fff) != (test_data[i] & 0x7fff)) { + /* Data boundary is found */ + error = 1; + break; + } + } + if (error == 1) + break; + } + + /* Change The Sampling Clock Edge To The Next One. */ + write32(&mtk_pwrap->si_sample_ctrl, ++si_sample_ctrl << 5); + + /* Read Test */ + pwrap_read_nochk(PMIC_DEW_READ_TEST, &rdata); + if (rdata != DEFAULT_VALUE_READ_TEST) { + pwrap_err("rdata = %x, exp = 0x5aa5\n", rdata); + return 0x10; + } + + return 0; +} + +static void pwrap_init_spislv(void) +{ + /* Turn on IO filter function */ + pwrap_write_nochk(PMIC_FILTER_CON0, 0xf0); + /* Turn on IO SMT function to improve noise immunity */ + pwrap_write_nochk(PMIC_SMT_CON1, 0xf); + /* Turn off IO pull function for power saving */ + pwrap_write_nochk(PMIC_GPIO_PULLEN0_CLR, 0xf0); + /* Turn off IO pull function for power saving */ + pwrap_write_nochk(PMIC_RG_SPI_CON0, 0x1); + /* Set PMIC GPIO driving current to 4mA */ + pwrap_write_nochk(PMIC_DRV_CON1, 0x8888); +} + +static void pwrap_init_reg_clock(u16 regck_sel) +{ + write32(&mtk_pwrap->ext_ck_write, 0x1); + + pwrap_write_nochk(PMIC_DEW_RDDMY_NO, 0x8); + write32(&mtk_pwrap->rddmy, 0x8); + + /* Config SPI Waveform according to reg clk */ + uint32_t value = (regck_sel == REG_CLOCK_18MHZ) ? 0 : 0x0f0f; + write32(&mtk_pwrap->cshext_write, value); + write32(&mtk_pwrap->cshext_read, value); + write32(&mtk_pwrap->cslext_write, value); + write32(&mtk_pwrap->cslext_read, value); +} + +s32 pwrap_init(void) +{ + s32 sub_return = 0, sub_return1 = 0; + u16 rdata; + + pwrap_spi_clk_set(); + + /* Reset spislv */ + sub_return = pwrap_reset_spislv(); + if (sub_return != 0) { + pwrap_err("reset_spislv fail, ret=%x\n", sub_return); + return E_PWR_INIT_RESET_SPI; + } + + /* Enable WRAP */ + write32(&mtk_pwrap->wrap_en, 0x1); + + /* Enable WACS2 */ + write32(&mtk_pwrap->wacs2_en, 0x1); + write32(&mtk_pwrap->hiprio_arb_en, WACS2); /* ONLY WACS2 */ + + /* SPI Waveform Configuration. 0:safe mode, 1:18MHz */ + pwrap_init_reg_clock(REG_CLOCK_18MHZ); + + /* SPI Slave Configuration */ + pwrap_init_spislv(); + + /* Enable DIO mode */ + sub_return = pwrap_init_dio(1); + if (sub_return != 0) { + pwrap_err("dio test error, err=%x, ret=%x\n", 0x11, sub_return); + return E_PWR_INIT_DIO; + } + + /* Input data calibration flow; */ + sub_return = pwrap_init_sistrobe(); + if (sub_return != 0) { + pwrap_err("InitSiStrobe fail,ret=%x\n", sub_return); + return E_PWR_INIT_SIDLY; + } + + /* + * Write test using WACS2, + * make sure the read/write function ready. + */ + sub_return = pwrap_write_nochk(PMIC_DEW_WRITE_TEST, WRITE_TEST_VALUE); + sub_return1 = pwrap_read_nochk(PMIC_DEW_WRITE_TEST, &rdata); + if (rdata != WRITE_TEST_VALUE || sub_return || sub_return1) { + pwrap_err("write error, rdata=%#x, return=%#x, return1=%#x\n", + rdata, sub_return, sub_return1); + return E_PWR_INIT_WRITE_TEST; + } + + /* + * Status update function initialization + * 1. Signature Checking using CRC (CRC 0 only) + * 2. EINT update + * 3. Read back Auxadc thermal data for GPS + */ + pwrap_initstaupd(); + + write32(&mtk_pwrap->priority_user_sel_2, 0x0b09080a); + write32(&mtk_pwrap->arbiter_out_sel_2, 0x0b080a09); + + pwrap_starve_set(); + + pwrap_enable(); + + /* Initialization Done */ + write32(&mtk_pwrap->init_done0, 0x1); + write32(&mtk_pwrap->init_done2, 0x1); + write32(&mtk_pwrap->init_done_p2p, 0x1); + write32(&mtk_pwrap->init_done_md32, 0x1); + + /* Lock SPISLV Registers */ + pwrap_lock_spislvreg(); + + /* Enable Command Recording */ + sub_return = pwrap_write_nochk(PMIC_RG_SPI_RECORD0, 0x1); + if (sub_return != 0) + pwrap_err("enable spi debug fail, ret=%x\n", sub_return); + + /* Clear Last three command */ + sub_return = pwrap_write_nochk(PMIC_RG_SPI_CON13, 0x1); + if (sub_return != 0) + pwrap_err("clear record command fail, ret=%x\n", sub_return); + sub_return = pwrap_write_nochk(PMIC_RG_SPI_CON13, 0x0); + if (sub_return != 0) + pwrap_err("clear record command fail, ret=%x\n", sub_return); + + /* Disable monitor MD HW channel (CH8) */ + write32(&mtk_pwrap->monitor_ctrl_1, 0x1feff); + /* Record all addr (mask+addr) */ + write32(&mtk_pwrap->monitor_ctrl_2, 0x0); + /* Record all wdata (mask+addr) */ + write32(&mtk_pwrap->monitor_ctrl_3, 0x0); + /* Clear log */ + write32(&mtk_pwrap->monitor_ctrl_0, 0x8); + /* Reenable */ + write32(&mtk_pwrap->monitor_ctrl_0, 0x1); + + return 0; +} -- To view, visit https://review.coreboot.org/29421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idbdb15f11227ded3f5d18fe6504c8c646973b733 Gerrit-Change-Number: 29421 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: mediatek: Refactor PMIC wrapper code among similar SoCs
by Tristan Hsieh (Code Review) 01 Nov '18

01 Nov '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/29420 Change subject: mediatek: Refactor PMIC wrapper code among similar SoCs ...................................................................... mediatek: Refactor PMIC wrapper code among similar SoCs Refactor PMIC wrapper code which will be reused among similar SoCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I25acb6da49e72748d856804ef4f97e9ec3bef72d Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- A src/soc/mediatek/common/include/soc/pmic_wrap_common.h A src/soc/mediatek/common/pmic_wrap.c M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8173/include/soc/pmic_wrap.h M src/soc/mediatek/mt8173/pmic_wrap.c 5 files changed, 376 insertions(+), 337 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/29420/1 diff --git a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h new file mode 100644 index 0000000..f01e9b0 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_PMIC_WRAP_COMMON_H +#define SOC_MEDIATEK_PMIC_WRAP_COMMON_H + +#include <arch/io.h> +#include <console/console.h> +#include <timer.h> + +#define PWRAPTAG "[PWRAP] " +#define pwrap_err(fmt, arg ...) printk(BIOS_ERR, PWRAPTAG "ERROR,line=%d" fmt, \ + __LINE__, ## arg) + +/* external API */ +s32 pwrap_read(u16 adr, u16 *rdata); +s32 pwrap_write(u16 adr, u16 wdata); +s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check); +s32 pwrap_init(void); + +/* internal API */ +s32 pwrap_reset_spislv(void); +s32 pwrap_read_nochk(u16 adr, u16 *rdata); +s32 pwrap_write_nochk(u16 adr, u16 wdata); + +/* dewrapper defaule value */ +enum { + DEFAULT_VALUE_READ_TEST = 0x5aa5, + WRITE_TEST_VALUE = 0xa55a +}; + +/* timeout setting */ +enum { + TIMEOUT_READ_US = 255, + TIMEOUT_WAIT_IDLE_US = 255 +}; + +/* manual commnd */ +enum { + OP_WR = 0x1, + OP_CSH = 0x0, + OP_CSL = 0x1, + OP_OUTS = 0x8, +}; + +enum { + RDATA_WACS_RDATA_SHIFT = 0, + RDATA_WACS_FSM_SHIFT = 16, + RDATA_WACS_REQ_SHIFT = 19, + RDATA_SYNC_IDLE_SHIFT, + RDATA_INIT_DONE_SHIFT, + RDATA_SYS_IDLE_SHIFT, +}; + +enum { + RDATA_WACS_RDATA_MASK = 0xffff, + RDATA_WACS_FSM_MASK = 0x7, + RDATA_WACS_REQ_MASK = 0x1, + RDATA_SYNC_IDLE_MASK = 0x1, + RDATA_INIT_DONE_MASK = 0x1, + RDATA_SYS_IDLE_MASK = 0x1, +}; + +/* WACS_FSM */ +enum { + WACS_FSM_IDLE = 0x00, + WACS_FSM_REQ = 0x02, + WACS_FSM_WFDLE = 0x04, /* wait for dle, wait for read data done */ + WACS_FSM_WFVLDCLR = 0x06, /* finish read data, wait for valid flag + * clearing */ + WACS_INIT_DONE = 0x01, + WACS_SYNC_IDLE = 0x01, + WACS_SYNC_BUSY = 0x00 +}; + +/* error information flag */ +enum { + E_PWR_INVALID_ARG = 1, + E_PWR_INVALID_RW = 2, + E_PWR_INVALID_ADDR = 3, + E_PWR_INVALID_WDAT = 4, + E_PWR_INVALID_OP_MANUAL = 5, + E_PWR_NOT_IDLE_STATE = 6, + E_PWR_NOT_INIT_DONE = 7, + E_PWR_NOT_INIT_DONE_READ = 8, + E_PWR_WAIT_IDLE_TIMEOUT = 9, + E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, + E_PWR_INIT_SIDLY_FAIL = 11, + E_PWR_RESET_TIMEOUT = 12, + E_PWR_TIMEOUT = 13, + E_PWR_INIT_RESET_SPI = 20, + E_PWR_INIT_SIDLY = 21, + E_PWR_INIT_REG_CLOCK = 22, + E_PWR_INIT_ENABLE_PMIC = 23, + E_PWR_INIT_DIO = 24, + E_PWR_INIT_CIPHER = 25, + E_PWR_INIT_WRITE_TEST = 26, + E_PWR_INIT_ENABLE_CRC = 27, + E_PWR_INIT_ENABLE_DEWRAP = 28, + E_PWR_INIT_ENABLE_EVENT = 29, + E_PWR_READ_TEST_FAIL = 30, + E_PWR_WRITE_TEST_FAIL = 31, + E_PWR_SWITCH_DIO = 32 +}; + +typedef u32 (*loop_condition_fp)(u32); + +static inline u32 wait_for_fsm_vldclr(u32 x) +{ + return ((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != + WACS_FSM_WFVLDCLR; +} + +static inline u32 wait_for_sync(u32 x) +{ + return ((x >> RDATA_SYNC_IDLE_SHIFT) & RDATA_SYNC_IDLE_MASK) != + WACS_SYNC_IDLE; +} + +static inline u32 wait_for_idle_and_sync(u32 x) +{ + return ((((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != + WACS_FSM_IDLE) || (((x >> RDATA_SYNC_IDLE_SHIFT) & + RDATA_SYNC_IDLE_MASK) != WACS_SYNC_IDLE)); +} + +static inline u32 wait_for_cipher_ready(u32 x) +{ + return x != 3; +} + +static inline u32 wait_for_state_idle(u32 timeout_us, void *wacs_register, + void *wacs_vldclr_register, + u32 *read_reg) +{ + u32 reg_rdata; + + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, timeout_us); + do { + reg_rdata = read32((wacs_register)); + /* if last read command timeout,clear vldclr bit + read command state machine:FSM_REQ-->wfdle-->WFVLDCLR; + write:FSM_REQ-->idle */ + switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & + RDATA_WACS_FSM_MASK)) { + case WACS_FSM_WFVLDCLR: + write32(wacs_vldclr_register, 1); + pwrap_err("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n"); + break; + case WACS_FSM_WFDLE: + pwrap_err("WACS_FSM = WACS_FSM_WFDLE\n"); + break; + case WACS_FSM_REQ: + pwrap_err("WACS_FSM = WACS_FSM_REQ\n"); + break; + default: + break; + } + + if (stopwatch_expired(&sw)) + return E_PWR_WAIT_IDLE_TIMEOUT; + + } while (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != + WACS_FSM_IDLE); /* IDLE State */ + if (read_reg) + *read_reg = reg_rdata; + return 0; +} + +static inline u32 wait_for_state_ready(loop_condition_fp fp, u32 timeout_us, + void *wacs_register, u32 *read_reg) +{ + u32 reg_rdata; + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, timeout_us); + do { + reg_rdata = read32((wacs_register)); + + if (stopwatch_expired(&sw)) { + pwrap_err("timeout when waiting for idle\n"); + return E_PWR_WAIT_IDLE_TIMEOUT; + } + } while (fp(reg_rdata)); /* IDLE State */ + if (read_reg) + *read_reg = reg_rdata; + return 0; +} + +#endif /* SOC_MEDIATEK_PMIC_WRAP_COMMON_H */ diff --git a/src/soc/mediatek/common/pmic_wrap.c b/src/soc/mediatek/common/pmic_wrap.c new file mode 100644 index 0000000..9e0832a --- /dev/null +++ b/src/soc/mediatek/common/pmic_wrap.c @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <assert.h> +#include <soc/pmic_wrap.h> + +s32 pwrap_reset_spislv(void) +{ + u32 ret = 0; + u32 return_value = 0; + + write32(&mtk_pwrap->hiprio_arb_en, 0); + write32(&mtk_pwrap->wrap_en, 0); + write32(&mtk_pwrap->mux_sel, 1); + write32(&mtk_pwrap->man_en, 1); + write32(&mtk_pwrap->dio_en, 0); + + write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_CSL << 8)); + /* to reset counter */ + write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); + write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_CSH << 8)); + /* + * In order to pull CSN signal to PMIC, + * PMIC will count it then reset spi slave + */ + write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); + write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); + write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); + write32(&mtk_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); + + return_value = wait_for_state_ready(wait_for_sync, + TIMEOUT_WAIT_IDLE_US, + &mtk_pwrap->wacs2_rdata, 0); + if (return_value != 0) { + pwrap_err("%s fail,return_value=%#x\n", __func__, return_value); + ret = E_PWR_TIMEOUT; + } + + write32(&mtk_pwrap->man_en, 0); + write32(&mtk_pwrap->mux_sel, 0); + + return ret; +} + +s32 pwrap_read_nochk(u16 adr, u16 *rdata) +{ + return pwrap_wacs2(0, adr, 0, rdata, 0); +} + +s32 pwrap_write_nochk(u16 adr, u16 wdata) +{ + return pwrap_wacs2(1, adr, wdata, 0, 0); +} + +s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check) +{ + u32 reg_rdata = 0; + u32 wacs_write = 0; + u32 wacs_adr = 0; + u32 wacs_cmd = 0; + u32 return_value = 0; + + if (init_check) { + reg_rdata = read32(&mtk_pwrap->wacs2_rdata); + /* Prevent someone to used pwrap before pwrap init */ + if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) & + RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { + pwrap_err("initialization isn't finished\n"); + return E_PWR_NOT_INIT_DONE; + } + } + reg_rdata = 0; + /* Check IDLE in advance */ + return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE_US, + &mtk_pwrap->wacs2_rdata, + &mtk_pwrap->wacs2_vldclr, + 0); + if (return_value != 0) { + pwrap_err("wait_for_fsm_idle fail,return_value=%d\n", + return_value); + return E_PWR_WAIT_IDLE_TIMEOUT; + } + wacs_write = write << 31; + wacs_adr = (adr >> 1) << 16; + wacs_cmd = wacs_write | wacs_adr | wdata; + + write32(&mtk_pwrap->wacs2_cmd, wacs_cmd); + if (write == 0) { + if (rdata == NULL) { + pwrap_err("rdata is a NULL pointer\n"); + return E_PWR_INVALID_ARG; + } + return_value = wait_for_state_ready(wait_for_fsm_vldclr, + TIMEOUT_READ_US, + &mtk_pwrap->wacs2_rdata, + &reg_rdata); + if (return_value != 0) { + pwrap_err("wait_for_fsm_vldclr fail,return_value=%d\n", + return_value); + return E_PWR_WAIT_IDLE_TIMEOUT_READ; + } + *rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT) + & RDATA_WACS_RDATA_MASK); + write32(&mtk_pwrap->wacs2_vldclr, 1); + } + + return 0; +} + +/* external API for pmic_wrap user */ + +s32 pwrap_read(u16 adr, u16 *rdata) +{ + return pwrap_wacs2(0, adr, 0, rdata, 1); +} + +s32 pwrap_write(u16 adr, u16 wdata) +{ + return pwrap_wacs2(1, adr, wdata, 0, 1); +} diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index e125e03..b2a5ebd 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -27,7 +27,8 @@ bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c endif -bootblock-y += ../common/gpio.c gpio.c gpio_init.c pmic_wrap.c mt6391.c +bootblock-y += ../common/gpio.c gpio.c gpio_init.c +bootblock-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c bootblock-y += ../common/wdt.c bootblock-y += ../common/mmu_operations.c mmu_operations.c @@ -56,7 +57,7 @@ romstage-y += ../common/cbmem.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/spi.c spi.c -romstage-y += pmic_wrap.c mt6391.c +romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c romstage-y += memory.c romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c @@ -72,7 +73,7 @@ ramstage-y += ../common/timer.c ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c -ramstage-y += pmic_wrap.c mt6391.c i2c.c +ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c i2c.c ramstage-y += mt6311.c ramstage-y += da9212.c ramstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h index 6807b13..3687a29 100644 --- a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h +++ b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h @@ -17,15 +17,10 @@ #define SOC_MEDIATEK_MT8173_PMIC_WRAP_H #include <soc/addressmap.h> +#include <soc/pmic_wrap_common.h> #include <types.h> -/* external API */ -s32 pwrap_read(u16 adr, u16 *rdata); -s32 pwrap_write(u16 adr, u16 wdata); -s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check); -s32 pwrap_init(void); - -static struct mt8173_pwrap_regs *const mt8173_pwrap = (void *)PMIC_WRAP_BASE; +static struct mt8173_pwrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE; enum { WACS2 = 1 << 4 @@ -44,12 +39,6 @@ PMIC_TOP_CKCON3 = PMIC_BASE + 0x01D4 }; -/* timeout setting */ -enum { - TIMEOUT_READ_US = 255, - TIMEOUT_WAIT_IDLE_US = 255 -}; - /* PMIC_WRAP registers */ struct mt8173_pwrap_regs { u32 mux_sel; @@ -136,36 +125,6 @@ check_member(mt8173_pwrap_regs, dcm_dbc_prd, 0x148); -enum { - RDATA_WACS_RDATA_SHIFT = 0, - RDATA_WACS_FSM_SHIFT = 16, - RDATA_WACS_REQ_SHIFT = 19, - RDATA_SYNC_IDLE_SHIFT, - RDATA_INIT_DONE_SHIFT, - RDATA_SYS_IDLE_SHIFT, -}; - -enum { - RDATA_WACS_RDATA_MASK = 0xffff, - RDATA_WACS_FSM_MASK = 0x7, - RDATA_WACS_REQ_MASK = 0x1, - RDATA_SYNC_IDLE_MASK = 0x1, - RDATA_INIT_DONE_MASK = 0x1, - RDATA_SYS_IDLE_MASK = 0x1, -}; - -/* WACS_FSM */ -enum { - WACS_FSM_IDLE = 0x00, - WACS_FSM_REQ = 0x02, - WACS_FSM_WFDLE = 0x04, /* wait for dle, wait for read data done */ - WACS_FSM_WFVLDCLR = 0x06, /* finish read data, wait for valid flag - * clearing */ - WACS_INIT_DONE = 0x01, - WACS_SYNC_IDLE = 0x01, - WACS_SYNC_BUSY = 0x00 -}; - /* dewrapper regsister */ enum { DEW_EVENT_OUT_EN = DEW_BASE + 0x0, @@ -195,57 +154,10 @@ DEW_CIPHER_IV5 = DEW_BASE + 0x30 }; -/* dewrapper defaule value */ -enum { - DEFAULT_VALUE_READ_TEST = 0x5aa5, - WRITE_TEST_VALUE = 0xa55a -}; - enum pmic_regck { REG_CLOCK_18MHZ, REG_CLOCK_26MHZ, REG_CLOCK_SAFE_MODE }; -/* manual commnd */ -enum { - OP_WR = 0x1, - OP_CSH = 0x0, - OP_CSL = 0x1, - OP_OUTS = 0x8, - OP_OUTD = 0x9, - OP_INS = 0xC, - OP_IND = 0xD -}; - -/* error information flag */ -enum { - E_PWR_INVALID_ARG = 1, - E_PWR_INVALID_RW = 2, - E_PWR_INVALID_ADDR = 3, - E_PWR_INVALID_WDAT = 4, - E_PWR_INVALID_OP_MANUAL = 5, - E_PWR_NOT_IDLE_STATE = 6, - E_PWR_NOT_INIT_DONE = 7, - E_PWR_NOT_INIT_DONE_READ = 8, - E_PWR_WAIT_IDLE_TIMEOUT = 9, - E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, - E_PWR_INIT_SIDLY_FAIL = 11, - E_PWR_RESET_TIMEOUT = 12, - E_PWR_TIMEOUT = 13, - E_PWR_INIT_RESET_SPI = 20, - E_PWR_INIT_SIDLY = 21, - E_PWR_INIT_REG_CLOCK = 22, - E_PWR_INIT_ENABLE_PMIC = 23, - E_PWR_INIT_DIO = 24, - E_PWR_INIT_CIPHER = 25, - E_PWR_INIT_WRITE_TEST = 26, - E_PWR_INIT_ENABLE_CRC = 27, - E_PWR_INIT_ENABLE_DEWRAP = 28, - E_PWR_INIT_ENABLE_EVENT = 29, - E_PWR_READ_TEST_FAIL = 30, - E_PWR_WRITE_TEST_FAIL = 31, - E_PWR_SWITCH_DIO = 32 -}; - #endif /* SOC_MEDIATEK_MT8173_PMIC_WRAP_H */ diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c index d7d4193..2c60e76 100644 --- a/src/soc/mediatek/mt8173/pmic_wrap.c +++ b/src/soc/mediatek/mt8173/pmic_wrap.c @@ -15,183 +15,10 @@ #include <arch/io.h> #include <assert.h> -#include <console/console.h> #include <delay.h> #include <soc/infracfg.h> #include <soc/pmic_wrap.h> -#include <timer.h> -#define PWRAPTAG "[PWRAP] " -#define pwrap_log(fmt, arg ...) printk(BIOS_INFO, PWRAPTAG fmt, ## arg) -#define pwrap_err(fmt, arg ...) printk(BIOS_ERR, PWRAPTAG "ERROR,line=%d" fmt, \ - __LINE__, ## arg) - -/* define macro and inline function (for do while loop) */ - -typedef u32 (*loop_condition_fp)(u32); - -static inline u32 wait_for_fsm_vldclr(u32 x) -{ - return ((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != - WACS_FSM_WFVLDCLR; -} - -static inline u32 wait_for_sync(u32 x) -{ - return ((x >> RDATA_SYNC_IDLE_SHIFT) & RDATA_SYNC_IDLE_MASK) != - WACS_SYNC_IDLE; -} - -static inline u32 wait_for_idle_and_sync(u32 x) -{ - return ((((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != - WACS_FSM_IDLE) || (((x >> RDATA_SYNC_IDLE_SHIFT) & - RDATA_SYNC_IDLE_MASK)!= WACS_SYNC_IDLE)); -} - -static inline u32 wait_for_cipher_ready(u32 x) -{ - return x != 3; -} - -static inline u32 wait_for_state_idle(u32 timeout_us, void *wacs_register, - void *wacs_vldclr_register, - u32 *read_reg) -{ - u32 reg_rdata; - - struct stopwatch sw; - - stopwatch_init_usecs_expire(&sw, timeout_us); - do { - reg_rdata = read32((wacs_register)); - /* if last read command timeout,clear vldclr bit - read command state machine:FSM_REQ-->wfdle-->WFVLDCLR; - write:FSM_REQ-->idle */ - switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & - RDATA_WACS_FSM_MASK)) { - case WACS_FSM_WFVLDCLR: - write32(wacs_vldclr_register, 1); - pwrap_err("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n"); - break; - case WACS_FSM_WFDLE: - pwrap_err("WACS_FSM = WACS_FSM_WFDLE\n"); - break; - case WACS_FSM_REQ: - pwrap_err("WACS_FSM = WACS_FSM_REQ\n"); - break; - default: - break; - } - - if (stopwatch_expired(&sw)) - return E_PWR_WAIT_IDLE_TIMEOUT; - - } while (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != - WACS_FSM_IDLE); /* IDLE State */ - if (read_reg) - *read_reg = reg_rdata; - return 0; -} - -static inline u32 wait_for_state_ready(loop_condition_fp fp, u32 timeout_us, - void *wacs_register, u32 *read_reg) -{ - u32 reg_rdata; - struct stopwatch sw; - - stopwatch_init_usecs_expire(&sw, timeout_us); - do { - reg_rdata = read32((wacs_register)); - - if (stopwatch_expired(&sw)) { - pwrap_err("timeout when waiting for idle\n"); - return E_PWR_WAIT_IDLE_TIMEOUT; - } - } while (fp(reg_rdata)); /* IDLE State */ - if (read_reg) - *read_reg = reg_rdata; - return 0; -} - -s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check) -{ - u32 reg_rdata = 0; - u32 wacs_write = 0; - u32 wacs_adr = 0; - u32 wacs_cmd = 0; - u32 return_value = 0; - - if (init_check) { - reg_rdata = read32(&mt8173_pwrap->wacs2_rdata); - /* Prevent someone to used pwrap before pwrap init */ - if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) & - RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { - pwrap_err("initialization isn't finished\n"); - return E_PWR_NOT_INIT_DONE; - } - } - reg_rdata = 0; - /* Check IDLE in advance */ - return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE_US, - &mt8173_pwrap->wacs2_rdata, - &mt8173_pwrap->wacs2_vldclr, - 0); - if (return_value != 0) { - pwrap_err("wait_for_fsm_idle fail,return_value=%d\n", - return_value); - return E_PWR_WAIT_IDLE_TIMEOUT; - } - wacs_write = write << 31; - wacs_adr = (adr >> 1) << 16; - wacs_cmd = wacs_write | wacs_adr | wdata; - - write32(&mt8173_pwrap->wacs2_cmd, wacs_cmd); - if (write == 0) { - if (NULL == rdata) { - pwrap_err("rdata is a NULL pointer\n"); - return E_PWR_INVALID_ARG; - } - return_value = wait_for_state_ready(wait_for_fsm_vldclr, - TIMEOUT_READ_US, - &mt8173_pwrap->wacs2_rdata, - &reg_rdata); - if (return_value != 0) { - pwrap_err("wait_for_fsm_vldclr fail,return_value=%d\n", - return_value); - return E_PWR_WAIT_IDLE_TIMEOUT_READ; - } - *rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT) - & RDATA_WACS_RDATA_MASK); - write32(&mt8173_pwrap->wacs2_vldclr, 1); - } - - return 0; -} - -/* external API for pmic_wrap user */ - -s32 pwrap_read(u16 adr, u16 *rdata) -{ - return pwrap_wacs2(0, adr, 0, rdata, 1); -} - -s32 pwrap_write(u16 adr, u16 wdata) -{ - return pwrap_wacs2(1, adr, wdata, 0, 1); -} - -static s32 pwrap_read_nochk(u16 adr, u16 *rdata) -{ - return pwrap_wacs2(0, adr, 0, rdata, 0); -} - -static s32 pwrap_write_nochk(u16 adr, u16 wdata) -{ - return pwrap_wacs2(1, adr, wdata, 0, 0); -} - -/* call it in pwrap_init,mustn't check init done */ static s32 pwrap_init_dio(u32 dio_en) { u16 rdata = 0; @@ -203,13 +30,13 @@ return_value = wait_for_state_ready(wait_for_idle_and_sync, TIMEOUT_WAIT_IDLE_US, - &mt8173_pwrap->wacs2_rdata, + &mtk_pwrap->wacs2_rdata, 0); if (return_value != 0) { pwrap_err("%s fail,return_value=%#x\n", __func__, return_value); return return_value; } - write32(&mt8173_pwrap->dio_en, dio_en); + write32(&mtk_pwrap->dio_en, dio_en); /* Read Test */ pwrap_read_nochk(DEW_READ_TEST, &rdata); if (rdata != DEFAULT_VALUE_READ_TEST) { @@ -235,7 +62,7 @@ u32 sidly = 0; for (i = 0; i < 4; i++) { - write32(&mt8173_pwrap->sidly, i); + write32(&mtk_pwrap->sidly, i); pwrap_wacs2(0, DEW_READ_TEST, 0, &rdata, 0); if (rdata == DEFAULT_VALUE_READ_TEST) pass |= 1 << i; @@ -285,49 +112,11 @@ die("sidly pass range not continuous\n"); } - write32(&mt8173_pwrap->sidly, sidly); + write32(&mtk_pwrap->sidly, sidly); return 0; } -static s32 pwrap_reset_spislv(void) -{ - u32 ret = 0; - u32 return_value = 0; - - write32(&mt8173_pwrap->hiprio_arb_en, 0); - write32(&mt8173_pwrap->wrap_en, 0); - write32(&mt8173_pwrap->mux_sel, 1); - write32(&mt8173_pwrap->man_en, 1); - write32(&mt8173_pwrap->dio_en, 0); - - write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSL << 8)); - /* to reset counter */ - write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); - write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSH << 8)); - /* - * In order to pull CSN signal to PMIC, - * PMIC will count it then reset spi slave - */ - write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); - write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); - write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); - write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); - - return_value = wait_for_state_ready(wait_for_sync, - TIMEOUT_WAIT_IDLE_US, - &mt8173_pwrap->wacs2_rdata, 0); - if (return_value != 0) { - pwrap_err("%s fail,return_value=%#x\n", __func__, return_value); - ret = E_PWR_TIMEOUT; - } - - write32(&mt8173_pwrap->man_en, 0); - write32(&mt8173_pwrap->mux_sel, 0); - - return ret; -} - static s32 pwrap_init_reg_clock(enum pmic_regck regck_sel) { u16 wdata = 0; @@ -350,25 +139,25 @@ /* Config SPI Waveform according to reg clk */ switch (regck_sel) { case REG_CLOCK_18MHZ: - write32(&mt8173_pwrap->rddmy, 0xc); - write32(&mt8173_pwrap->cshext_write, 0x0); - write32(&mt8173_pwrap->cshext_read, 0x4); - write32(&mt8173_pwrap->cslext_start, 0x0); - write32(&mt8173_pwrap->cslext_end, 0x4); + write32(&mtk_pwrap->rddmy, 0xc); + write32(&mtk_pwrap->cshext_write, 0x0); + write32(&mtk_pwrap->cshext_read, 0x4); + write32(&mtk_pwrap->cslext_start, 0x0); + write32(&mtk_pwrap->cslext_end, 0x4); break; case REG_CLOCK_26MHZ: - write32(&mt8173_pwrap->rddmy, 0xc); - write32(&mt8173_pwrap->cshext_write, 0x0); - write32(&mt8173_pwrap->cshext_read, 0x4); - write32(&mt8173_pwrap->cslext_start, 0x2); - write32(&mt8173_pwrap->cslext_end, 0x2); + write32(&mtk_pwrap->rddmy, 0xc); + write32(&mtk_pwrap->cshext_write, 0x0); + write32(&mtk_pwrap->cshext_read, 0x4); + write32(&mtk_pwrap->cslext_start, 0x2); + write32(&mtk_pwrap->cslext_end, 0x2); break; default: - write32(&mt8173_pwrap->rddmy, 0xf); - write32(&mt8173_pwrap->cshext_write, 0xf); - write32(&mt8173_pwrap->cshext_read, 0xf); - write32(&mt8173_pwrap->cslext_start, 0xf); - write32(&mt8173_pwrap->cslext_end, 0xf); + write32(&mtk_pwrap->rddmy, 0xf); + write32(&mtk_pwrap->cshext_write, 0xf); + write32(&mtk_pwrap->cshext_read, 0xf); + write32(&mtk_pwrap->cslext_start, 0xf); + write32(&mtk_pwrap->cslext_end, 0xf); break; } @@ -388,8 +177,8 @@ clrbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); /* Enable DCM */ - write32(&mt8173_pwrap->dcm_en, 3); - write32(&mt8173_pwrap->dcm_dbc_prd, 0); + write32(&mtk_pwrap->dcm_en, 3); + write32(&mtk_pwrap->dcm_dbc_prd, 0); /* Reset SPISLV */ sub_return = pwrap_reset_spislv(); @@ -399,9 +188,9 @@ return E_PWR_INIT_RESET_SPI; } /* Enable WACS2 */ - write32(&mt8173_pwrap->wrap_en, 1); - write32(&mt8173_pwrap->hiprio_arb_en, WACS2); - write32(&mt8173_pwrap->wacs2_en, 1); + write32(&mtk_pwrap->wrap_en, 1); + write32(&mtk_pwrap->hiprio_arb_en, WACS2); + write32(&mtk_pwrap->wacs2_en, 1); /* SIDLY setting */ sub_return = pwrap_init_sidly(); @@ -461,14 +250,14 @@ pwrap_err("enable CRC fail,sub_return=%#x\n", sub_return); return E_PWR_INIT_ENABLE_CRC; } - write32(&mt8173_pwrap->crc_en, 0x1); - write32(&mt8173_pwrap->sig_mode, 0x0); - write32(&mt8173_pwrap->sig_adr, DEW_CRC_VAL); + write32(&mtk_pwrap->crc_en, 0x1); + write32(&mtk_pwrap->sig_mode, 0x0); + write32(&mtk_pwrap->sig_adr, DEW_CRC_VAL); /* PMIC_WRAP enables */ - write32(&mt8173_pwrap->hiprio_arb_en, 0x1ff); - write32(&mt8173_pwrap->wacs0_en, 0x1); - write32(&mt8173_pwrap->wacs1_en, 0x1); + write32(&mtk_pwrap->hiprio_arb_en, 0x1ff); + write32(&mtk_pwrap->wacs0_en, 0x1); + write32(&mtk_pwrap->wacs1_en, 0x1); /* * switch event pin from usbdl mode to normal mode for pmic interrupt, @@ -481,9 +270,9 @@ sub_return); /* Initialization Done */ - write32(&mt8173_pwrap->init_done2, 0x1); - write32(&mt8173_pwrap->init_done0, 0x1); - write32(&mt8173_pwrap->init_done1, 0x1); + write32(&mtk_pwrap->init_done2, 0x1); + write32(&mtk_pwrap->init_done0, 0x1); + write32(&mtk_pwrap->init_done1, 0x1); return 0; } -- To view, visit https://review.coreboot.org/29420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I25acb6da49e72748d856804ef4f97e9ec3bef72d Gerrit-Change-Number: 29420 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: src/soc/intel/braswell/southcluster.c: Correct configuration of inter...
by build bot (Jenkins) (Code Review) 01 Nov '18

01 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29419 ) Change subject: src/soc/intel/braswell/southcluster.c: Correct configuration of interrupts ...................................................................... Patch Set 1: (12 comments) https://review.coreboot.org/#/c/29419/1/src/soc/intel/braswell/southcluster… File src/soc/intel/braswell/southcluster.c: https://review.coreboot.org/#/c/29419/1/src/soc/intel/braswell/southcluster… PS1, Line 120: for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/29419/1/src/soc/intel/braswell/southcluster… PS1, Line 152: /* Find the PIRQ that is attached to the INT_PIN this device uses */ line over 80 characters https://review.coreboot.org/#/c/29419/1/src/soc/intel/braswell/southcluster… PS1, Line 153: pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0x7; line over 80 characters https://review.coreboot.org/#/c/29419/1/src/soc/intel/braswell/southcluster… PS1, Line 159: /* Set this IRQ to level triggered since it is used by a PCI device */ line over 80 characters https://review.coreboot.org/#/c/29419/1/src/soc/intel/braswell/southcluster… PS1, Line 160: i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); line over 80 characters https://review.coreboot.org/#/c/29419/1/src/soc/intel/braswell/southcluster… PS1, Line 161: /* Set the Interrupt Line register in PCI config space */ line over 80 characters https://review.coreboot.org/#/c/29419/1/src/soc/intel/braswell/southcluster… PS1, Line 162: pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); line over 80 characters https://review.coreboot.org/#/c/29419/1/src/soc/intel/braswell/southcluster… PS1, Line 164: /* Set the Interrupt line register as "unknown or unused" */ line over 80 characters https://review.coreboot.org/#/c/29419/1/src/soc/intel/braswell/southcluster… PS1, Line 173: new_int_pin, pin_to_str(new_int_pin)); line over 80 characters https://review.coreboot.org/#/c/29419/1/src/soc/intel/braswell/southcluster… PS1, Line 284: if ( ir->pic[i] ) { space prohibited after that open parenthesis '(' https://review.coreboot.org/#/c/29419/1/src/soc/intel/braswell/southcluster… PS1, Line 284: if ( ir->pic[i] ) { space prohibited before that close parenthesis ')' https://review.coreboot.org/#/c/29419/1/src/soc/intel/braswell/southcluster… PS1, Line 284: if ( ir->pic[i] ) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/29419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I128cb35dd0e348a9cd9fb162651e0aa2b7e4a3ef Gerrit-Change-Number: 29419 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Nov 2018 10:38:56 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src/soc/intel/braswell/southcluster.c: Correct configuration of inter...
by Frans Hendriks (Code Review) 01 Nov '18

01 Nov '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29419 Change subject: src/soc/intel/braswell/southcluster.c: Correct configuration of interrupts ...................................................................... src/soc/intel/braswell/southcluster.c: Correct configuration of interrupts The level/edge mode of PIRQ is not configured and i8259 PIC not initialized. Add calls to i8259_configure_irq_trigger(), write_pci_config_irqs() and setup_i8259() to correct the configuration of interrupts. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I128cb35dd0e348a9cd9fb162651e0aa2b7e4a3ef Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/include/soc/irq.h M src/soc/intel/braswell/southcluster.c 2 files changed, 114 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/29419/1 diff --git a/src/soc/intel/braswell/include/soc/irq.h b/src/soc/intel/braswell/include/soc/irq.h index 4375c20..9a3c40d 100644 --- a/src/soc/intel/braswell/include/soc/irq.h +++ b/src/soc/intel/braswell/include/soc/irq.h @@ -154,6 +154,7 @@ #define PIRQ_PIC_IRQ12 0xc #define PIRQ_PIC_IRQ14 0xe #define PIRQ_PIC_IRQ15 0xf +#define PIRQ_PIC_UNKNOWN_UNUSED 0xff /* Overloaded term, but these values determine the per device route. */ #define PIRQA 0 diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index ca87d63..537d66d 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -26,6 +26,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <pc80/i8259.h> #include <pc80/mc146818rtc.h> #include <romstage_handoff.h> #include <soc/acpi.h> @@ -78,6 +79,105 @@ #define LPC_DEFAULT_IO_RANGE_LOWER 0 #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 +/* + * Write PCI config space IRQ assignments. PCI devices have the INT_LINE + * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing + * information to operating systems and drivers. The INT_PIN register is + * generally read only and reports which interrupt pin A - D it uses. The + * INT_LINE register is configurable and reports which IRQ (generally the + * PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling + * on devices that are downstream on a PCI bridge into account. + * + * This function will loop through all enabled PCI devices and program the + * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it + * uses. It then configures each interrupt in the pic to be level triggered. + */ +static void write_pci_config_irqs(void) +{ + device_t irq_dev; + device_t targ_dev; + uint8_t int_line = 0; + uint8_t original_int_pin = 0; + uint8_t new_int_pin = 0; + uint16_t current_bdf = 0; + uint16_t parent_bdf = 0; + uint8_t pirq = 0; + uint8_t device_num = 0; + const struct soc_irq_route *ir = &global_soc_irq_route; + + if (ir == NULL) { + printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" + " 'global_braswell_irq_route' structure does not exist\n"); + return; + } + + /* + * Loop through all enabled devices and program their + * INT_LINE, INT_PIN registers from values taken from + * the Interrupt Route registers in the ILB + */ + printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); + for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + + if ((irq_dev->path.type != DEVICE_PATH_PCI) || + (!irq_dev->enabled)) + continue; + + current_bdf = irq_dev->path.pci.devfn | + irq_dev->bus->secondary << 8; + + /* + * Step 1: Get the INT_PIN and device structure to look for + * in the pirq_data table defined in the mainboard directory. + */ + targ_dev = NULL; + new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); + if (targ_dev == NULL || new_int_pin < 1) + continue; + + /* Get the original INT_PIN for record keeping */ + original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + + parent_bdf = targ_dev->path.pci.devfn + | targ_dev->bus->secondary << 8; + device_num = PCI_SLOT(parent_bdf); + + if (ir->pcidev[device_num] == 0) { + printk(BIOS_WARNING, + "Warning: PCI Device %d does not have an IRQ entry, skipping it\n", + device_num); + continue; + } + + /* Find the PIRQ that is attached to the INT_PIN this device uses */ + pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0x7; + + /* Get the INT_LINE this device/function will use */ + int_line = ir->pic[pirq]; + + if (int_line != PIRQ_PIC_IRQDISABLE) { + /* Set this IRQ to level triggered since it is used by a PCI device */ + i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); + /* Set the Interrupt Line register in PCI config space */ + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + } else { + /* Set the Interrupt line register as "unknown or unused" */ + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, + PIRQ_PIC_UNKNOWN_UNUSED); + } + + printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", + original_int_pin, pin_to_str(original_int_pin)); + if (parent_bdf != current_bdf) + printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", + new_int_pin, pin_to_str(new_int_pin)); + printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n" + "\tINT_LINE\t: 0x%X (IRQ %d)\n", + 'A' + pirq, int_line, int_line); + } + printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); +} + static inline int io_range_in_default(int base, int size) { /* Does it start above the range? */ @@ -161,7 +261,6 @@ const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1); - void *actl = (void *)(ILB_BASE_ADDRESS + ACTL); const struct soc_irq_route *ir = &global_soc_irq_route; struct soc_intel_braswell_config *config = dev->chip_info; @@ -178,8 +277,14 @@ write16((void *)(ir_base + i*sizeof(ir->pcidev[i])), ir->pcidev[i]); - /* Route SCI to IRQ9 */ - write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); + /* Interrupt 9 should be level triggered (SCI) */ + i8259_configure_irq_trigger(9, 1); + + for (i = 0; i < NUM_PIRQS; i++) { + if ( ir->pic[i] ) { + i8259_configure_irq_trigger(ir->pic[i], 1); + } + } sc_rtc_init(); @@ -192,6 +297,11 @@ read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); } + /* Write IRQ assignments to PCI config space */ + write_pci_config_irqs(); + + /* Initialize i8259 pic */ + setup_i8259(); } /* -- To view, visit https://review.coreboot.org/29419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I128cb35dd0e348a9cd9fb162651e0aa2b7e4a3ef Gerrit-Change-Number: 29419 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

1 0

Change in coreboot[master]: mb/lenovo/t400: Improve docking code
by Patrick Rudolph (Code Review) 01 Nov '18

01 Nov '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/29418 Change subject: mb/lenovo/t400: Improve docking code ...................................................................... mb/lenovo/t400: Improve docking code * Remove dead code * Add support for types 2504 and 2505 * Print dock info at romstage entry * Improve dock disconnect for type 2505 * Move defines into dock.h for future ACPI code * Reduce timeouts according to spec to decrease boot time on error * Fix no docking detection (reduces boot time by 1 second) * Configure GPIO LDN before reading GPIOs Tested on Lenovo T500 with docking 2504 and 2505. Change-Id: Ic4510ffadc67da95961cecd51a6d8ed856b3ac99 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/lenovo/t400/dock.c M src/mainboard/lenovo/t400/dock.h M src/mainboard/lenovo/t400/romstage.c 3 files changed, 79 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/29418/1 diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c index 0c6db0b..fa33337 100644 --- a/src/mainboard/lenovo/t400/dock.c +++ b/src/mainboard/lenovo/t400/dock.c @@ -34,10 +34,8 @@ u8 mode; }; -static int poll_clk_stable(pnp_devfn_t dev) +static int poll_clk_stable(pnp_devfn_t dev, int timeout) { - int timeout = 1000; - /* Enable 14.318MHz CLK on CLKIN */ pnp_write_config(dev, 0x29, 0xa0); while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) @@ -69,20 +67,10 @@ static const pnp_devfn_t l_dlpc = PNP_DEV(0x164e, PC87382_DOCK); static const pnp_devfn_t l_gpio = PNP_DEV(0x164e, PC87382_GPIO); -#define DLPC_CONTROL 0x164c -#define DLPC_GPIO_BASE 0x1680 - -#define DLPC_GPDO0 (DLPC_GPIO_BASE + 0x0) -#define DLPC_GPDI0 (DLPC_GPIO_BASE + 0x1) -#define D_PLTRST 0x01 -#define D_LPCPD 0x02 - -#define DLPC_GPDO2 (DLPC_GPIO_BASE + 0x8) -#define DLPC_GPDI2 (DLPC_GPIO_BASE + 0x9) - static int pc87382_init(pnp_devfn_t dlpc, u16 dlpc_base) { - int timeout = 1000; + /* Maximum 3300 LCLKs at 14.318MHz */ + int timeout = 230; /* Enable LPC bridge LDN. */ pnp_set_logical_device(dlpc); @@ -93,7 +81,7 @@ outb(0x00, dlpc_base); outb(0x07, dlpc_base); while (!(inb(dlpc_base) & 8) && timeout--) - udelay(1000); + udelay(1); if (!timeout) return 1; @@ -106,8 +94,10 @@ /* Disconnect LPC bus */ u16 dlpc_base = pnp_read_iobase(dlpc, PNP_IDX_IO0); - outb(0x00, dlpc_base); - pnp_set_enable(dlpc, 0); + if (dlpc_base) { + outb(0x00, dlpc_base); + pnp_set_enable(dlpc, 0); + } } static const struct pin_config local_gpio[] = { @@ -115,18 +105,26 @@ {0x04, 4}, {0x20, 4}, {0x21, 4}, {0x23, 4}, }; -static int pc87382_connect(void) +/* Enable internal clock and configure GPIO LDN */ +int pc87382_early(void) { - u8 reg; - - if (poll_clk_stable(l_gpio) != 0) + /* Wake-up time is 33 msec (maximum). */ + if (poll_clk_stable(l_gpio, 33) != 0) return 1; + /* Set up GPIOs */ if (gpio_init(l_gpio, DLPC_GPIO_BASE, local_gpio, ARRAY_SIZE(local_gpio)) != 0) { return 1; } + return 0; +} + +static int pc87382_connect(void) +{ + u8 reg; + reg = inb(DLPC_GPDO0); reg |= D_PLTRST | D_LPCPD; /* Deassert D_PLTRST# and D_LPCPD# */ @@ -158,10 +156,12 @@ outb(reg, DLPC_GPDO0); } +/* Returns 3bit dock id */ static u8 dock_identify(void) { u8 id; + /* Make sure GPIO LDN is configured first ! */ id = (inb(DLPC_GPDI0) >> 4) & 1; id |= (inb(DLPC_GPDI2) & 3) << 1; @@ -172,10 +172,8 @@ #include <superio/nsc/pc87384/pc87384.h> -static const pnp_devfn_t r_gpio = PNP_DEV(0x2e, PC87384_GPIO); -static const pnp_devfn_t r_serial = PNP_DEV(0x2e, PC87384_SP1); - -#define DOCK_GPIO_BASE 0x1620 +static const pnp_devfn_t r_gpio = PNP_DEV(SUPERIO_DEV, PC87384_GPIO); +static const pnp_devfn_t r_serial = PNP_DEV(SUPERIO_DEV, PC87384_SP1); static const struct pin_config remote_gpio[] = { {0x00, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, @@ -190,7 +188,7 @@ static int pc87384_init(void) { - if (poll_clk_stable(r_gpio) != 0) + if (poll_clk_stable(r_gpio, 1000) != 0) return 1; /* set GPIO pins to Serial/Parallel Port @@ -199,9 +197,11 @@ pnp_write_config(r_gpio, 0x22, 0xa9); /* enable serial port */ - pnp_set_logical_device(r_serial); - pnp_set_iobase(r_serial, PNP_IDX_IO0, 0x3f8); - pnp_set_enable(r_serial, 1); + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + pnp_set_logical_device(r_serial); + pnp_set_iobase(r_serial, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_enable(r_serial, 1); + } if (gpio_init(r_gpio, DOCK_GPIO_BASE, remote_gpio, ARRAY_SIZE(remote_gpio)) != 0) @@ -228,14 +228,16 @@ void dock_connect(void) { - if (dock_identify() == 0) + const u8 id = dock_identify(); + + /* Dock type 2505 doesn't have serial, LPT port or LEDs */ + if (id == DOCK_TYPE_NONE || id == DOCK_TYPE_2505) return; - if (pc87382_connect() != 0) { + if (pc87382_connect() != 0 || pc87384_init() != 0) { pc87382_disconnect(); return; } - pc87384_init(); ec_write(H8_LED_CONTROL, H8_LED_CONTROL_OFF | H8_LED_CONTROL_DOCK_LED1); @@ -253,13 +255,12 @@ H8_LED_CONTROL_OFF | H8_LED_CONTROL_DOCK_LED2); } -void h8_mainboard_init_dock(void) +void dock_info(void) { - u8 id = dock_identify(); + const u8 id = dock_identify(); - if (id != 0) { - printk(BIOS_DEBUG, "dock (id=%d) is present\n", id); - dock_connect(); - } else - printk(BIOS_DEBUG, "dock is not connected\n"); + if (id != DOCK_TYPE_NONE) + printk(BIOS_DEBUG, "DOCK: is present: id=%d\n", id); + else + printk(BIOS_DEBUG, "DOCK: not connected\n"); } diff --git a/src/mainboard/lenovo/t400/dock.h b/src/mainboard/lenovo/t400/dock.h index 74b730c..d94cb9e 100644 --- a/src/mainboard/lenovo/t400/dock.h +++ b/src/mainboard/lenovo/t400/dock.h @@ -16,7 +16,34 @@ #ifndef THINKPAD_T400_DOCK_H #define THINKPAD_T400_DOCK_H +#if ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_SMM +int pc87382_early(void); + void dock_connect(void); void dock_disconnect(void); int dock_present(void); +void dock_info(void); +#endif + +/* pc87382 */ +#define DLPC_CONTROL 0x164c +#define DLPC_GPIO_BASE 0x1680 + +#define DLPC_GPDO0 (DLPC_GPIO_BASE + 0x0) +#define DLPC_GPDI0 (DLPC_GPIO_BASE + 0x1) +#define D_PLTRST 0x01 +#define D_LPCPD 0x02 + +#define DLPC_GPDO2 (DLPC_GPIO_BASE + 0x8) +#define DLPC_GPDI2 (DLPC_GPIO_BASE + 0x9) + + /* Pullups on all GPIOs, dock pulls ID pins low */ +#define DOCK_TYPE_2504 1 +#define DOCK_TYPE_2505 2 +#define DOCK_TYPE_NONE 7 + +/* pc87384 */ +#define SUPERIO_DEV 0x2e +#define DOCK_GPIO_BASE 0x1620 + #endif diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 7bf14bf..01886dd 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -66,6 +66,7 @@ sysinfo_t sysinfo; int s3resume = 0; int cbmem_initted; + int err; u16 reg16; timestamp_init(get_initial_timestamp()); @@ -81,11 +82,20 @@ i82801ix_early_init(); early_lpc_setup(); - dock_connect(); + /* Minimal setup to detect dock */ + err = pc87382_early(); + if (err == 0) + dock_connect(); console_init(); printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist); + /* Print dock info */ + if (err) + printk(BIOS_ERR, "DOCK: Failed to init pc87382\n"); + + dock_info(); + reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) { -- To view, visit https://review.coreboot.org/29418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic4510ffadc67da95961cecd51a6d8ed856b3ac99 Gerrit-Change-Number: 29418 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code
by Frans Hendriks (Code Review) 01 Nov '18

01 Nov '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29417 Change subject: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code ...................................................................... src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code Linux remains using SPI1 and PWM ASL even if these devices are disabled. SPI1 and PWM are disabled by standard Intel FSP. Remove ASL code when standard Intel FSP is used. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/acpi/lpss.asl 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29417/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 2ba7992..4723682 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -127,4 +127,16 @@ string default "soc/intel/braswell/bootblock/timestamp.inc" +config ENABLE_SPI1_ASL + bool "Include ASL code for SPI1 device" + default y + help + Enable this if the SPI1 are supported + This device is disabled in Intel FSP. +config ENABLE_PWM_ASL + bool "Include ASL code for PWM devices" + default y + help + Enable this if the PWM interfaces are supported + This device is disabled in Intel FSP. endif diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl index 4cc93cc..19ff1e9 100644 --- a/src/soc/intel/braswell/acpi/lpss.asl +++ b/src/soc/intel/braswell/acpi/lpss.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -522,6 +523,7 @@ } } +#if IS_ENABLED(CONFIG_ENABLE_SPI1_ASL) Device (SPI1) { Name (_HID, "8086228E") @@ -574,7 +576,9 @@ Or (PSAT, 0x00000000, PSAT) } } +#endif +#if IS_ENABLED(CONFIG_ENABLE_PWM_ASL) Device (PWM1) { Name (_HID, "80862288") @@ -630,6 +634,7 @@ } } } +#endif Device (UAR1) { -- To view, visit https://review.coreboot.org/29417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606 Gerrit-Change-Number: 29417 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: src/soc/intel/braswell/southcluster.c: Config i8254 timer
by Frans Hendriks (Code Review) 01 Nov '18

01 Nov '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29416 Change subject: src/soc/intel/braswell/southcluster.c: Config i8254 timer ...................................................................... src/soc/intel/braswell/southcluster.c: Config i8254 timer ISA timer is not configured. Add call setup_i8254(). BUG=N/A TEST=Intel CherryHill CRB Change-Id: If45c4975d147f28a456198ea290efba1c8b0464b Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/southcluster.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/29416/1 diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index ca87d63..a509a4e 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -27,6 +27,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> +#include <pc80/i8254.h> #include <romstage_handoff.h> #include <soc/acpi.h> #include <soc/iomap.h> @@ -192,6 +193,8 @@ read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); } + /* Initialize i8254 timers */ + setup_i8254(); } /* -- To view, visit https://review.coreboot.org/29416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If45c4975d147f28a456198ea290efba1c8b0464b Gerrit-Change-Number: 29416 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: src: Add missing include <stdint.h>
by Elyes HAOUAS (Code Review) 01 Nov '18

01 Nov '18

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29403 to look at the new patch set (#7). Change subject: src: Add missing include <stdint.h> ...................................................................... src: Add missing include <stdint.h> This is part #2 follows Change-Id: I6a9d71e69 Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/common/common.h M src/cpu/intel/haswell/chip.h M src/device/oprom/yabel/compat/time.h M src/drivers/pc80/tpm/chip.h M src/ec/smsc/mec1308/chip.h M src/include/device/path.h M src/include/device/pcix.h M src/mainboard/google/parrot/ec.h M src/mainboard/roda/rk886ex/m3885.h M src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h M src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h M src/mainboard/siemens/mc_tcu3/lcd_panel.h M src/northbridge/amd/agesa/family14/chip.h M src/northbridge/amd/agesa/family15tn/chip.h M src/northbridge/amd/agesa/family16kb/chip.h M src/northbridge/amd/amdfam10/northbridge.h M src/northbridge/amd/amdht/AsPsNb.h M src/northbridge/amd/pi/00630F01/chip.h M src/northbridge/amd/pi/00660F01/chip.h M src/northbridge/amd/pi/00730F01/chip.h M src/northbridge/intel/pineview/raminit.h M src/northbridge/intel/x4x/iomap.h M src/soc/cavium/common/pci/chip.h M src/soc/intel/broadwell/include/soc/xhci.h M src/soc/nvidia/tegra210/include/soc/display.h M src/soc/nvidia/tegra210/include/soc/tegra_dsi.h M src/soc/rockchip/common/include/soc/pwm.h M src/soc/rockchip/rk3288/include/soc/display.h M src/soc/rockchip/rk3399/include/soc/saradc.h M src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h M src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h M src/southbridge/amd/agesa/hudson/chip.h M src/southbridge/amd/cimx/sb800/sb_cimx.h M src/southbridge/amd/cimx/sb900/sb_cimx.h M src/southbridge/amd/sb700/chip.h M src/southbridge/intel/common/pciehp.h M src/superio/fintek/f81216h/f81216h.h M src/superio/nuvoton/nct5104d/chip.h M src/superio/serverengines/pilot/pilot.h M src/superio/smsc/lpc47n227/lpc47n227.h 40 files changed, 81 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/29403/7 -- To view, visit https://review.coreboot.org/29403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Gerrit-Change-Number: 29403 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/soc/intel/braswell/southcluster.c: Config ISA DMA controller
by Frans Hendriks (Code Review) 01 Nov '18

01 Nov '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29415 Change subject: src/soc/intel/braswell/southcluster.c: Config ISA DMA controller ...................................................................... src/soc/intel/braswell/southcluster.c: Config ISA DMA controller ISA dma controller is not configured. Add call isa_dma_init(). BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ib7af3f4ef6d6a29628bb2c27d32071be63ff6af2 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/southcluster.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/29415/1 diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index ca87d63..44f1626 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -26,6 +26,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <pc80/isa-dma.h> #include <pc80/mc146818rtc.h> #include <romstage_handoff.h> #include <soc/acpi.h> @@ -168,6 +169,8 @@ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); + isa_dma_init(); + /* Set up the PIRQ PIC routing based on static config. */ for (i = 0; i < NUM_PIRQS; i++) write8((void *)(pr_base + i*sizeof(ir->pic[i])), -- To view, visit https://review.coreboot.org/29415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib7af3f4ef6d6a29628bb2c27d32071be63ff6af2 Gerrit-Change-Number: 29415 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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coreboot-gerrit November 2018