coreboot-gerrit November 2018

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Change in coreboot[master]: SMBIOS: [test] Upgrade to 3.20
by Elyes HAOUAS (Code Review) 14 Nov '18

14 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29641 Change subject: SMBIOS: [test] Upgrade to 3.20 ...................................................................... SMBIOS: [test] Upgrade to 3.20 Change-Id: I8bccedd277beb755b643a663f3278af25f8fbf96 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/smbios.c M src/include/smbios.h M src/mainboard/samsung/lumpy/mainboard.c 3 files changed, 54 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/29641/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index babe61b..154991a 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -670,11 +670,10 @@ t->length = len - 2; t->reference_designation = smbios_add_string(t->eos, name); t->device_type = SMBIOS_DEVICE_TYPE_OTHER; - t->device_status = 1; t->device_type_instance = instance; t->segment_group_number = segment; t->bus_number = bus; - t->device_number = device; + t->device_function_number = (device << 3) | (function << 0); t->function_number = function; len = t->length + smbios_string_table_len(t->eos); @@ -764,20 +763,16 @@ handle++)); memset(se, 0, sizeof(struct smbios_entry)); - memcpy(se->anchor, "_SM_", 4); + memcpy(se->anchor, "_SM3_", 5); se->length = sizeof(struct smbios_entry); - se->major_version = 2; - se->minor_version = 7; + se->major_version = 3; + se->minor_version = 2; + se->docrev = 0; se->max_struct_size = max_struct_size; - se->struct_count = handle; - memcpy(se->intermediate_anchor_string, "_DMI_", 5); - se->struct_table_address = (u32)tables; + se->struct_table_address = (u64)tables; se->struct_table_length = len; - se->intermediate_checksum = smbios_checksum((u8 *)se + 0x10, - sizeof(struct smbios_entry) - - 0x10); se->checksum = smbios_checksum((u8 *)se, sizeof(struct smbios_entry)); return current; } diff --git a/src/include/smbios.h b/src/include/smbios.h index 91777e3..eaabb99 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -52,18 +52,25 @@ const char *smbios_mainboard_family(void); #endif -#define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) -#define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) -#define BIOS_CHARACTERISTICS_PNP (1 << 9) -#define BIOS_CHARACTERISTICS_APM (1 << 10) -#define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11) -#define BIOS_CHARACTERISTICS_SHADOW (1 << 12) -#define BIOS_CHARACTERISTICS_BOOT_FROM_CD (1 << 15) -#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT (1 << 16) -#define BIOS_CHARACTERISTICS_BIOS_SOCKETED (1 << 17) +#define BIOS_CHARACTERISTICS_ISA_SUPPORTED (1 << 4) +#define BIOS_CHARACTERISTICS_MCA_SUPPORTED (1 << 5) +#define BIOS_CHARACTERISTICS_EISA_SUPPORTED (1 << 6) +#define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) +#define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) +#define BIOS_CHARACTERISTICS_PNP (1 << 9) +#define BIOS_CHARACTERISTICS_APM (1 << 10) +#define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11) +#define BIOS_CHARACTERISTICS_SHADOW (1 << 12) +#define BIOS_CHARACTERISTICS_VL_VESA_SUPPORTED (1 << 13) +#define BIOS_CHARACTERISTICS_ESCD_SUPPORT_AVAILABLE (1 << 14) +#define BIOS_CHARACTERISTICS_BOOT_FROM_CD (1 << 15) +#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT (1 << 16) +#define BIOS_CHARACTERISTICS_BIOS_SOCKETED (1 << 17) +#define BIOS_CHARACTERISTICS_BOOT_FROM_PCMCIA (1 << 18) +#define BIOS_CHARACTERISTICS_EDD_SPEC_SUPPORTED (1 << 19) -#define BIOS_EXT1_CHARACTERISTICS_ACPI (1 << 0) -#define BIOS_EXT2_CHARACTERISTICS_TARGET (1 << 2) +#define BIOS_EXT1_CHARACTERISTICS_ACPI (1 << 0) +#define BIOS_EXT2_CHARACTERISTICS_TARGET (1 << 2) #define BIOS_MEMORY_ECC_SINGLE_BIT_CORRECTING (1 << 3) #define BIOS_MEMORY_ECC_DOUBLE_BIT_CORRECTING (1 << 4) @@ -83,7 +90,7 @@ #define MEMORY_TYPE_DETAIL_NON_VOLATILE (1 << 12) #define MEMORY_TYPE_DETAIL_REGISTERED (1 << 13) #define MEMORY_TYPE_DETAIL_UNBUFFERED (1 << 14) - +#define MEMORY_TYPE_DETAIL_LRDIMM (1 << 16) typedef enum { MEMORY_BUS_WIDTH_8 = 0, MEMORY_BUS_WIDTH_16 = 1, @@ -203,20 +210,18 @@ } smbios_struct_type_t; struct smbios_entry { - u8 anchor[4]; + u8 anchor[5]; u8 checksum; u8 length; u8 major_version; u8 minor_version; - u16 max_struct_size; + u8 docrev; u8 entry_point_rev; - u8 formwatted_area[5]; - u8 intermediate_anchor_string[5]; - u8 intermediate_checksum; + u8 reserved[1]; + u16 max_struct_size; u16 struct_table_length; - u32 struct_table_address; - u16 struct_count; - u8 smbios_bcd_revision; + u64 struct_table_address; + u8 eos[2]; } __packed; struct smbios_type0 { @@ -235,6 +240,7 @@ u8 system_bios_minor_release; u8 ec_major_release; u8 ec_minor_release; + u16 extended_bios_rom_size; u8 eos[2]; } __packed; @@ -282,6 +288,8 @@ u8 location_in_chassis; u16 chassis_handle; u8 board_type; + u8 count_contained_object_handles; + u16 contained_object_handles; u8 eos[2]; } __packed; @@ -342,6 +350,7 @@ u8 number_of_power_cords; u8 element_count; u8 element_record_length; + u8 contained_elements; u8 sku_number; u8 eos[2]; } __packed; @@ -373,6 +382,9 @@ u8 thread_count; u16 processor_characteristics; u16 processor_family2; + u16 core_count2; + u16 core_enabled2; + u16 thread_count2; u8 eos[2]; } __packed; @@ -398,6 +410,7 @@ u8 header_format; u8 log_type_descriptors; u8 log_type_descriptor_length; + u8 list_supported_event_log_type_descriptors; u8 eos[2]; } __packed; @@ -454,6 +467,17 @@ u16 minimum_voltage; u16 maximum_voltage; u16 configured_voltage; + u8 memory_technology; + u16 memory_operating_mode_capability; + u8 firmware_version; + 16 module_manufacturer_id; + u16 module_product_id; + u16 memory_sub_controller_manufacturer_id; + u16 memory_sub_controller_product_id; + u64 non-volatile_size; + u64 volatile_size; + u64 cache_size; + u64 logical_size; u8 eos[2]; } __packed; @@ -477,6 +501,7 @@ u64 base_address; u8 base_address_modifier; u8 irq; + u8 eos[2]; } __packed; enum smbios_bmc_interface_type { @@ -504,13 +529,11 @@ u8 length; u16 handle; u8 reference_designation; - u8 device_type: 7; - u8 device_status: 1; + u8 device_type; u8 device_type_instance; u16 segment_group_number; u8 bus_number; - u8 function_number: 3; - u8 device_number: 5; + u8 device_function_number; u8 eos[2]; } __packed; diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 8664217..76ddc49 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -57,12 +57,10 @@ t->length = len - 2; t->reference_designation = smbios_add_string(t->eos, name); t->device_type = SMBIOS_DEVICE_TYPE_OTHER; - t->device_status = 1; t->device_type_instance = irq; t->segment_group_number = 0; t->bus_number = addr; - t->function_number = 0; - t->device_number = 0; + t->device_function_number = 0; len = t->length + smbios_string_table_len(t->eos); *current += len; -- To view, visit https://review.coreboot.org/29641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8bccedd277beb755b643a663f3278af25f8fbf96 Gerrit-Change-Number: 29641 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: [WIP]: Filter cpp comments
by Nico Huber (Code Review) 14 Nov '18

14 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29640 Change subject: [WIP]: Filter cpp comments ...................................................................... [WIP]: Filter cpp comments Change-Id: I5fdaf8cacc26d990a7571bfe6c99a63a427d0944 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M toolchain.inc A util/scripts/cpp_filter_comments.sh 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29640/1 diff --git a/toolchain.inc b/toolchain.inc index ec57b5d..b934e65 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -23,6 +23,7 @@ export CCACHE_COMPILERCHECK=content export CCACHE_BASEDIR=$(top) +export CCACHE_PREFIX_CPP=$(top)/util/scripts/cpp_filter_comments.sh $(foreach arch,$(ARCH_SUPPORTED), \ $(eval CC_$(arch):=$(CCACHE) $(CC_$(arch)))) diff --git a/util/scripts/cpp_filter_comments.sh b/util/scripts/cpp_filter_comments.sh new file mode 100755 index 0000000..b11dcdb --- /dev/null +++ b/util/scripts/cpp_filter_comments.sh @@ -0,0 +1,3 @@ +#!/bin/env sh + +exec "$@" | grep -v '^# ' -- To view, visit https://review.coreboot.org/29640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5fdaf8cacc26d990a7571bfe6c99a63a427d0944 Gerrit-Change-Number: 29640 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: MAKE: MOAAAAAR $$$$$$$$
by Nico Huber (Code Review) 14 Nov '18

14 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29639 Change subject: MAKE: MOAAAAAR $$$$$$$$ ...................................................................... MAKE: MOAAAAAR $$$$$$$$ Change-Id: I19d3016e67f8930345e0da9564abcc5e5f8ab365 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Makefile M Makefile.inc 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/29639/1 diff --git a/Makefile b/Makefile index 1d4a488..5b3724c 100644 --- a/Makefile +++ b/Makefile @@ -320,7 +320,8 @@ $$(call src-to-obj,$1,$$(1).$2): $$(1).$2 $(KCONFIG_AUTOHEADER) $(4) @printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n" $(CC_$(1)) \ - -MMD $$$$(CPPFLAGS_$(1)) $$$$(CFLAGS_$(1)) -MT $$$$(@) \ + -MMD $$$$(CPPFLAGS_$(1)) $$$$(CFLAGS_$(1)) \ + -MT '$$$$(patsubst $(obj)/%,$$$$$$$$(obj)/%,$$$$(@))' \ $(3) -c -o $$$$@ $$$$< end$(EMPTY)if en$(EMPTY)def diff --git a/Makefile.inc b/Makefile.inc index aaae7bc..4f894d1 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -373,7 +373,7 @@ COREBOOT_EXPORTS += COREBOOT_EXTRA_VERSION endif -CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj) +CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -isystem $(obj) CPPFLAGS_common += -Isrc/device/oprom/include VBOOT_SOURCE ?= 3rdparty/vboot CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include -- To view, visit https://review.coreboot.org/29639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I19d3016e67f8930345e0da9564abcc5e5f8ab365 Gerrit-Change-Number: 29639 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: SMBIOS: Remove duplicated smbios_memory_type enum
by Elyes HAOUAS (Code Review) 14 Nov '18

14 Nov '18

1 0

Change in coreboot[master]: SMBIOS: Remove duplicated smbios_memory_type enum
by Richard Spiegel (Code Review) 14 Nov '18

14 Nov '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/29638 ) Change subject: SMBIOS: Remove duplicated smbios_memory_type enum ...................................................................... Patch Set 2: Code-Review+1 (2 comments) Some people would say this should be 2 separate commits, or have a title that clearly indicate both things. Why not "SMBIOS: Update to version 3.2.0"? Then you can add any other modification related to this version on the same commit. Over all looks good, but unless you break it in 2 commits or change the title to something that involves both actions (and possibly more), someone else will have to approve. https://review.coreboot.org/#/c/29638/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29638/2//COMMIT_MSG@9 PS2, Line 9: memory_speed > "memory speed" is the name done by SMBIOS version 3.2.0 […] Ok https://review.coreboot.org/#/c/29638/2/src/include/smbios.h File src/include/smbios.h: https://review.coreboot.org/#/c/29638/2/src/include/smbios.h@a122 PS2, Line 122: : : : : : > Please see line #140 (new file) OK, I see. -- To view, visit https://review.coreboot.org/29638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I49554d13f1b6371b85a58cc1263608ad9e99130e Gerrit-Change-Number: 29638 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Nov 2018 18:49:03 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: SMBIOS: Remove duplicated smbios_memory_type enum
by Elyes HAOUAS (Code Review) 14 Nov '18

14 Nov '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/29638 ) Change subject: SMBIOS: Remove duplicated smbios_memory_type enum ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/29638/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29638/2//COMMIT_MSG@9 PS2, Line 9: memory_speed > I would prefer mem_clock_frequency or mem_clk_freq. […] "memory speed" is the name done by SMBIOS version 3.2.0 ( https://www.dmtf.org/standards/smbios Document Identifier: DSP0134) Please see page #99: "Memory speed is expressed in megatransfers per second (MT/s). Previous revisions (3.0.0 and earlier) of this specification used MHz to indicate clock speed. With double data rate memory, clock speed is distinct from transfer rate, since data is transferred on both the rising and the falling edges of the clock signal. This maintains backward compatibility with observed DDR implementations prior to this revision, which already reported transfer rate instead of clock speed, e.g., DDR4-2133 (PC4-17000) memory was reported as 2133 instead of 1066." https://review.coreboot.org/#/c/29638/2/src/include/smbios.h File src/include/smbios.h: https://review.coreboot.org/#/c/29638/2/src/include/smbios.h@a122 PS2, Line 122: : : : : : > These memory types are not present at smbios_memory_type enum. They need to go there (renamed). Please see line #140 (new file) -- To view, visit https://review.coreboot.org/29638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I49554d13f1b6371b85a58cc1263608ad9e99130e Gerrit-Change-Number: 29638 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Nov 2018 18:10:16 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: SMBIOS: Remove duplicated smbios_memory_type enum
by Richard Spiegel (Code Review) 14 Nov '18

14 Nov '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/29638 ) Change subject: SMBIOS: Remove duplicated smbios_memory_type enum ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/29638/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29638/2//COMMIT_MSG@9 PS2, Line 9: memory_speed I would prefer mem_clock_frequency or mem_clk_freq. Something that clearly says memory clock frequency. clock_frequency would be acceptable too. Unless this defines transfer rate instead of clock (DDR has 2 transfers per clock cycle for example). Only then would memory_speed be acceptable. https://review.coreboot.org/#/c/29638/2/src/include/smbios.h File src/include/smbios.h: https://review.coreboot.org/#/c/29638/2/src/include/smbios.h@a122 PS2, Line 122: : : : : : These memory types are not present at smbios_memory_type enum. They need to go there (renamed). -- To view, visit https://review.coreboot.org/29638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I49554d13f1b6371b85a58cc1263608ad9e99130e Gerrit-Change-Number: 29638 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Nov 2018 17:58:26 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Add DRAM check for s3
by Marshall Dawson (Code Review) 14 Nov '18

14 Nov '18

Hello build bot (Jenkins), Daniel Kurtz, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29406 to look at the new patch set (#5). Change subject: soc/amd/stoneyridge: Add DRAM check for s3 ...................................................................... soc/amd/stoneyridge: Add DRAM check for s3 Allocate cbmem space to store DRAM check data during S3. Verify the the data is unchanged during the resume. Due to where the save and verify steps are placed, the test cannot capture 100% of potential memory corruption causes in coreboot. The ranges to verify are determined by the coreboot tables that are constructed at the end of POST. If a failure occurs within RAM available to the OS, the test reports "ERROR" to force suspend_stress_test to stop. Otherwise, the mismatch is reported as "FYI", e.g. in memory owned by coreboot. CAUTION: This test must not be deployed in a shipping system. It disables TSEG, and its protections, in order to allow the performance to be at an acceptable level. TODO: Add the capability of checking DRAM above 4GB. TEST=Suspend/resume grunt. Verify mismatch with induced error. BUG=b:118157730 Change-Id: I375dd7ea9a3ab8992f1616126bcbd9724e4fc9a0 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/pi/amd_resume_final.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/finalize.c M src/soc/amd/stoneyridge/include/soc/iomap.h A src/soc/amd/stoneyridge/include/soc/s3test_util.h A src/soc/amd/stoneyridge/s3test_util.c M src/soc/amd/stoneyridge/smihandler.c 8 files changed, 433 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/29406/5 -- To view, visit https://review.coreboot.org/29406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I375dd7ea9a3ab8992f1616126bcbd9724e4fc9a0 Gerrit-Change-Number: 29406 Gerrit-PatchSet: 5 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: SMBIOS: Remove duplicated smbios_memory_type enum
by Elyes HAOUAS (Code Review) 14 Nov '18

14 Nov '18

Hello Richard Spiegel, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29638 to look at the new patch set (#2). Change subject: SMBIOS: Remove duplicated smbios_memory_type enum ...................................................................... SMBIOS: Remove duplicated smbios_memory_type enum Also, rename "clock_speed" to "memory_speed" as per SMBIOS spec version 3.2.0 Change-Id: I49554d13f1b6371b85a58cc1263608ad9e99130e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/smbios.c M src/include/memory_info.h M src/include/smbios.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/google/cyan/spd/spd.c M src/northbridge/amd/amdfam10/northbridge.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 7 files changed, 17 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/29638/2 -- To view, visit https://review.coreboot.org/29638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I49554d13f1b6371b85a58cc1263608ad9e99130e Gerrit-Change-Number: 29638 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: SMBIOS: Remove duplicated smbios_memory_type enum
by Elyes HAOUAS (Code Review) 14 Nov '18

14 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29638 Change subject: SMBIOS: Remove duplicated smbios_memory_type enum ...................................................................... SMBIOS: Remove duplicated smbios_memory_type enum Also, rename "clock_speed" to "memory_speed" as per SMBIOS spec version 3.2.0 Change-Id: I49554d13f1b6371b85a58cc1263608ad9e99130e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/smbios.c M src/include/memory_info.h M src/include/smbios.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/google/cyan/spd/spd.c M src/northbridge/amd/amdfam10/northbridge.c M src/northbridge/intel/nehalem/raminit.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 8 files changed, 18 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/29638/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index c0545ce..babe61b 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -276,7 +276,7 @@ memset(t, 0, sizeof(struct smbios_type17)); t->memory_type = dimm->ddr_type; - t->clock_speed = dimm->ddr_frequency; + t->memory_speed = dimm->ddr_frequency; t->speed = dimm->ddr_frequency; t->type = SMBIOS_MEMORY_DEVICE; if (dimm->dimm_size < 0x7fff) { diff --git a/src/include/memory_info.h b/src/include/memory_info.h index 5976e31..93c7b6b 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -36,7 +36,7 @@ /* * SMBIOS (not SPD) device type. * - * See the smbios.h smbios_memory_device_type enum. + * See the smbios.h smbios_memory_type enum. */ uint16_t ddr_type; uint16_t ddr_frequency; diff --git a/src/include/smbios.h b/src/include/smbios.h index 574b924..91777e3 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -97,36 +97,6 @@ } smbios_memory_bus_width; typedef enum { - MEMORY_DEVICE_OTHER = 0x01, - MEMORY_DEVICE_UNKNOWN = 0x02, - MEMORY_DEVICE_DRAM = 0x03, - MEMORY_DEVICE_EDRAM = 0x04, - MEMORY_DEVICE_VRAM = 0x05, - MEMORY_DEVICE_SRAM = 0x06, - MEMORY_DEVICE_RAM = 0x07, - MEMORY_DEVICE_ROM = 0x08, - MEMORY_DEVICE_FLASH = 0x09, - MEMORY_DEVICE_EEPROM = 0x0A, - MEMORY_DEVICE_FEPROM = 0x0B, - MEMORY_DEVICE_EPROM = 0x0C, - MEMORY_DEVICE_CDRAM = 0x0D, - MEMORY_DEVICE_3DRAM = 0x0E, - MEMORY_DEVICE_SDRAM = 0x0F, - MEMORY_DEVICE_SGRAM = 0x10, - MEMORY_DEVICE_RDRAM = 0x11, - MEMORY_DEVICE_DDR = 0x12, - MEMORY_DEVICE_DDR2 = 0x13, - MEMORY_DEVICE_DDR2_FB_DIMM = 0x14, - MEMORY_DEVICE_DDR3 = 0x18, - MEMORY_DEVICE_DBD2 = 0x19, - MEMORY_DEVICE_DDR4 = 0x1A, - MEMORY_DEVICE_LPDDR = 0x1B, - MEMORY_DEVICE_LPDDR2 = 0x1C, - MEMORY_DEVICE_LPDDR3 = 0x1D, - MEMORY_DEVICE_LPDDR4 = 0x1E, -} smbios_memory_device_type; - -typedef enum { MEMORY_FORMFACTOR_OTHER = 0x01, MEMORY_FORMFACTOR_UNKNOWN = 0x02, MEMORY_FORMFACTOR_SIMM = 0x03, @@ -167,6 +137,12 @@ MEMORY_TYPE_DDR2_FBDIMM = 0x14, MEMORY_TYPE_DDR3 = 0x18, MEMORY_TYPE_FBD2 = 0x19, + MEMORY_TYPE_DDR4 = 0x1a, + MEMORY_TYPE_LPDDR = 0x1b, + MEMORY_TYPE_LPDDR2 = 0x1c, + MEMORY_TYPE_LPDDR3 = 0x1d, + MEMORY_TYPE_LPDDR4 = 0x1e, + MEMORY_TYPE_LOGICAL_NON_VOLATILE_DEVICE = 0x1f, } smbios_memory_type; typedef enum { @@ -474,7 +450,7 @@ u8 part_number; u8 attributes; u32 extended_size; - u16 clock_speed; + u16 memory_speed; u16 minimum_voltage; u16 maximum_voltage; u16 configured_voltage; diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 9d9225c..3eff307 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -202,7 +202,7 @@ t->memory_type = 0x12; /* DDR */ t->type_detail = 0x80; /* Synchronous */ t->speed = 200; - t->clock_speed = 200; + t->memory_speed = 200; t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); len = t->length + smbios_string_table_len(t->eos); *current += len; diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index 7682677..b7b0c30 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -138,9 +138,9 @@ /* Parse the SPD data to determine the DIMM information */ if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) { - dimm->ddr_type = MEMORY_DEVICE_DDR3; + dimm->ddr_type = MEMORY_TYPE_DDR3; } else { - dimm->ddr_type = MEMORY_DEVICE_LPDDR3; + dimm->ddr_type = MEMORY_TYPE_LPDDR3; } dimm->dimm_size = capmb / 8 * busw / devw * ranks; /* MiB */ dimm->mod_type = spd[3] & 0xf; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 4da5228..912d0a0 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1239,7 +1239,7 @@ else t->type_detail |= MEMORY_TYPE_DETAIL_UNBUFFERED; t->speed = max_speed; - t->clock_speed = speed; + t->memory_speed = speed; smbios_fill_dimm_manufacturer_from_id(mem_info->dct_stat[node].DimmManufacturerID[slot], t); t->part_number = smbios_add_string(t->eos, mem_info->dct_stat[node].DimmPartNumber[slot]); if (mem_info->dct_stat[node].DimmSerialNumber[slot] == 0) { diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index ee5a60b..6ef7ed7 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -185,7 +185,7 @@ #define gav(x) gav_real (__LINE__, (x)) struct raminfo { - u16 clock_speed_index; /* clock_speed (REAL, not DDR) / 133.(3) - 3 */ + u16 clock_speed_index; /* memory_speed (REAL, not DDR) / 133.(3) - 3 */ u16 fsb_frequency; /* in 1.(1)/2 MHz. */ u8 is_x16_module[2][2]; /* [CHANNEL][SLOT] */ u8 density[2][2]; /* [CHANNEL][SLOT] */ diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 0945780..eed9d8b 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -103,16 +103,16 @@ switch(memory_info_hob->MemoryType) { case MRC_DDR_TYPE_DDR4: - ddr_type = MEMORY_DEVICE_DDR4; + ddr_type = MEMORY_TYPE_DDR4; break; case MRC_DDR_TYPE_DDR3: - ddr_type = MEMORY_DEVICE_DDR3; + ddr_type = MEMORY_TYPE_DDR3; break; case MRC_DDR_TYPE_LPDDR3: - ddr_type = MEMORY_DEVICE_LPDDR3; + ddr_type = MEMORY_TYPE_LPDDR3; break; default: - ddr_type = MEMORY_DEVICE_UNKNOWN; + ddr_type = MEMORY_TYPE_UNKNOWN; break; } -- To view, visit https://review.coreboot.org/29638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I49554d13f1b6371b85a58cc1263608ad9e99130e Gerrit-Change-Number: 29638 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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coreboot-gerrit November 2018