coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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1699 discussions

Change in coreboot[master]: soc/intel/apollolake: Bump soc mem version
by Kane Chen (Code Review) 15 Nov '18

15 Nov '18

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/29647 Change subject: soc/intel/apollolake: Bump soc mem version ...................................................................... soc/intel/apollolake: Bump soc mem version This change is to bump fsp_memory_soc_version in order to trigger MRC full training BUG=b:119481870 Signed-off-by: Kane Chen <kane.chen(a)intel.com> Change-Id: I92463045f7a808fb25aaa7a2d5f6fcde36dfb458 --- M src/soc/intel/apollolake/meminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29647/1 diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 889bbde..431cdb6 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -367,5 +367,5 @@ uint8_t fsp_memory_soc_version(void) { /* Bump this value when the memory configuration parameters change. */ - return 1; + return 2; } -- To view, visit https://review.coreboot.org/29647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I92463045f7a808fb25aaa7a2d5f6fcde36dfb458 Gerrit-Change-Number: 29647 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>

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Change in coreboot[master]: cpu/intel/fsp_model_406dx: Remove unused FSP_MODEL_406DX_{A1, B0}
by Elyes HAOUAS (Code Review) 15 Nov '18

15 Nov '18

Elyes HAOUAS has abandoned this change. ( https://review.coreboot.org/29618 ) Change subject: cpu/intel/fsp_model_406dx: Remove unused FSP_MODEL_406DX_{A1,B0} ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/29618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I12ca33756c7d197de22d307448e27a504678537c Gerrit-Change-Number: 29618 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: tss: implement tlcl_save_state for running TPM_Shutdown(ST_STATE)
by Joel Kitching (Code Review) 15 Nov '18

15 Nov '18

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/29646 Change subject: tss: implement tlcl_save_state for running TPM_Shutdown(ST_STATE) ...................................................................... tss: implement tlcl_save_state for running TPM_Shutdown(ST_STATE) When an untrusted OS is running, we would like to use the Cr50 vendor-specific VENDOR_CC_TPM_MODE command to disable TPM. Before doing this, we should save TPM state. Implement tlcl_save_state for this purpose. This needs to live in coreboot codebase since on S3 resume path, depthcharge is not reached. BUG=b:70681930,b:118202153 TEST=None Signed-off-by: Joel Kitching <kitching(a)google.com> Change-Id: I8b51ca68456fc9b655e4dc2d0958b7c040d50510 --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 4 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/29646/1 diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index c053df9..9050ec8 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -102,6 +102,12 @@ uint32_t tlcl_resume(void); /** + * Send a TPM_Shutdown(ST_STATE). The TPM error code is returned (0 for + * success). + */ +uint32_t tlcl_save_state(void); + +/** * Run the self test. * * Note---this is synchronous. To run this in parallel with other firmware, diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index c67fdfa..e579bff 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -87,6 +87,35 @@ return tlcl_send_startup(TPM_SU_STATE); } +static uint32_t tlcl_send_shutdown(TPM_SU type) +{ + struct tpm2_shutdown shutdown; + struct tpm2_response *response; + + shutdown.shutdown_type = type; + response = tpm_process_command(TPM2_Shutdown, &shutdown); + + /* IO error, tpm2_response pointer is empty. */ + if (response == NULL) { + printk(BIOS_ERR, "%s: TPM communication error\n", __func__); + return TPM_E_IOERROR; + } + + printk(BIOS_INFO, "%s: Shutdown return code is %x\n", + __func__, response->hdr.tpm_code); + + if (response->hdr.tpm_code == TPM2_RC_SUCCESS) + return TPM_SUCCESS; + + /* Collapse any other errors into TPM_E_IOERROR. */ + return TPM_E_IOERROR; +} + +uint32_t tlcl_save_state(void) +{ + return tlcl_send_shutdown(TPM_SU_STATE); +} + uint32_t tlcl_assert_physical_presence(void) { /* diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index ad23d9b..af57248 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -28,6 +28,11 @@ return obuf_write_be16(ob, cmd_body->startup_type); } +static int marshal_shutdown(struct obuf *ob, struct tpm2_shutdown *cmd_body) +{ + return obuf_write_be16(ob, cmd_body->shutdown_type); +} + static int marshal_get_capability(struct obuf *ob, struct tpm2_get_capability *cmd_body) { @@ -302,6 +307,10 @@ rc |= marshal_startup(ob, tpm_command_body); break; + case TPM2_Shutdown: + rc |= marshal_shutdown(ob, tpm_command_body); + break; + case TPM2_GetCapability: rc |= marshal_get_capability(ob, tpm_command_body); break; @@ -499,6 +508,9 @@ case TPM2_Startup: break; + case TPM2_Shutdown: + break; + case TPM2_GetCapability: rc |= unmarshal_get_capability(ib, &tpm2_resp->gc); break; diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index e902f3c..12c84e1 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -71,6 +71,7 @@ #define TPM2_NV_WriteLock ((TPM_CC)0x00000138) #define TPM2_SelfTest ((TPM_CC)0x00000143) #define TPM2_Startup ((TPM_CC)0x00000144) +#define TPM2_Shutdown ((TPM_CC)0x00000145) #define TPM2_NV_Read ((TPM_CC)0x0000014E) #define TPM2_GetCapability ((TPM_CC)0x0000017A) #define TPM2_PCR_Extend ((TPM_CC)0x00000182) -- To view, visit https://review.coreboot.org/29646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8b51ca68456fc9b655e4dc2d0958b7c040d50510 Gerrit-Change-Number: 29646 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com>

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Change in coreboot[master]: siemens/mc_apl5: Add new mainboard variant mc_apl5
by Elyes HAOUAS (Code Review) 15 Nov '18

15 Nov '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/29635 ) Change subject: siemens/mc_apl5: Add new mainboard variant mc_apl5 ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29635/2/src/mainboard/siemens/mc_apl1/varia… File src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig: https://review.coreboot.org/#/c/29635/2/src/mainboard/siemens/mc_apl1/varia… PS2, Line 14: default "variants/mc_apl5/devicetree.cb" please see https://review.coreboot.org/#/c/coreboot/+/29595/ -- To view, visit https://review.coreboot.org/29635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icdbb116a822ffa7a3bfb7026a5d1164db56a0c46 Gerrit-Change-Number: 29635 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 15 Nov 2018 09:05:27 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: SMBIOS: Remove duplicated smbios_memory_type enum
by Patrick Rudolph (Code Review) 15 Nov '18

15 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29638 ) Change subject: SMBIOS: Remove duplicated smbios_memory_type enum ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/29638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I49554d13f1b6371b85a58cc1263608ad9e99130e Gerrit-Change-Number: 29638 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Nov 2018 08:59:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: siemens/mc_apl5: Add new mainboard variant mc_apl5
by Mario Scheithauer (Code Review) 15 Nov '18

15 Nov '18

Hello Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29635 to look at the new patch set (#2). Change subject: siemens/mc_apl5: Add new mainboard variant mc_apl5 ...................................................................... siemens/mc_apl5: Add new mainboard variant mc_apl5 This mainboard is based on mc_apl1. In a first step, it contains a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl5 mainboard will follow in separate commits. Change-Id: Icdbb116a822ffa7a3bfb7026a5d1164db56a0c46 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/Kconfig.name A src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig A src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb A src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h A src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c A src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c 8 files changed, 521 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/29635/2 -- To view, visit https://review.coreboot.org/29635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icdbb116a822ffa7a3bfb7026a5d1164db56a0c46 Gerrit-Change-Number: 29635 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/octopus: Set IOSSTATE to 9 for interrupt pins
by build bot (Jenkins) (Code Review) 15 Nov '18

15 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29645 ) Change subject: mb/google/octopus: Set IOSSTATE to 9 for interrupt pins ...................................................................... Patch Set 1: (5 comments) https://review.coreboot.org/#/c/29645/1/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/29645/1/src/mainboard/google/octopus/varian… PS1, Line 107: PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* Touch Panel Int */ line over 80 characters https://review.coreboot.org/#/c/29645/1/src/mainboard/google/octopus/varian… PS1, Line 109: PAD_CFG_GPI_APIC_IOS(GPIO_214, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* P_SENSOR_INT_L */ line over 80 characters https://review.coreboot.org/#/c/29645/1/src/mainboard/google/octopus/varian… PS1, Line 201: PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_137 -- HP_INT_ODL */ line over 80 characters https://review.coreboot.org/#/c/29645/1/src/mainboard/google/octopus/varian… PS1, Line 202: PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ line over 80 characters https://review.coreboot.org/#/c/29645/1/src/mainboard/google/octopus/varian… PS1, Line 203: PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ line over 80 characters -- To view, visit https://review.coreboot.org/29645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib7fccf0656ffca8c212d2ccd168f53ed41887763 Gerrit-Change-Number: 29645 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Nov 2018 08:12:15 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/octopus: Set IOSSTATE to 9 for interrupt pins
by Kane Chen (Code Review) 15 Nov '18

15 Nov '18

Kane Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/29645 ) Change subject: mb/google/octopus: Set IOSSTATE to 9 for interrupt pins ...................................................................... mb/google/octopus: Set IOSSTATE to 9 for interrupt pins According to EDS and architect's suggestion, we should set IOSTERM to 9 for interrupt pins to avoid unexpected wakeup during s0ix. BUG=b:113962641 TEST=verified pen and touchscreen are working even after s0ix Signed-off-by: Kane Chen <kane.chen(a)intel.com> Change-Id: Ib7fccf0656ffca8c212d2ccd168f53ed41887763 --- M src/mainboard/google/octopus/variants/baseboard/gpio.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/29645/2 -- To view, visit https://review.coreboot.org/29645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib7fccf0656ffca8c212d2ccd168f53ed41887763 Gerrit-Change-Number: 29645 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>

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Change in coreboot[master]: mb/google/octopus: Set IOSTERM to 9 for interrupt pins
by Kane Chen (Code Review) 15 Nov '18

15 Nov '18

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/29645 Change subject: mb/google/octopus: Set IOSTERM to 9 for interrupt pins ...................................................................... mb/google/octopus: Set IOSTERM to 9 for interrupt pins According to EDS and architect's suggestion, we should set IOSTERM to 9 for interrupt pins to avoid unexpected wakeup during s0ix. BUG=b:113962641 TEST=verified pen and touchscreen are working even after s0ix Signed-off-by: Kane Chen <kane.chen(a)intel.com> Change-Id: Ib7fccf0656ffca8c212d2ccd168f53ed41887763 --- M src/mainboard/google/octopus/variants/baseboard/gpio.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/29645/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 8af11bf..6eafc1c 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -104,9 +104,9 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PROCHOT_B */ PAD_NC(GPIO_211, UP_20K), /* EMMC_RST_B -- unused */ - PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* Touch Panel Int */ + PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* Touch Panel Int */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPI_APIC_IOS(GPIO_214, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* P_SENSOR_INT_L */ + PAD_CFG_GPI_APIC_IOS(GPIO_214, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* P_SENSOR_INT_L */ /* NORTH COMMUNITY GPIOS */ @@ -198,9 +198,9 @@ PAD_NC(GPIO_134, NONE),/* GPIO_134 -- unused */ PAD_CFG_GPI_IRQ_WAKE(GPIO_135, NONE, DEEP, LEVEL, INVERT),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_137 -- HP_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ // Also we may be able to use eSPI WAKE# Virtual Wire instead PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ -- To view, visit https://review.coreboot.org/29645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib7fccf0656ffca8c212d2ccd168f53ed41887763 Gerrit-Change-Number: 29645 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>

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Change in coreboot[master]: SMBIOS: [test] Upgrade to 3.2.0
by Elyes HAOUAS (Code Review) 15 Nov '18

15 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29641 to look at the new patch set (#8). Change subject: SMBIOS: [test] Upgrade to 3.2.0 ...................................................................... SMBIOS: [test] Upgrade to 3.2.0 Change-Id: I8bccedd277beb755b643a663f3278af25f8fbf96 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/smbios.c M src/include/smbios.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/samsung/lumpy/mainboard.c M src/northbridge/amd/amdfam10/northbridge.c 5 files changed, 100 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/29641/8 -- To view, visit https://review.coreboot.org/29641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8bccedd277beb755b643a663f3278af25f8fbf96 Gerrit-Change-Number: 29641 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit November 2018