coreboot-gerrit November 2018

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Change in coreboot[master]: mb/google/poppy/variants/nami: Invert FP MCU wake signal
by Shelley Chen (Code Review) 16 Nov '18

16 Nov '18

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/29650 Change subject: mb/google/poppy/variants/nami: Invert FP MCU wake signal ...................................................................... mb/google/poppy/variants/nami: Invert FP MCU wake signal GPP_D6 needs to be inverted to enter S0ix. Keeps device awake otherwise. BUG=b:119447525, b:115706071 BRANCH=Nami TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop into S0ix in the EC console. Change-Id: Iad5df124e2439bbdc078d6a33f8d0510d25ecf6f Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/poppy/variants/nami/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/29650/1 diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index 6b8b650..f48033a 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -426,7 +426,7 @@ /* D5 : ISH_I2C0_SDA ==> FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_D5, 0, DEEP), /* D6 : ISH_I2C0_SCL ==> FPMCU_INT_L */ - PAD_CFG_GPI_IRQ_WAKE(GPP_D6, 20K_PU, DEEP, LEVEL, NONE), + PAD_CFG_GPI_IRQ_WAKE(GPP_D6, 20K_PU, DEEP, LEVEL, INVERT), /* D17 : DMIC_CLK1 ==> NC */ PAD_CFG_NC(GPP_D17), }; -- To view, visit https://review.coreboot.org/29650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iad5df124e2439bbdc078d6a33f8d0510d25ecf6f Gerrit-Change-Number: 29650 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com>

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Change in coreboot[master]: mb/google/sarien: Set SMBIOS mainboard SKU
by Trent Begin (Code Review) 15 Nov '18

15 Nov '18

Trent Begin has posted comments on this change. ( https://review.coreboot.org/29649 ) Change subject: mb/google/sarien: Set SMBIOS mainboard SKU ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/29649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I03013bab89d53d1eba969c6ffb7e95fcbb315a81 Gerrit-Change-Number: 29649 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Trent Begin <tbegin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Nov 2018 23:33:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/sarien: Set SMBIOS mainboard SKU
by Furquan Shaikh (Code Review) 15 Nov '18

15 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29649 ) Change subject: mb/google/sarien: Set SMBIOS mainboard SKU ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I03013bab89d53d1eba969c6ffb7e95fcbb315a81 Gerrit-Change-Number: 29649 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Trent Begin <tbegin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Nov 2018 23:21:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/sarien: Set SMBIOS mainboard SKU
by Duncan Laurie (Code Review) 15 Nov '18

15 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29649 Change subject: mb/google/sarien: Set SMBIOS mainboard SKU ...................................................................... mb/google/sarien: Set SMBIOS mainboard SKU Setting sku_id() is not enough to get a value to show up in the SMBIOS tables, it also needs to be returned as a string for the table creation to consume. This change defines the smbios_mainboard_sku() function and returns a string constant of "sku#" as expected. Change-Id: I03013bab89d53d1eba969c6ffb7e95fcbb315a81 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/sku.c M src/mainboard/google/sarien/variants/arcada/include/variant/variant.h M src/mainboard/google/sarien/variants/sarien/include/variant/variant.h 3 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29649/1 diff --git a/src/mainboard/google/sarien/sku.c b/src/mainboard/google/sarien/sku.c index 9fc61a3..c064c02 100644 --- a/src/mainboard/google/sarien/sku.c +++ b/src/mainboard/google/sarien/sku.c @@ -14,9 +14,15 @@ */ #include <boardid.h> +#include <smbios.h> #include <variant/variant.h> uint32_t sku_id(void) { return VARIANT_SKU_ID; } + +const char *smbios_mainboard_sku(void) +{ + return VARIANT_SKU_NAME; +} diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h b/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h index f1e551a..d128432 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h @@ -18,5 +18,6 @@ /* Arcada is SKU ID 2 */ #define VARIANT_SKU_ID 2 +#define VARIANT_SKU_NAME "sku2" #endif diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h b/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h index d0be7fc..d367505 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h @@ -18,5 +18,6 @@ /* Sarien is SKU ID 1 */ #define VARIANT_SKU_ID 1 +#define VARIANT_SKU_NAME "sku1" #endif -- To view, visit https://review.coreboot.org/29649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I03013bab89d53d1eba969c6ffb7e95fcbb315a81 Gerrit-Change-Number: 29649 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: Stop charging with highest priority
by Nick Vaccaro (Code Review) 15 Nov '18

15 Nov '18

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/28723 ) Change subject: mb/google/poppy/variants/nocturne: Stop charging with highest priority ...................................................................... Patch Set 1: Is this still something that we need? -- To view, visit https://review.coreboot.org/28723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I22bf648ff31f7bdf0ce0d147399d4f566ccdddc3 Gerrit-Change-Number: 28723 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Nov 2018 22:03:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: tss: implement Cr50 vendor-specific VENDOR_CC_TPM_MODE
by build bot (Jenkins) (Code Review) 15 Nov '18

15 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29648 ) Change subject: tss: implement Cr50 vendor-specific VENDOR_CC_TPM_MODE ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29648/1/src/security/tpm/tss/tcg-2.0/tss_ma… File src/security/tpm/tss/tcg-2.0/tss_marshaling.c: https://review.coreboot.org/#/c/29648/1/src/security/tpm/tss/tcg-2.0/tss_ma… PS1, Line 482: break; break is not useful after a goto or return -- To view, visit https://review.coreboot.org/29648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idd55708797d2b17336fcbe80c0724957f7052e90 Gerrit-Change-Number: 29648 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Nov 2018 11:41:49 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: tss: implement Cr50 vendor-specific VENDOR_CC_TPM_MODE
by Joel Kitching (Code Review) 15 Nov '18

15 Nov '18

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/29648 Change subject: tss: implement Cr50 vendor-specific VENDOR_CC_TPM_MODE ...................................................................... tss: implement Cr50 vendor-specific VENDOR_CC_TPM_MODE When an untrusted OS is running, we would like to use the Cr50 vendor-specific VENDOR_CC_TPM_MODE command to disable TPM. This implements the "set" funtionality of this command, and exposes it as tlcl_cr50_set_tpm_mode. This needs to live in coreboot codebase since on S3 resume path, depthcharge is not reached. BUG=b:70681930,b:118202153 TEST=hack a call to tlcl_cr50_set_tpm_mode into coreboot on S3 resume verify in AP console that it is called verify that `tpm_version` fails to run Change-Id: Idd55708797d2b17336fcbe80c0724957f7052e90 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h M src/security/tpm/tss/vendor/cr50/cr50.c M src/security/tpm/tss/vendor/cr50/cr50.h 4 files changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/29648/1 diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index af57248..5f04c6d 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -273,6 +273,10 @@ rc |= obuf_write_be16(ob, sub_command[0]); rc |= obuf_write_be16(ob, sub_command[1]); break; + case TPM2_CR50_SUB_CMD_TPM_MODE: + rc |= obuf_write_be16(ob, sub_command[0]); + rc |= obuf_write_be8(ob, sub_command[1]); + break; default: /* Unsupported subcommand. */ printk(BIOS_WARNING, "Unsupported cr50 subcommand: 0x%04x\n", @@ -473,6 +477,9 @@ case TPM2_CR50_SUB_CMD_TURN_UPDATE_ON: return ibuf_read_be8(ib, &vcr->num_restored_headers); break; + case TPM2_CR50_SUB_CMD_TPM_MODE: + return ibuf_read_be8(ib, &vcr->tpm_mode); + break; default: printk(BIOS_ERR, "%s:%d - unsupported vendor command %#04x!\n", diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 12c84e1..2a49bef 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -293,6 +293,7 @@ uint16_t vc_subcommand; union { uint8_t num_restored_headers; + uint8_t tpm_mode; }; }; diff --git a/src/security/tpm/tss/vendor/cr50/cr50.c b/src/security/tpm/tss/vendor/cr50/cr50.c index 90f7963..bd28a69 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.c +++ b/src/security/tpm/tss/vendor/cr50/cr50.c @@ -52,3 +52,35 @@ *num_restored_headers = response->vcr.num_restored_headers; return TPM_SUCCESS; } + +uint32_t tlcl_cr50_set_tpm_mode(uint8_t mode) +{ + struct tpm2_response *response; + uint16_t command_body[] = { + TPM2_CR50_SUB_CMD_TPM_MODE, mode + }; + + printk(BIOS_INFO, "Setting cr50 TPM mode\n"); + + response = tpm_process_command(TPM2_CR50_VENDOR_COMMAND, command_body); + + if (response == NULL) { + printk(BIOS_ERR, "%s: communications error\n", __func__); + return TPM_E_COMMUNICATION_ERROR; + } + + if (response->hdr.tpm_code) { + printk(BIOS_ERR, "%s: invalid header code: %x\n", __func__, + response->hdr.tpm_code); + return TPM_E_IOERROR; + } + + if (response->vcr.tpm_mode != mode) { + printk(BIOS_ERR, + "%s: invalid TPM mode response: %d (expect %d)\n", + __func__, response->vcr.tpm_mode, mode); + return TPM_E_WRITE_FAILURE; + } + + return TPM_SUCCESS; +} diff --git a/src/security/tpm/tss/vendor/cr50/cr50.h b/src/security/tpm/tss/vendor/cr50/cr50.h index 9bf3bd5..682be70 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.h +++ b/src/security/tpm/tss/vendor/cr50/cr50.h @@ -25,6 +25,15 @@ #define TPM2_CR50_VENDOR_COMMAND ((TPM_CC)(TPM_CC_VENDOR_BIT_MASK | 0)) #define TPM2_CR50_SUB_CMD_NVMEM_ENABLE_COMMITS (21) #define TPM2_CR50_SUB_CMD_TURN_UPDATE_ON (24) +#define TPM2_CR50_SUB_CMD_TPM_MODE (40) + +/* TPM2_CR50_SUB_CMD_TPM_MODE return values (TPM modes) */ +enum { + TpmModeEnabledTentative = 0, /* TPM is enabled, can be changed */ + TpmModeEnabled = 1, /* TPM is enabled, cannot be changed */ + TpmModeDisabled = 2, /* TPM is disabled, cannot be changed */ + TpmModeMax, +}; /** * CR50 specific tpm command to enable nvmem commits before internal timeout @@ -44,4 +53,28 @@ uint32_t tlcl_cr50_enable_update(uint16_t timeout_ms, uint8_t *num_restored_headers); +/** + * CR50 specific tpm command to get/set the TPM mode. This function sets + * the mode and validates that it was updated successfully. If any of the + * following occur, the function fails: + * - TPM does not understand the instruction (old version) + * - TPM has already left the TpmModeEnabledTentative mode + * - TPM responds with a mode other than the requested mode + * - Some other communication error + * Otherwise, the function call succeeds. + * + * `mode` argument may be any of the following: + * - TpmModeEnabledTentative = 0 TPM is enabled, can be changed + * - TpmModeEnabled = 1 TPM is enabled, cannot be changed + * - TpmModeDisabled = 2 TPM is disabled, cannot be changed + * + * Returns TPM_SUCCESS on success and TPM_E_* on failure. + * + * Note that CR50 also implements a version of this command which simply + * returns the current TPM mode (differentiated by whether or not the 8-bit + * mode argument is attached to the vendor command), but only the "set" + * version is implemented here. + */ +uint32_t tlcl_cr50_set_tpm_mode(uint8_t mode); + #endif /* CR50_TSS_STRUCTURES_H_ */ -- To view, visit https://review.coreboot.org/29648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idd55708797d2b17336fcbe80c0724957f7052e90 Gerrit-Change-Number: 29648 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com>

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Change in coreboot[master]: drivers/intel/fsp1_1: Remove unused DISPLAY_FAST_BOOT_DATA
by Felix Held (Code Review) 15 Nov '18

15 Nov '18

Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/29617 ) Change subject: drivers/intel/fsp1_1: Remove unused DISPLAY_FAST_BOOT_DATA ...................................................................... drivers/intel/fsp1_1: Remove unused DISPLAY_FAST_BOOT_DATA Change-Id: I405b79ee192317c86725f9bf0b1d166c045d30e2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/29617 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/drivers/intel/fsp1_1/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index a70f00d..13de66c 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -59,10 +59,6 @@ value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool). -config DISPLAY_FAST_BOOT_DATA - bool "Display fast boot data" - default n - config DISPLAY_HOBS bool "Display hand-off-blocks (HOBs)" default n -- To view, visit https://review.coreboot.org/29617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I405b79ee192317c86725f9bf0b1d166c045d30e2 Gerrit-Change-Number: 29617 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: oc/intel/quark/Kconfig: Remove unused MMCOMF_SUPPORT_DEFAULT
by Felix Held (Code Review) 15 Nov '18

15 Nov '18

Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/29609 ) Change subject: oc/intel/quark/Kconfig: Remove unused MMCOMF_SUPPORT_DEFAULT ...................................................................... oc/intel/quark/Kconfig: Remove unused MMCOMF_SUPPORT_DEFAULT Change-Id: I24596b7b4f3e7caef7f42e4317a786caa42c5c2d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/29609 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/soc/intel/quark/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 232dc4f..adf545d 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -41,10 +41,6 @@ select UNCOMPRESSED_RAMSTAGE select USE_MARCH_586 -config MMCOMF_SUPPORT_DEFAULT - bool - default n - ##### # Debug serial output # The following options configure the debug serial port -- To view, visit https://review.coreboot.org/29609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I24596b7b4f3e7caef7f42e4317a786caa42c5c2d Gerrit-Change-Number: 29609 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/apollolake: Bump soc mem version
by Kane Chen (Code Review) 15 Nov '18

15 Nov '18

Kane Chen has posted comments on this change. ( https://review.coreboot.org/29647 ) Change subject: soc/intel/apollolake: Bump soc mem version ...................................................................... Patch Set 1: it's still under discussion. -- To view, visit https://review.coreboot.org/29647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I92463045f7a808fb25aaa7a2d5f6fcde36dfb458 Gerrit-Change-Number: 29647 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Thu, 15 Nov 2018 09:57:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit November 2018