coreboot-gerrit November 2018

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Change in coreboot[master]: mb/{lenovo, roda}: Remove DISPLAY_DEVICE_2_IS_LCD_SCREEN macro
by Patrick Georgi (Code Review) 16 Nov '18

16 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29537 ) Change subject: mb/{lenovo,roda}: Remove DISPLAY_DEVICE_2_IS_LCD_SCREEN macro ...................................................................... mb/{lenovo,roda}: Remove DISPLAY_DEVICE_2_IS_LCD_SCREEN macro This macro is no longer used since commit dd2bc3f8 with Change-Id I556769e5e28b83e7465e3db689e26c8c0ab44757 ("igd.asl rewrite"). Change-Id: Iabf927d8462673cb96851c01318d826d4c422e0d Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Reviewed-on: https://review.coreboot.org/29537 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/t400/dsdt.asl M src/mainboard/lenovo/x200/dsdt.asl M src/mainboard/roda/rk9/dsdt.asl 3 files changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Elyes HAOUAS: Looks good to me, approved diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index 6ba4774..c9f4c08 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -18,7 +18,6 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define DISPLAY_DEVICE_2_IS_LCD_SCREEN 1 DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index 5452fe3..42fcab3 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -18,7 +18,6 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define DISPLAY_DEVICE_2_IS_LCD_SCREEN 1 DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/roda/rk9/dsdt.asl b/src/mainboard/roda/rk9/dsdt.asl index 5c5ca2f..dee3cf4 100644 --- a/src/mainboard/roda/rk9/dsdt.asl +++ b/src/mainboard/roda/rk9/dsdt.asl @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#define DISPLAY_DEVICE_2_IS_LCD_SCREEN 1 - DefinitionBlock( "dsdt.aml", "DSDT", -- To view, visit https://review.coreboot.org/29537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Iabf927d8462673cb96851c01318d826d4c422e0d Gerrit-Change-Number: 29537 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/*/*/Kconfig: Don't specify devicetree path if default val used
by Patrick Georgi (Code Review) 16 Nov '18

16 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29625 ) Change subject: mb/*/*/Kconfig: Don't specify devicetree path if default val used ...................................................................... mb/*/*/Kconfig: Don't specify devicetree path if default val used Change-Id: I3d77a625c5ece7b7ea5476fe0bd42829d1fc72c4 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Reviewed-on: https://review.coreboot.org/29625 Reviewed-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/cavium/cn8100_sff_evb/Kconfig M src/mainboard/google/gru/Kconfig M src/mainboard/intel/leafhill/Kconfig M src/mainboard/opencellular/elgon/Kconfig 4 files changed, 0 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Elyes HAOUAS: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/cavium/cn8100_sff_evb/Kconfig b/src/mainboard/cavium/cn8100_sff_evb/Kconfig index b95ddf6..0cb6f5a 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/Kconfig +++ b/src/mainboard/cavium/cn8100_sff_evb/Kconfig @@ -61,9 +61,6 @@ ########################################################## #### Update below when adding a new derivative board. #### ########################################################## -config DEVICETREE - string - default "devicetree.cb" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index fee2dd0..49944a8 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -105,7 +105,6 @@ config DEVICETREE string default "devicetree.scarlet.cb" if BOARD_GOOGLE_SCARLET - default "devicetree.cb" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig index 79ee3d0..94d0493 100644 --- a/src/mainboard/intel/leafhill/Kconfig +++ b/src/mainboard/intel/leafhill/Kconfig @@ -11,10 +11,6 @@ string default intel/leafhill -config DEVICETREE - string - default "devicetree.cb" - config MAINBOARD_PART_NUMBER string default "Leafhill" diff --git a/src/mainboard/opencellular/elgon/Kconfig b/src/mainboard/opencellular/elgon/Kconfig index 3e0a125..3ba2a60 100644 --- a/src/mainboard/opencellular/elgon/Kconfig +++ b/src/mainboard/opencellular/elgon/Kconfig @@ -80,9 +80,6 @@ ########################################################## #### Update below when adding a new derivative board. #### ########################################################## -config DEVICETREE - string - default "devicetree.cb" config MAINBOARD_PART_NUMBER string -- To view, visit https://review.coreboot.org/29625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I3d77a625c5ece7b7ea5476fe0bd42829d1fc72c4 Gerrit-Change-Number: 29625 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/lenovo/x60/dsdt: Remove unused include
by Patrick Georgi (Code Review) 16 Nov '18

16 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29068 ) Change subject: mb/lenovo/x60/dsdt: Remove unused include ...................................................................... mb/lenovo/x60/dsdt: Remove unused include Tested - builds fine with this patch. Change-Id: I4666a8c9dd0e03ee32770844019dfc032e07e460 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Reviewed-on: https://review.coreboot.org/29068 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/x60/dsdt.asl 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Elyes HAOUAS: Looks good to me, approved diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 3222303..d4f4668 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include "smi.h" - #define THINKPAD_EC_GPE 28 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -- To view, visit https://review.coreboot.org/29068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I4666a8c9dd0e03ee32770844019dfc032e07e460 Gerrit-Change-Number: 29068 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/docker: Unify local build targets
by Patrick Georgi (Code Review) 16 Nov '18

16 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29456 ) Change subject: util/docker: Unify local build targets ...................................................................... util/docker: Unify local build targets Add a `docker-run-local` target that is used as a template for the local build targets (`docker-build-coreboot`, `docker-abuild`, and `docker-what-jenkins-does`). Note this changes the user for `docker-what-jenkins-does` which has (ccache) issues if it's not `root`. Will be fixed in a follow-up. Change-Id: I9088fb9211726cddc37b17ddf70170c2c382679e Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/29456 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/docker/Makefile 1 file changed, 12 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/util/docker/Makefile b/util/docker/Makefile index beb2a7e..32714fc 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -95,29 +95,23 @@ $(DOCKER) rmi $$($(DOCKER) images | grep -v "REPOSITORY" | tr -s ' ' | cut -f3 -d ' '); \ fi -docker-build-coreboot: test-docker +docker-run-local: test-docker $(DOCKER) run -u root -it -v $(top):/home/coreboot/coreboot \ --user $(UID):$(GID) \ --rm coreboot/coreboot-sdk:$(COREBOOT_CONTAINER_VERSION) \ - /bin/bash -c "cd /home/coreboot/coreboot && \ - make clean && \ - make $(BUILD_CMD); \ - rm .xcompile" + /bin/bash -c "cd /home/coreboot/coreboot && $(DOCKER_RUN_LOCAL)" -docker-abuild: test-docker - $(DOCKER) run -u root -it -v $(top):/home/coreboot/coreboot \ - --user $(UID):$(GID) \ - --rm coreboot/coreboot-sdk:$(COREBOOT_CONTAINER_VERSION) \ - /bin/bash -c "cd /home/coreboot/coreboot && \ - make clean && \ - util/abuild/abuild $(ABUILD_ARGS); \ - rm -f .xcompile" +docker-build-coreboot: docker-run-local +docker-build-coreboot: override DOCKER_RUN_LOCAL := \ + make clean && make $(BUILD_CMD); rm -f .xcompile -docker-what-jenkins-does: test-docker - $(DOCKER) run -u root -it -v $(top):/home/coreboot/coreboot \ - --rm coreboot/coreboot-sdk:$(COREBOOT_CONTAINER_VERSION) \ - /bin/bash -c "cd /home/coreboot/coreboot && \ - make clean && make what-jenkins-does CPUS=$(CPUS)" +docker-abuild: docker-run-local +docker-abuild: override DOCKER_RUN_LOCAL := \ + make clean && util/abuild/abuild $(ABUILD_ARGS); rm -f .xcompile + +docker-what-jenkins-does: docker-run-local +docker-what-jenkins-does: override DOCKER_RUN_LOCAL := \ + make clean && make what-jenkins-does CPUS=$(CPUS) docker-jenkins-server: test-docker @if [ ! -d "$(COREBOOT_JENKINS_CACHE_DIR)" ]; then \ -- To view, visit https://review.coreboot.org/29456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I9088fb9211726cddc37b17ddf70170c2c382679e Gerrit-Change-Number: 29456 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/fizz/variants/karma: Increase Pmax to 151 for all SKUs
by David Wu (Code Review) 16 Nov '18

16 Nov '18

David Wu has uploaded this change for review. ( https://review.coreboot.org/29654 Change subject: mb/google/fizz/variants/karma: Increase Pmax to 151 for all SKUs ...................................................................... mb/google/fizz/variants/karma: Increase Pmax to 151 for all SKUs Needs to increase ROPmax to 80W (includes both panel and audio), hence the Pmax = 71W (PL4) + 80W (ROPmax) = 151W. BUG=b:119644629 BRANCH=master TEST=USE=fw_debug emerge-kalista chromeos-mrc coreboot chromeos-bootimage & ensure the Pmax value is passed to FSP-S. Change-Id: I504ff66a218bf4e385270c2cb385a83dca312a81 Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/fizz/variants/karma/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29654/1 diff --git a/src/mainboard/google/fizz/variants/karma/overridetree.cb b/src/mainboard/google/fizz/variants/karma/overridetree.cb index 7552c71..f04def2 100644 --- a/src/mainboard/google/fizz/variants/karma/overridetree.cb +++ b/src/mainboard/google/fizz/variants/karma/overridetree.cb @@ -7,6 +7,7 @@ #| Touchsreen | 10 | | #+----------------+-------+-----------------------------------+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Touchscreen + register "psys_pmax" = "151" device domain 0 on device pci 14.0 on -- To view, visit https://review.coreboot.org/29654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I504ff66a218bf4e385270c2cb385a83dca312a81 Gerrit-Change-Number: 29654 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: soc/intel/{common, skylake}: Make ASPM enabling as common PCH feature
by Subrata Banik (Code Review) 16 Nov '18

16 Nov '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/29653 Change subject: soc/intel/{common, skylake}: Make ASPM enabling as common PCH feature ...................................................................... soc/intel/{common, skylake}: Make ASPM enabling as common PCH feature This patch moves required Kconfig selection for enabling ASPM feature (like clk_pm, L1 state etc) from soc code to intel common pch base code. TEST=Run lspci -vvv | grep ASPM The output shows the ASPM L1 is enable for pci devices Change-Id: Ic77602a75f0c9ccf28ebfd57e53433dc90985a16 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/pch/Kconfig M src/soc/intel/skylake/Kconfig 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/29653/1 diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 2bf6d68..0b43b65 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -17,6 +17,10 @@ config PCH_SPECIFIC_OPTIONS def_bool y + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_DSP diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 2db8217..85bf904 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -40,10 +40,6 @@ select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_COMMON_CLOCK - select PCIEXP_L1_SUB_STATE select PCIEX_LENGTH_64MB select REG_SCRIPT select RTC -- To view, visit https://review.coreboot.org/29653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic77602a75f0c9ccf28ebfd57e53433dc90985a16 Gerrit-Change-Number: 29653 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: tss/tcg-2.0: remove unnecessary breaks from marshaling code
by Joel Kitching (Code Review) 16 Nov '18

16 Nov '18

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/29652 Change subject: tss/tcg-2.0: remove unnecessary breaks from marshaling code ...................................................................... tss/tcg-2.0: remove unnecessary breaks from marshaling code BUG=None TEST=None Change-Id: I054e0799469bf39499666342a5c639b1f766cd85 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/tpm/tss/tcg-2.0/tss_marshaling.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29652/1 diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 83e1ad8..0707f52 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -476,10 +476,8 @@ break; case TPM2_CR50_SUB_CMD_TURN_UPDATE_ON: return ibuf_read_be8(ib, &vcr->num_restored_headers); - break; case TPM2_CR50_SUB_CMD_TPM_MODE: return ibuf_read_be8(ib, &vcr->tpm_mode); - break; default: printk(BIOS_ERR, "%s:%d - unsupported vendor command %#04x!\n", -- To view, visit https://review.coreboot.org/29652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I054e0799469bf39499666342a5c639b1f766cd85 Gerrit-Change-Number: 29652 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com>

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Change in coreboot[master]: tss: implement Cr50 vendor-specific VENDOR_CC_TPM_MODE
by build bot (Jenkins) (Code Review) 16 Nov '18

16 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29648 ) Change subject: tss: implement Cr50 vendor-specific VENDOR_CC_TPM_MODE ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29648/4/src/security/tpm/tss/tcg-2.0/tss_ma… File src/security/tpm/tss/tcg-2.0/tss_marshaling.c: https://review.coreboot.org/#/c/29648/4/src/security/tpm/tss/tcg-2.0/tss_ma… PS4, Line 482: break; break is not useful after a goto or return -- To view, visit https://review.coreboot.org/29648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idd55708797d2b17336fcbe80c0724957f7052e90 Gerrit-Change-Number: 29648 Gerrit-PatchSet: 4 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Comment-Date: Fri, 16 Nov 2018 06:32:10 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: tss: implement Cr50 vendor-specific VENDOR_CC_TPM_MODE
by build bot (Jenkins) (Code Review) 16 Nov '18

16 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29648 ) Change subject: tss: implement Cr50 vendor-specific VENDOR_CC_TPM_MODE ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/29648/3/src/security/tpm/tss/tcg-2.0/tss_ma… File src/security/tpm/tss/tcg-2.0/tss_marshaling.c: https://review.coreboot.org/#/c/29648/3/src/security/tpm/tss/tcg-2.0/tss_ma… PS3, Line 482: break; break is not useful after a goto or return -- To view, visit https://review.coreboot.org/29648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idd55708797d2b17336fcbe80c0724957f7052e90 Gerrit-Change-Number: 29648 Gerrit-PatchSet: 3 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Comment-Date: Fri, 16 Nov 2018 05:25:10 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/sarien: Program HD Audio SVID/SSID
by Lijian Zhao (Code Review) 16 Nov '18

16 Nov '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/29651 Change subject: mb/google/sarien: Program HD Audio SVID/SSID ...................................................................... mb/google/sarien: Program HD Audio SVID/SSID Realtek Codec kernel driver requires PCH HD Audio controller to have subystem vendor id and subsystem device id matched with verb table. So program same values to make it working. BUG=N/A TEST=Boot up on Sarien board and check with kernel driver dmesg to see ALC3204 or ALC3254. Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/sarien/ramstage.c A src/mainboard/google/sarien/variants/arcada/include/variant/ssid.h A src/mainboard/google/sarien/variants/sarien/include/variant/ssid.h 3 files changed, 79 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29651/1 diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index c65104b..b2914ae 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -16,6 +16,7 @@ #include <arch/acpi.h> #include <soc/ramstage.h> #include <variant/gpio.h> +#include <variant/ssid.h> #include <vendorcode/google/chromeos/chromeos.h> void mainboard_silicon_init_params(FSP_S_CONFIG *params) @@ -25,6 +26,10 @@ gpio_table = variant_gpio_table(&num_gpios); gpio_configure_pads(gpio_table, num_gpios); + + /* Update PCH HDA SVID/SSID */ + params->SiSsidTablePtr = (uintptr_t)ssidtblptr; + params->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssidtblptr); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/ssid.h b/src/mainboard/google/sarien/variants/arcada/include/variant/ssid.h new file mode 100644 index 0000000..b321ae8 --- /dev/null +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/ssid.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef VARIANT_SSID_H +#define VARIANT_SSID_H + +#include <device/pci_ids.h> +#include <soc/intel/common/ssid.h> + +#define HDA_FUNC 3 +#define ALC_SSID 0x08b6 + +struct svid_ssid_init_entry ssidtblptr[] = { + { + { + { + PCI_SUBSYSTEM_VENDOR_ID, HDA_FUNC, + PCH_DEV_SLOT_LPC, 0, 0, 0, 0 + } + }, + { CONFIG_SUBSYSTEM_VENDOR_ID, ALC_SSID } + , 0 + }, +}; + +#endif diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/ssid.h b/src/mainboard/google/sarien/variants/sarien/include/variant/ssid.h new file mode 100644 index 0000000..405d48e --- /dev/null +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/ssid.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef VARIANT_SSID_H +#define VARIANT_SSID_H + +#include <device/pci_ids.h> +#include <soc/intel/common/ssid.h> + +#define HDA_FUNC 3 +#define ALC_SSID 0x08b8 + +struct svid_ssid_init_entry ssidtblptr[] = { + { + { + { + PCI_SUBSYSTEM_VENDOR_ID, HDA_FUNC, + PCH_DEV_SLOT_LPC, 0, 0, 0, 0 + } + }, + { CONFIG_SUBSYSTEM_VENDOR_ID, ALC_SSID } + , 0 + }, +}; + +#endif -- To view, visit https://review.coreboot.org/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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coreboot-gerrit November 2018