coreboot-gerrit November 2018

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Change in coreboot[master]: mb/lenovo: Unify thermal threshold handling
by Patrick Rudolph (Code Review) 16 Nov '18

16 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29659 ) Change subject: mb/lenovo: Unify thermal threshold handling ...................................................................... Patch Set 5: Code-Review+1 Please use the correct copyright in the newly added files. -- To view, visit https://review.coreboot.org/29659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If569f67c932b7fbf14893b890a5588df4994daeb Gerrit-Change-Number: 29659 Gerrit-PatchSet: 5 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Nov 2018 19:54:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: azalia: Add Azalia Reset macro
by build bot (Jenkins) (Code Review) 16 Nov '18

16 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29554 ) Change subject: azalia: Add Azalia Reset macro ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/29554/9/src/include/device/azalia_device.h File src/include/device/azalia_device.h: https://review.coreboot.org/#/c/29554/9/src/include/device/azalia_device.h@… PS9, Line 50: #define AZALIA_RESET(pin) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/29554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36 Gerrit-Change-Number: 29554 Gerrit-PatchSet: 9 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Nov 2018 18:52:49 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/braswell: Disable OS use of HPET
by Matt DeVillier (Code Review) 16 Nov '18

16 Nov '18

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/29655 ) Change subject: soc/intel/braswell: Disable OS use of HPET ...................................................................... Patch Set 3: with what payload/distro/kernel(s) are you seeing the 'MP-BIOS bug: 8254 timer not connected to IO-APIC' issue? I'm not seeing that with Braswell ChromeOS devices using Tianocore and booting Ubuntu (and derivatives) w/kernels 4.9+. Linux reports the HPET is the current clock source, and no error in dmesg. -- To view, visit https://review.coreboot.org/29655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie9a78dcc736eb057c040a0a303c812adb1f76f3c Gerrit-Change-Number: 29655 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Nov 2018 17:35:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: intel/i945: Fix booting on a dual channel configuration
by Patrick Georgi (Code Review) 16 Nov '18

16 Nov '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/29663 Change subject: intel/i945: Fix booting on a dual channel configuration ...................................................................... intel/i945: Fix booting on a dual channel configuration The register values in dram width programming changed in commit a4fc7bef7ffab0 which broke booting on getac/p470. TEST=getac/p470 with 2 X8DDS DRAM boots again Change-Id: I8b3eedc8c5234e8a28948d4dc58bf565024f62ce Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29663/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 30e16db..5f06b7d 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -660,13 +660,13 @@ c1dramw |= (0x0000) << 4*(i % 2); break; case SYSINFO_DIMM_X8DS: - c1dramw |= (0x0001) << 4*(i % 2); + c1dramw |= (0x0010) << 4*(i % 2); break; case SYSINFO_DIMM_X16SS: c1dramw |= (0x0000) << 4*(i % 2); break; case SYSINFO_DIMM_X8DDS: - c1dramw |= (0x0005) << 4*(i % 2); + c1dramw |= (0x0050) << 4*(i % 2); break; case SYSINFO_DIMM_NOT_POPULATED: c1dramw |= (0x0000) << 4*(i % 2); -- To view, visit https://review.coreboot.org/29663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8b3eedc8c5234e8a28948d4dc58bf565024f62ce Gerrit-Change-Number: 29663 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 16 Nov '18

16 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29662 to look at the new patch set (#2). Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support No working C_ENVIRONMENT_BOOTBLOCK support is available. Enable support and add required files for the Braswell Bootblock in C. BUG=NA TEST=Portwell PQ7-M107 Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/Makefile.inc A src/drivers/intel/fsp1_1/cache_as_ram_cbootblock.S M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc A src/soc/intel/braswell/bootblock/bootblock_c.c A src/soc/intel/braswell/include/soc/bootblock.h M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/car_stage.S 8 files changed, 330 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29662/2 -- To view, visit https://review.coreboot.org/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/braswell: Add support for FSP MR2
by Frans Hendriks (Code Review) 16 Nov '18

16 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29661 to look at the new patch set (#2). Change subject: soc/intel/braswell: Add support for FSP MR2 ...................................................................... soc/intel/braswell: Add support for FSP MR2 Actual FspUpdVpd.h does not match the MR2 version in fsp 3rdparty Add config USE_BSWSBFSP to support FSP MR2 BUG=NA TEST=Portwell PQ7-M107 Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/Kconfig M src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h 2 files changed, 37 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/29661/2 -- To view, visit https://review.coreboot.org/29661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Gerrit-Change-Number: 29661 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
by build bot (Jenkins) (Code Review) 16 Nov '18

16 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29662 ) Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29662/1/src/drivers/intel/fsp1_1/cache_as_r… File src/drivers/intel/fsp1_1/cache_as_ram_cbootblock.S: https://review.coreboot.org/#/c/29662/1/src/drivers/intel/fsp1_1/cache_as_r… PS1, Line 179: * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. line over 80 characters -- To view, visit https://review.coreboot.org/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Nov 2018 14:30:39 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 16 Nov '18

16 Nov '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29662 Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support No working C_ENVIRONMENT_BOOTBLOCK support is available. Enable support and add required files for the Braswell Bootblock in C. BUG=NA TEST=Portwell PQ7-M107 Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/Makefile.inc A src/drivers/intel/fsp1_1/cache_as_ram_cbootblock.S M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc A src/soc/intel/braswell/bootblock/bootblock_c.c A src/soc/intel/braswell/include/soc/bootblock.h M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/car_stage.S 8 files changed, 329 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29662/1 diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 953d1e4..3b3387e 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -3,6 +3,7 @@ # # Copyright (C) 2014 Sage Electronic Engineering, LLC. # Copyright (C) 2015 Intel Corp. +# Copyright (C) 2018 Eltan B.V. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -22,6 +23,7 @@ bootblock-y += bootblock.c bootblock-y += fsp_util.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK)+= cache_as_ram_cbootblock.S romstage-y += car.c romstage-y += fsp_util.c diff --git a/src/drivers/intel/fsp1_1/cache_as_ram_cbootblock.S b/src/drivers/intel/fsp1_1/cache_as_ram_cbootblock.S new file mode 100644 index 0000000..70f36a4 --- /dev/null +++ b/src/drivers/intel/fsp1_1/cache_as_ram_cbootblock.S @@ -0,0 +1,215 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> +#include <../../../../../arch/x86/walkcbfs.S> + +#define LHLT_DELAY 0x50000 /* I/O delay between post codes */ + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + +.global cache_as_ram +cache_as_ram: + post_code(0x20) + +#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) + /* + * SOC specific setup + * NOTE: This has to preserve the registers + * mm0, mm1 and edi. + */ + #include <soc/car_setup.S> + + post_code(0x28) +#endif + + /* + * Find the FSP binary in cbfs. + * Make a fake stack that has the return value back to this code. + */ + lea fake_fsp_stack, %esp + jmp find_fsp +find_fsp_ret: + /* Save the FSP location */ + mov %eax, %ebp + + /* + * Only when a valid FSP binary is found at CONFIG_FSP_LOC is + * the returned FSP_INFO_HEADER structure address above the base + * address of FSP binary specified by the CONFIG_FSP_LOC value. + * All of the error values are in the 0x8xxxxxxx range which are + * below the CONFIG_FSP_LOC value. + */ + cmp $CONFIG_FSP_LOC, %eax + jbe halt1 + + post_code(POST_FSP_TEMP_RAM_INIT) + + /* Calculate entry into FSP */ + mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ + add 0x1c(%ebp), %eax /* add in the offset for FSP */ + + /* + * Pass early init variables on a fake stack (no memory yet) + * as well as the return location + */ + lea CAR_init_stack, %esp + + /* + * BIST value is zero + * eax: TempRamInitApi address + * ebp: FSP_INFO_HEADER address + * edi: BIST value + * esi: Not used + * mm0: low 32-bits of TSC value + * mm1: high 32-bits of TSC value + */ + + /* call FSP binary to setup temporary stack */ + jmp *%eax + +CAR_init_done: + addl $4, %esp + + /* + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + * mm0: low 32-bits of TSC value + * mm1: high 32-bits of TSC value + */ + + cmp $0, %eax + jne halt2 + + /* Setup bootloader stack */ + movl %edx, %esp + + /* + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + * esp: Top of stack in temp RAM + * mm0: low 32-bits of TSC value + * mm1: high 32-bits of TSC value + */ + + /* Create cache_as_ram_params on stack */ + pushl %edx /* bootloader CAR end */ + pushl %ecx /* bootloader CAR begin */ + pushl %ebp /* FSP_INFO_HEADER */ + pushl %edi /* bist */ + movd %mm1, %eax + pushl %eax /* tsc[63:32] */ + movd %mm0, %eax + pushl %eax /* tsc[31:0] */ + pushl %esp /* pointer to cache_as_ram_params */ + + /* Save FSP_INFO_HEADER location in ebx */ + mov %ebp, %ebx + + /* coreboot assumes stack/heap region will be zero */ + cld + movl %ecx, %edi + neg %ecx + /* Only clear up to current stack value. */ + add %esp, %ecx + shrl $2, %ecx + xorl %eax, %eax + rep stosl + + /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */ + push %ebp + movd %mm1, %eax + push %eax + + /* We can call into C functions now */ + call bootblock_c_entry + + /* Never reached */ + +halt1: + /* + * Failures for postcode 0xBA - failed in fsp_fih_early_find() + * + * Values are: + * 0x01 - FV signature, "_FVH" not present + * 0x02 - FFS GUID not present + * 0x03 - FSP INFO Header not found + * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP + rebased to a different location, or does it need to be? + * 0x05 - FSP INFO Header signature "FSPH" not found + * 0x06 - FSP Image ID is not the expected ID. + */ + movb $0xBA, %ah + jmp .Lhlt + +halt2: + /* + * Failures for postcode 0xBB - failed in the FSP: + * + * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully. + * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. + * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. + * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed + * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. + * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked + */ + movb $0xBB, %ah + jmp .Lhlt + +.Lhlt: + xchg %al, %ah +#if IS_ENABLED(CONFIG_POST_IO) + outb %al, $CONFIG_POST_IO_PORT +#else + post_code(POST_DEAD_CODE) +#endif + movl $LHLT_DELAY, %ecx +.Lhlt_Delay: + outb %al, $0xED + loop .Lhlt_Delay + jmp .Lhlt + +/* + * esp is set to this location so that the call into and return from the FSP + * in find_fsp will work. + */ + .align 4 +fake_fsp_stack: + .long find_fsp_ret + .long CONFIG_FSP_LOC /* FSP base address */ + +CAR_init_params: + .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ + .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_ROM_SIZE /* Total FW Length */ + +CAR_init_stack: + .long CAR_init_done + .long CAR_init_params diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 50c2802..e7b0ef7 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -40,15 +40,30 @@ select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC - select USE_GENERIC_FSP_CAR_INC select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT select HAVE_FSP_GOP select GENERIC_GPIO_LIB select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI + select BOOTBLOCK_CONSOLE select CPU_INTEL_COMMON +config USE_GENERIC_FSP_CAR_INC + bool + default y if !C_ENVIRONMENT_BOOTBLOCK + +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x8000 + config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index ac1bacd..6939ddd 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -9,6 +9,8 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += bootblock/bootblock_c.c + romstage-y += gpio_support.c romstage-y += iosf.c romstage-y += lpc_init.c diff --git a/src/soc/intel/braswell/bootblock/bootblock_c.c b/src/soc/intel/braswell/bootblock/bootblock_c.c new file mode 100644 index 0000000..8cb6fa8 --- /dev/null +++ b/src/soc/intel/braswell/bootblock/bootblock_c.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <fsp/bootblock.h> + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_timestamp(base_timestamp, NULL, 0); +} + +void bootblock_soc_early_init(void) +{ +} + + +void bootblock_soc_init(void) +{ + printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); +} diff --git a/src/soc/intel/braswell/include/soc/bootblock.h b/src/soc/intel/braswell/include/soc/bootblock.h new file mode 100644 index 0000000..072e55d --- /dev/null +++ b/src/soc/intel/braswell/include/soc/bootblock.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BOOTBLOCK_H_ +#define _SOC_BOOTBLOCK_H_ + +#endif /* _SOC_BOOTBLOCK_H_ */ diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index c3ed415..7afb0b5 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,3 +1,4 @@ +romstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += car_stage.S romstage-y += early_spi.c romstage-y += pmc.c romstage-y += romstage.c diff --git a/src/soc/intel/braswell/romstage/car_stage.S b/src/soc/intel/braswell/romstage/car_stage.S new file mode 100644 index 0000000..db9f404 --- /dev/null +++ b/src/soc/intel/braswell/romstage/car_stage.S @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc + * Copyright 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* I/O delay between post codes on failure */ +#define LHLT_DELAY 0x50000 + +.text +.global car_stage_entry +car_stage_entry: + call romstage_c_entry + #include "src/drivers/intel/fsp1_1/after_raminit.S" + + movb $0x69, %ah + jmp .Lhlt + +.Lhlt: + xchg %al, %ah +#if IS_ENABLED(CONFIG_POST_IO) + outb %al, $CONFIG_POST_IO_PORT +#else + post_code(POST_DEAD_CODE) +#endif + movl $LHLT_DELAY, %ecx +.Lhlt_Delay: + outb %al, $0xED + loop .Lhlt_Delay + jmp .Lhlt -- To view, visit https://review.coreboot.org/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: mb/lenovo: Unify thermal threshold handling
by Peter Lemenkov (Code Review) 16 Nov '18

16 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29659 to look at the new patch set (#5). Change subject: mb/lenovo: Unify thermal threshold handling ...................................................................... mb/lenovo: Unify thermal threshold handling Unify thermal handling across Lenovo boards (except g505, which is different). Namely, do the following: * Move thermal levels from acpi_tables to thermal.h (and create if necessary). * Don't use board-specific ifdef guards. * Set thermal levels using dedicated acpi_update_thermal_table function as almost all Lenovo boards do. * Update list of authors in comments. Merge all author's entries. * Minor whitespace and formatting. This makes diff -ruw between the Lenovo boards smaller. Change-Id: If569f67c932b7fbf14893b890a5588df4994daeb Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/l520/acpi_tables.c M src/mainboard/lenovo/l520/thermal.h M src/mainboard/lenovo/s230u/acpi_tables.c A src/mainboard/lenovo/s230u/thermal.h M src/mainboard/lenovo/t400/acpi_tables.c A src/mainboard/lenovo/t400/thermal.h M src/mainboard/lenovo/t420/thermal.h M src/mainboard/lenovo/t420s/thermal.h M src/mainboard/lenovo/t430/thermal.h M src/mainboard/lenovo/t430s/thermal.h M src/mainboard/lenovo/t520/acpi_tables.c M src/mainboard/lenovo/t520/thermal.h M src/mainboard/lenovo/t530/acpi_tables.c M src/mainboard/lenovo/t530/thermal.h M src/mainboard/lenovo/t60/acpi_tables.c A src/mainboard/lenovo/t60/thermal.h M src/mainboard/lenovo/x131e/thermal.h M src/mainboard/lenovo/x1_carbon_gen1/thermal.h M src/mainboard/lenovo/x200/acpi_tables.c A src/mainboard/lenovo/x200/thermal.h M src/mainboard/lenovo/x201/acpi_tables.c A src/mainboard/lenovo/x201/thermal.h M src/mainboard/lenovo/x220/thermal.h M src/mainboard/lenovo/x230/thermal.h M src/mainboard/lenovo/x60/acpi_tables.c A src/mainboard/lenovo/x60/thermal.h M src/mainboard/lenovo/z61t/acpi_tables.c A src/mainboard/lenovo/z61t/thermal.h 28 files changed, 402 insertions(+), 115 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/29659/5 -- To view, visit https://review.coreboot.org/29659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: If569f67c932b7fbf14893b890a5588df4994daeb Gerrit-Change-Number: 29659 Gerrit-PatchSet: 5 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/braswell: Add support for FSP MR2
by Frans Hendriks (Code Review) 16 Nov '18

16 Nov '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29661 Change subject: soc/intel/braswell: Add support for FSP MR2 ...................................................................... soc/intel/braswell: Add support for FSP MR2 Actual FspUpdVpd.h does not match the MR2 version in fsp 3rdparty Add config USE_BSWSBFSP to support FSP MR2 BUG=NA TEST=Portwell PQ7-M107 Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/Kconfig M src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h 2 files changed, 39 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/29661/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 50c2802..8b44d1d 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -128,4 +128,11 @@ string default "soc/intel/braswell/bootblock/timestamp.inc" +config USE_BSWSBFSP + bool "Use MR2 FSP" + default y + help + FSP releases have difference image IDs. Enable this option when + FSP MR2 is used. + endif diff --git a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h index 1ae1d03..265873d 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h +++ b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h @@ -1,6 +1,7 @@ /** @file Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2018, Eltan B.V. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -197,6 +198,7 @@ Enable/Disable DDR3 Auto Self Refresh **/ UINT8 PcdDdr3AutoSelfRefreshEnable; +/* NOT SUPPORTED BY MR2 START */ /** Offset 0x0044 Disable Auto Detect Dram for LPDDR3 memory To Enable/Disable AutoDetectDram @@ -229,6 +231,7 @@ UINT8 PcdRxOdtLimitChannel1; /** Offset 0x004A **/ +/* NOT SUPPORTED BY MR2 END */ UINT8 ReservedMemoryInitUpd[182]; } MEMORY_INIT_UPD; @@ -485,6 +488,7 @@ Check for Sd card detect **/ UINT8 PcdSdDetectChk; +/* NOT SUPPORTED BY MR2 START */ /** Offset 0x0163 **/ UINT8 I2C0Frequency; @@ -524,7 +528,8 @@ /** Offset 0x016F **/ UINT8 D0VnnBump100mV; -/** Offset 0x170 + /* NOT SUPPORTED BY MR2 END */ + ** Offset 0x170 **/ UINT8 ReservedSiliconInitUpd[398]; } SILICON_INIT_UPD; @@ -558,13 +563,28 @@ /** Offset 0x0100 **/ SILICON_INIT_UPD SiliconInitUpd; -/** Offset 0x0305 +/** Offset 0x02FE **/ UINT16 PcdRegionTerminator; + +#if IS_ENABLED(CONFIG_USE_BSWSBFSP) +/** Offset 0x0300 +**/ + UINT8 UnusedUpdSpace4[2123]; +/** Offset 0x0B4B +**/ + UINT8 PcdPaddingSpace; +#endif //CONFIG_USE_BSWSBFSP + } UPD_DATA_REGION; +#if IS_ENABLED(CONFIG_USE_BSWSBFSP) +#define FSP_IMAGE_ID 0x5053464253575342 /* 'BSWSBFSP' */ +#define FSP_IMAGE_REV 0x01010401 +#else #define FSP_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */ #define FSP_IMAGE_REV 0x01010700 +#endif typedef struct _VPD_DATA_REGION { /** Offset 0x0000 @@ -577,6 +597,16 @@ /** Offset 0x000C **/ UINT32 PcdUpdRegionOffset; +#if IS_ENABLED(CONFIG_USE_BSWSBFSP) +/** Offset 0x0010 +**/ + UINT8 UnusedVpdSpace0[20]; +/** Offset 0x0024 + Enable Secure Boot + Enable/disable secure boot. Auto by default. +**/ + UINT8 PcdEnableSecureBoot; +#endif } VPD_DATA_REGION; #pragma pack(pop) -- To view, visit https://review.coreboot.org/29661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Gerrit-Change-Number: 29661 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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coreboot-gerrit November 2018