coreboot-gerrit November 2018

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Change in coreboot[master]: ec/google/wilco: Enable COM1 ACPI device
by Duncan Laurie (Code Review) 17 Nov '18

17 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29672 Change subject: ec/google/wilco: Enable COM1 ACPI device ...................................................................... ec/google/wilco: Enable COM1 ACPI device Enable the COM1 ACPI device based on the existing Kconfig option CONFIG_DRIVERS_UART_8250IO instead of expecting the mainboard to also define another value for ACPI. Change-Id: I69361cc2c245cfcad3e4f57567bf56d5a26f0b06 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/acpi/superio.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29672/1 diff --git a/src/ec/google/wilco/acpi/superio.asl b/src/ec/google/wilco/acpi/superio.asl index a8cea78..9c23c49 100644 --- a/src/ec/google/wilco/acpi/superio.asl +++ b/src/ec/google/wilco/acpi/superio.asl @@ -29,7 +29,7 @@ Method (_STA, 0, NotSerialized) { -#ifdef SIO_EC_ENABLE_COM1 +#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) Return (0x0f) #else Return (Zero) -- To view, visit https://review.coreboot.org/29672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I69361cc2c245cfcad3e4f57567bf56d5a26f0b06 Gerrit-Change-Number: 29672 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: soc/intel/cannonlake: Fix IO decode setup
by Duncan Laurie (Code Review) 17 Nov '18

17 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29671 Change subject: soc/intel/cannonlake: Fix IO decode setup ...................................................................... soc/intel/cannonlake: Fix IO decode setup This change makes the early IO decode setup mirror that of other Intel SOCs and fixes issues with COM1 not being enabled properly. Tested by successfully successfully receiving serial output from an 8250IO UART device at the standard 0x3f8 base address. Change-Id: I9bd894fea62b78b81e5c80b5e88a539ebddac2df Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/cannonlake/bootblock/pch.c 1 file changed, 29 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/29671/1 diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 3ef084a..b06c81b 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -46,6 +46,9 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) + #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC @@ -168,23 +171,38 @@ outw(tcocnt, tcobase + TCO1_CNT); } +static int pch_check_decode_enable(void) +{ + uint32_t dmi_control; + + /* + * This cycle decoding is only allowed to set when + * DMICTL.SRLOCK is 0. + */ + dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + if (dmi_control & PCR_DMI_DMICTL_SRLOCK) + return -1; + return 0; +} + void pch_early_iorange_init(void) { - uint16_t dec_rng, dec_en = 0; + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | + LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; /* IO Decode Range */ - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) && - IS_ENABLED(CONFIG_UART_DEBUG)) { - dec_rng = COMA_RANGE | (COMB_RANGE << 4); - dec_en = COMA_LPC_EN | COMB_LPC_EN; - pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, dec_rng); - pcr_write16(PID_DMI, PCR_DMI_LPCIOD, dec_rng); - } + if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN; - pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en); - pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en); + if (pch_check_decode_enable() == 0) { + io_enables = lpc_enable_fixed_io_ranges(io_enables); + /* + * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same + * value program in LPC PCI offset 82h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + } /* Program generic IO Decode Range */ pch_enable_lpc(); -- To view, visit https://review.coreboot.org/29671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9bd894fea62b78b81e5c80b5e88a539ebddac2df Gerrit-Change-Number: 29671 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: [WIP]x86|mb/emulation/qemu-q35: 64bit ramstage support
by build bot (Jenkins) (Code Review) 17 Nov '18

17 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29667 ) Change subject: [WIP]x86|mb/emulation/qemu-q35: 64bit ramstage support ...................................................................... Patch Set 2: (26 comments) https://review.coreboot.org/#/c/29667/2/src/arch/x86/boot.c File src/arch/x86/boot.c: https://review.coreboot.org/#/c/29667/2/src/arch/x86/boot.c@36 PS2, Line 36: printk(BIOS_DEBUG, "Jumping to %p\n", (void*)prog_entry(prog)); "(foo*)" should be "(foo *)" https://review.coreboot.org/#/c/29667/2/src/arch/x86/exception.c File src/arch/x86/exception.c: https://review.coreboot.org/#/c/29667/2/src/arch/x86/exception.c@513 PS2, Line 513: for (int i = 0; i < 16; i++) suspect code indent for conditional statements (8, 8) https://review.coreboot.org/#/c/29667/2/src/arch/x86/include/arch/mmu.h File src/arch/x86/include/arch/mmu.h: https://review.coreboot.org/#/c/29667/2/src/arch/x86/include/arch/mmu.h@78 PS2, Line 78: #define L0_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L0_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/2/src/arch/x86/include/arch/mmu.h@79 PS2, Line 79: #define L1_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L1_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/2/src/arch/x86/include/arch/mmu.h@80 PS2, Line 80: #define L2_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L2_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/2/src/arch/x86/include/arch/mmu.h@81 PS2, Line 81: #define L3_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L3_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/2/src/arch/x86/include/arch/registers… File src/arch/x86/include/arch/registers.h: https://review.coreboot.org/#/c/29667/2/src/arch/x86/include/arch/registers… PS2, Line 23: #define DOWNTO8(A) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29667/2/src/arch/x86/include/arch/registers… PS2, Line 41: #define DOWNTO16(A) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c File src/arch/x86/mmu.c: https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@214 PS2, Line 214: if ((size >= L1_XLAT_SIZE) && suspect code indent for conditional statements (8, 24) https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@274 PS2, Line 274: switch ((pte[index] & AVAIL_MASK) >> AVAIL_SHIFT) { switch and case should be at the same indent https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@276 PS2, Line 276: printk(BIOS_DEBUG, "INVAL ");break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@278 PS2, Line 278: printk(BIOS_DEBUG, "TABLE @ %llx\n", pte[index] & XLAT_ADDR_MASK);break; line over 80 characters https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@278 PS2, Line 278: printk(BIOS_DEBUG, "TABLE @ %llx\n", pte[index] & XLAT_ADDR_MASK);break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@280 PS2, Line 280: printk(BIOS_DEBUG, "PAGE %llx, %llx %llx\n", pte[index] & ((XLAT_ADDR_MASK<<1)), line over 80 characters https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@281 PS2, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; line over 80 characters https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@281 PS2, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; need consistent spacing around '-' (ctx:WxV) https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@281 PS2, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@281 PS2, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@284 PS2, Line 284: printk(BIOS_DEBUG, "BLOCK %llx, %llx %llx\n", pte[index] & ((XLAT_ADDR_MASK<<1)), line over 80 characters https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@285 PS2, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; line over 80 characters https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@285 PS2, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; need consistent spacing around '-' (ctx:WxV) https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@285 PS2, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@285 PS2, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@340 PS2, Line 340: next_free_table = cbmem_add(CBMEM_ID_TTB, CONFIG_TTB_SIZE_KB * 1024); line over 80 characters https://review.coreboot.org/#/c/29667/2/src/arch/x86/mmu.c@390 PS2, Line 390: #define MSR_EFER 0xc0000080 /* extended feature register */ line over 80 characters https://review.coreboot.org/#/c/29667/2/src/mainboard/emulation/qemu-q35/ro… File src/mainboard/emulation/qemu-q35/romstage.c: https://review.coreboot.org/#/c/29667/2/src/mainboard/emulation/qemu-q35/ro… PS2, Line 43: mmu_config_range(0x100000000ULL, (uint64_t)qemu_get_high_memory_size() * 1024ULL, PAT_WB); line over 80 characters -- To view, visit https://review.coreboot.org/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Nov 2018 16:57:45 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: treewide: use /usr/bin/env where appropriate
by Angel Pons (Code Review) 17 Nov '18

17 Nov '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/28953 ) Change subject: treewide: use /usr/bin/env where appropriate ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28953/1/util/ipqheader/mbn_tools.py File util/ipqheader/mbn_tools.py: https://review.coreboot.org/#/c/28953/1/util/ipqheader/mbn_tools.py@1 PS1, Line 1: #!/usr/bin/env python > oops, sorry - I missed this. […] Refer to CB:29666 -- To view, visit https://review.coreboot.org/28953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7546bcb881c532adc984577ecb0ee2ec4f2efe00 Gerrit-Change-Number: 28953 Gerrit-PatchSet: 2 Gerrit-Owner: Yegor Timoshenko <yegortimoshenko(a)riseup.net> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yegor Timoshenko <yegortimoshenko(a)riseup.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 17 Nov 2018 16:45:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: util/board_status: run dmesg with sudo
by Angel Pons (Code Review) 17 Nov '18

17 Nov '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/29670 ) Change subject: util/board_status: run dmesg with sudo ...................................................................... Patch Set 1: Code-Review+2 Some distros allow non-root to access the kernel log buffer (e.g. Arch Linux), some others do not (e.g. Debian). -- To view, visit https://review.coreboot.org/29670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I654422992e5ba1e98a786f65d50289efbcd46602 Gerrit-Change-Number: 29670 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Nov 2018 16:44:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/abuild: Use absolute paths for (failed|passed)_boards
by Nico Huber (Code Review) 17 Nov '18

17 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/29451 ) Change subject: util/abuild: Use absolute paths for (failed|passed)_boards ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29451/4/util/abuild/abuild File util/abuild/abuild: https://review.coreboot.org/#/c/29451/4/util/abuild/abuild@22 PS4, Line 22: TOP > any reason why you couldn't just derive the full paths from $TOP? Don't know what $TOP is used for at all. The original problem, {failed,passed}_boards, is relative to $TARGET so that can't work. (now that I looked, half of the script seems to use $TOP as root of the coreboot tree, the other half $ROOT and assumes abuild might be called from somewhere else) Maybe it could be used for some paths that I normalized to use abspath(). Idk, for somebody who didn't wrote this script, it's hard to grasp in which directory it is at which point. Some of the calls to `pwd` on the LHS might be unnecessary, who knows? -- To view, visit https://review.coreboot.org/29451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ief00e28e09a4714b0106c35ad4f4e9c696f6aad4 Gerrit-Change-Number: 29451 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Nov 2018 16:25:47 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: util/abuild: Ensure .xcompile exists
by Nico Huber (Code Review) 17 Nov '18

17 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/29483 ) Change subject: util/abuild: Ensure .xcompile exists ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29483/1/util/abuild/abuild File util/abuild/abuild: https://review.coreboot.org/#/c/29483/1/util/abuild/abuild@482 PS1, Line 482: missing_arches=$(printf 'include .xcompile\nall: ; @echo $(foreach arch,'"$required_arches"',$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch)))' | $MAKE --no-print-directory -f -) It's used here before the regular `make` is run. -- To view, visit https://review.coreboot.org/29483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib485e7741b7700fa241c192e60900ae5f1d977f5 Gerrit-Change-Number: 29483 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Nov 2018 16:12:18 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: util/board_status: run dmesg with sudo
by Patrick Georgi (Code Review) 17 Nov '18

17 Nov '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/29670 Change subject: util/board_status: run dmesg with sudo ...................................................................... util/board_status: run dmesg with sudo Newer kernels only allow root to access the kernel log buffer. In another case (cbmem) we use sudo to get past that, so we can expect sudo to be available here, too. Change-Id: I654422992e5ba1e98a786f65d50289efbcd46602 Signed-off-by: Patrick Georgi <patrick(a)georgi.software> --- M util/board_status/board_status.sh 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29670/1 diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 4acbb6c..bba3d1f 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -381,7 +381,7 @@ cmd_nonfatal $REMOTE "$cbmem_cmd -t" "${tmpdir}/${results}/coreboot_timestamps.txt" echo "Getting remote dmesg" - cmd $REMOTE dmesg "${tmpdir}/${results}/kernel_log.txt" + cmd $REMOTE sudo dmesg "${tmpdir}/${results}/kernel_log.txt" else echo "Verifying that CBMEM is available" if [ $(id -u) -ne 0 ]; then -- To view, visit https://review.coreboot.org/29670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I654422992e5ba1e98a786f65d50289efbcd46602 Gerrit-Change-Number: 29670 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Nico Huber (Code Review) 17 Nov '18

17 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29669 Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... cpu/intel/sandybridge: Add `hyper_threading` option More and more people request an option to disable HT. To implement that we have to toggle a bit in a `soft reset` register in the PCH that can override certain default settings of the CPU when it comes out of reset. The `soft reset` register is already used for other settings. So we have to take care that all settings are gathered before we issue the reset. Note, the current code using `soft reset` for flex ratio selection seems incomplete. Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/cpu/intel/model_206ax/bootblock.c M src/mainboard/lenovo/t430/cmos.layout M src/southbridge/intel/bd82x6x/pch.h 3 files changed, 46 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29669/1 diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 670b097..929c6dc 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -19,6 +19,8 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> +#include <option_table.h> +#include <pc80/mc146818rtc.h> #include <halt.h> #include <cpu/intel/microcode/microcode.c> @@ -61,34 +63,29 @@ wrmsr(MTRR_DEF_TYPE_MSR, msr); } -static void set_flex_ratio_to_tdp_nominal(void) +static u32 set_flex_ratio_to_tdp_nominal(u32 soft_reset) { msr_t flex_ratio, msr; - u32 soft_reset; u8 nominal_ratio; /* Minimum CPU revision for configurable TDP support */ if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) - return; + return soft_reset; /* Check for Flex Ratio support */ flex_ratio = rdmsr(MSR_FLEX_RATIO); if (!(flex_ratio.lo & FLEX_RATIO_EN)) - return; + return soft_reset; /* Check for >0 configurable TDPs */ msr = rdmsr(MSR_PLATFORM_INFO); if (((msr.hi >> 1) & 3) == 0) - return; + return soft_reset; /* Use nominal TDP ratio for flex ratio */ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); nominal_ratio = msr.lo & 0xff; - /* See if flex ratio is already set to nominal TDP ratio */ - if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) - return; - /* Set flex ratio to nominal TDP ratio */ flex_ratio.lo &= ~0xff00; flex_ratio.lo |= nominal_ratio << 8; @@ -97,24 +94,52 @@ /* Set flex ratio in soft reset data register bits 11:6. * RCBA region is enabled in southbridge bootblock */ - soft_reset = RCBA32(SOFT_RESET_DATA); soft_reset &= ~(0x3f << 6); soft_reset |= (nominal_ratio & 0x3f) << 6; - RCBA32(SOFT_RESET_DATA) = soft_reset; + return soft_reset; +} - /* Set soft reset control to use register value */ +static u32 set_hyperthreading_option(u32 soft_reset) +{ + int ht_requested; + + ht_requested = read_option(hyper_threading, 1); + + soft_reset &= ~1; + soft_reset |= !ht_requested; /* Bit 0 is ht disable */ + return soft_reset; +} + +static void soft_reset_settings(void) +{ + int need_reset; + u32 soft_reset; + + soft_reset = RCBA32(SOFT_RESET_DATA); + soft_reset = set_flex_ratio_to_tdp_nominal(soft_reset); + soft_reset = set_hyperthreading_option(soft_reset); + + /* Check if we didn't already request these settings */ + need_reset = !(RCBA32(SOFT_RESET_CTRL) & 1) || + RCBA32(SOFT_RESET_DATA) != soft_reset; + + /* Set current requests */ + RCBA32(SOFT_RESET_DATA) = soft_reset; + /* Use them instead of defaults */ RCBA32_OR(SOFT_RESET_CTRL, 1); - /* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); + if (need_reset) { + outb(0x2, 0xcf9); + outb(0x6, 0xcf9); + halt(); + } else { + RCBA32_OR(SOFT_RESET_LOCK, 1); + } } static void bootblock_cpu_init(void) { - /* Set flex ratio and reset if needed */ - set_flex_ratio_to_tdp_nominal(); + soft_reset_settings(); enable_rom_caching(); intel_update_microcode_from_cbfs(); } diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout index 1b50e7f..9517482 100644 --- a/src/mainboard/lenovo/t430/cmos.layout +++ b/src/mainboard/lenovo/t430/cmos.layout @@ -72,7 +72,8 @@ 422 2 e 10 backlight # coreboot config options: cpu -#424 8 r 0 unused +424 1 e 1 hyper_threading +#425 7 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index bb0d5c4..7aab77a 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -391,6 +391,7 @@ #define D22IR 0x315c /* 16bit */ #define D20IR 0x3160 /* 16bit */ #define OIC 0x31fe /* 16bit */ +#define SOFT_RESET_LOCK 0x38f0 #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 -- To view, visit https://review.coreboot.org/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: nb/intel/sandybridge/acpi: Add RMRR entry for iGPU
by Nico Huber (Code Review) 17 Nov '18

17 Nov '18

Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29668 to look at the new patch set (#4). Change subject: nb/intel/sandybridge/acpi: Add RMRR entry for iGPU ...................................................................... nb/intel/sandybridge/acpi: Add RMRR entry for iGPU The iGPU always needs access to its stolen memory. For proper IOMMU support, we have to make the OS aware of that. Directly below TOLUD lies the data stolen memory (BDSM) followed by the GTT stolen memory (BGSM), the iGPU needs access to both. Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/intel/sandybridge/acpi.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/29668/4 -- To view, visit https://review.coreboot.org/29668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d Gerrit-Change-Number: 29668 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit November 2018