coreboot-gerrit November 2018

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Change in coreboot[master]: soc/intel/common/*/Kconfig: Remove redundant comments
by Subrata Banik (Code Review) 18 Nov '18

18 Nov '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/29677 ) Change subject: soc/intel/common/*/Kconfig: Remove redundant comments ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ide9608e487793fa4a8b0e291ba168126e0484355 Gerrit-Change-Number: 29677 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 18 Nov 2018 03:24:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Kconfig: Unify power-after-failure options
by Nico Huber (Code Review) 18 Nov '18

18 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/29680 ) Change subject: Kconfig: Unify power-after-failure options ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/29680/1/src/mainboard/Kconfig File src/mainboard/Kconfig: https://review.coreboot.org/#/c/29680/1/src/mainboard/Kconfig@198 PS1, Line 198: config POWER_STATE_DEFAULT_OFF_AFTER_FAILURE Should get rid of this and invert the default, only intel/soc/common/ doesn't set it. https://review.coreboot.org/#/c/29680/1/src/mainboard/Kconfig@208 PS1, Line 208: default POWER_STATE_ON_AFTER_FAILURE Should mention that this can be overridden by an option-table entry. -- To view, visit https://review.coreboot.org/29680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0 Gerrit-Change-Number: 29680 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 18 Nov 2018 01:43:40 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP]x86|mb/emulation/qemu-q35: 64bit ramstage support
by build bot (Jenkins) (Code Review) 17 Nov '18

17 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29667 ) Change subject: [WIP]x86|mb/emulation/qemu-q35: 64bit ramstage support ...................................................................... Patch Set 4: (26 comments) https://review.coreboot.org/#/c/29667/4/src/arch/x86/boot.c File src/arch/x86/boot.c: https://review.coreboot.org/#/c/29667/4/src/arch/x86/boot.c@35 PS4, Line 35: printk(BIOS_DEBUG, "Jumping to %p\n", (void*)prog_entry(prog)); "(foo*)" should be "(foo *)" https://review.coreboot.org/#/c/29667/4/src/arch/x86/exception.c File src/arch/x86/exception.c: https://review.coreboot.org/#/c/29667/4/src/arch/x86/exception.c@513 PS4, Line 513: for (int i = 0; i < 16; i++) suspect code indent for conditional statements (8, 8) https://review.coreboot.org/#/c/29667/4/src/arch/x86/include/arch/mmu.h File src/arch/x86/include/arch/mmu.h: https://review.coreboot.org/#/c/29667/4/src/arch/x86/include/arch/mmu.h@78 PS4, Line 78: #define L0_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L0_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/4/src/arch/x86/include/arch/mmu.h@79 PS4, Line 79: #define L1_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L1_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/4/src/arch/x86/include/arch/mmu.h@80 PS4, Line 80: #define L2_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L2_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/4/src/arch/x86/include/arch/mmu.h@81 PS4, Line 81: #define L3_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L3_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/4/src/arch/x86/include/arch/registers… File src/arch/x86/include/arch/registers.h: https://review.coreboot.org/#/c/29667/4/src/arch/x86/include/arch/registers… PS4, Line 23: #define DOWNTO8(A) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29667/4/src/arch/x86/include/arch/registers… PS4, Line 41: #define DOWNTO16(A) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c File src/arch/x86/mmu.c: https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@214 PS4, Line 214: if ((size >= L1_XLAT_SIZE) && suspect code indent for conditional statements (8, 24) https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@274 PS4, Line 274: switch ((pte[index] & AVAIL_MASK) >> AVAIL_SHIFT) { switch and case should be at the same indent https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@276 PS4, Line 276: printk(BIOS_DEBUG, "INVAL ");break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@278 PS4, Line 278: printk(BIOS_DEBUG, "TABLE @ %llx\n", pte[index] & XLAT_ADDR_MASK);break; line over 80 characters https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@278 PS4, Line 278: printk(BIOS_DEBUG, "TABLE @ %llx\n", pte[index] & XLAT_ADDR_MASK);break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@280 PS4, Line 280: printk(BIOS_DEBUG, "PAGE %llx, %llx %llx\n", pte[index] & ((XLAT_ADDR_MASK<<1)), line over 80 characters https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@281 PS4, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; line over 80 characters https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@281 PS4, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; need consistent spacing around '-' (ctx:WxV) https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@281 PS4, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@281 PS4, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@284 PS4, Line 284: printk(BIOS_DEBUG, "BLOCK %llx, %llx %llx\n", pte[index] & ((XLAT_ADDR_MASK<<1)), line over 80 characters https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@285 PS4, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; line over 80 characters https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@285 PS4, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; need consistent spacing around '-' (ctx:WxV) https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@285 PS4, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@285 PS4, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@340 PS4, Line 340: next_free_table = cbmem_add(CBMEM_ID_TTB, CONFIG_TTB_SIZE_KB * 1024); line over 80 characters https://review.coreboot.org/#/c/29667/4/src/arch/x86/mmu.c@390 PS4, Line 390: #define MSR_EFER 0xc0000080 /* extended feature register */ line over 80 characters https://review.coreboot.org/#/c/29667/4/src/mainboard/emulation/qemu-q35/ro… File src/mainboard/emulation/qemu-q35/romstage.c: https://review.coreboot.org/#/c/29667/4/src/mainboard/emulation/qemu-q35/ro… PS4, Line 43: mmu_config_range(0x100000000ULL, (uint64_t)qemu_get_high_memory_size() * 1024ULL, PAT_WB); line over 80 characters -- To view, visit https://review.coreboot.org/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Nov 2018 23:05:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: (console, drivers/uart)/Kconfig: Fix dependencies
by Nico Huber (Code Review) 17 Nov '18

17 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/29572 ) Change subject: (console,drivers/uart)/Kconfig: Fix dependencies ...................................................................... Patch Set 3: needed a manual rebase -- To view, visit https://review.coreboot.org/29572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Gerrit-Change-Number: 29572 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Nov 2018 22:47:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common: Bring DISPLAY_MTRRS into the light
by Nico Huber (Code Review) 17 Nov '18

17 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29684 Change subject: soc/intel/common: Bring DISPLAY_MTRRS into the light ...................................................................... soc/intel/common: Bring DISPLAY_MTRRS into the light Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the "Debug" menu. It turned out, though, that the code looks rather generic and while it's not perfect, I see nothing to be ashamed of. No need to hide it in soc/intel/. If somebody wants to review the code if it's 100% generic, we could even get rid of HAVE_DISPLAY_MTRRS. Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Documentation/Intel/Board/Galileo_checklist.html M Documentation/Intel/SoC/soc.html M src/Kconfig M src/arch/x86/postcar.c M src/cpu/x86/mtrr/Makefile.inc A src/cpu/x86/mtrr/debug.c M src/cpu/x86/mtrr/earlymtrr.c M src/drivers/intel/fsp1_1/after_raminit.S M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/include/fsp/ramstage.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/drivers/intel/fsp1_1/stack.c M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/notify.c M src/include/cpu/x86/mtrr.h M src/soc/intel/common/Kconfig M src/soc/intel/common/Makefile.inc D src/soc/intel/common/util.c D src/soc/intel/common/util.h M src/soc/intel/quark/Makefile.inc M src/soc/intel/quark/bootblock/bootblock.c M src/soc/intel/quark/include/soc/ramstage.h M src/soc/intel/quark/romstage/mtrr.c M src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat M src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat M src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat M src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat 27 files changed, 247 insertions(+), 313 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/29684/1 diff --git a/Documentation/Intel/Board/Galileo_checklist.html b/Documentation/Intel/Board/Galileo_checklist.html index 3fc04b1..397f570 100644 --- a/Documentation/Intel/Board/Galileo_checklist.html +++ b/Documentation/Intel/Board/Galileo_checklist.html @@ -79,8 +79,6 @@ <tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr> <tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr> <tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_memory_init_params</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_mtrrs</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_get_variable_mtrr_count</td></tr> <tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>soc_pre_ram_init</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr> diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 29b819e..fff536b 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -234,8 +234,6 @@ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">src/drivers/intel/fsp1_1/cache_as_ram.inc</a> </li> <li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common - specifically building - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/co…">util.c</a> </li> </ol> </li> diff --git a/src/Kconfig b/src/Kconfig index ce584f5..b14fa32 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -700,6 +700,13 @@ bool "Output verbose GPIO debug messages" depends on HAVE_DEBUG_GPIO +config HAVE_DISPLAY_MTRRS + bool + +config DISPLAY_MTRRS + bool "Display intermediate MTRR settings" + depends on HAVE_DISPLAY_MTRRS + config DEBUG_CBFS bool "Output verbose CBFS debug messages" default n diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index 295276b..ea05824 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -16,9 +16,9 @@ #include <arch/cpu.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> #include <main_decl.h> #include <program_loading.h> -#include <soc/intel/common/util.h> /* * Systems without a native coreboot cache-as-ram teardown may implement @@ -35,9 +35,7 @@ /* Recover cbmem so infrastruture using it is functional. */ cbmem_initialize(); - /* Display the MTRRs */ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) - soc_display_mtrrs(); + display_mtrrs(); /* Load and run ramstage. */ run_ramstage(); diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index e6e9c50..caa6e9c 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1,3 +1,9 @@ -ramstage-y += mtrr.c -romstage-y += earlymtrr.c -bootblock-y += earlymtrr.c +ramstage-y += mtrr.c + +romstage-y += earlymtrr.c +bootblock-y += earlymtrr.c + +bootblock-y += debug.c +romstage-y += debug.c +postcar-y += debug.c +ramstage-y += debug.c diff --git a/src/cpu/x86/mtrr/debug.c b/src/cpu/x86/mtrr/debug.c new file mode 100644 index 0000000..c562d84 --- /dev/null +++ b/src/cpu/x86/mtrr/debug.c @@ -0,0 +1,202 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <stdint.h> + +static const char *display_mtrr_type(uint32_t type) +{ + switch (type) { + default: return "reserved"; + case 0: return "UC"; + case 1: return "WC"; + case 4: return "WT"; + case 5: return "WP"; + case 6: return "WB"; + case 7: return "UC-"; + } +} + +static void display_mtrr_fixed_types(uint64_t msr, + uint32_t starting_address, uint32_t memory_size) +{ + uint32_t base_address; + uint32_t index; + uint32_t next_address; + uint32_t next_type; + uint32_t type; + + type = msr & MTRR_DEF_TYPE_MASK; + base_address = starting_address; + next_address = base_address; + for (index = 0; index < 64; index += 8) { + next_address = starting_address + (memory_size * + ((index >> 3) + 1)); + next_type = (msr >> index) & MTRR_DEF_TYPE_MASK; + if (next_type != type) { + printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", + base_address, next_address - 1, + display_mtrr_type(type)); + base_address = next_address; + type = next_type; + } + } + if (base_address != next_address) + printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", + base_address, next_address - 1, + display_mtrr_type(type)); +} + +static void display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address, + const char *name) +{ + union { + uint64_t u64; + msr_t s; + } msr; + + msr.s = rdmsr(msr_reg); + printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); + display_mtrr_fixed_types(msr.u64, starting_address, 0x1000); +} + +static void display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address, + const char *name) +{ + union { + uint64_t u64; + msr_t s; + } msr; + + msr.s = rdmsr(msr_reg); + printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); + display_mtrr_fixed_types(msr.u64, starting_address, 0x4000); +} + +static void display_64k_mtrr(void) +{ + union { + uint64_t u64; + msr_t s; + } msr; + + msr.s = rdmsr(MTRR_FIX_64K_00000); + printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_FIX64K_00000\n", msr.u64); + display_mtrr_fixed_types(msr.u64, 0, 0x10000); +} + +static void display_mtrrcap(void) +{ + msr_t msr; + + msr = rdmsr(MTRR_CAP_MSR); + printk(BIOS_DEBUG, + "0x%08x%08x: IA32_MTRRCAP: %s%s%s%u variable MTRRs\n", + msr.hi, msr.lo, + (msr.lo & MTRR_CAP_SMRR) ? "SMRR, " : "", + (msr.lo & MTRR_CAP_WC) ? "WC, " : "", + (msr.lo & MTRR_CAP_FIX) ? "FIX, " : "", + msr.lo & MTRR_CAP_VCNT); +} + +static void display_mtrr_def_type(void) +{ + union { + uint64_t u64; + msr_t s; + } msr; + + msr.s = rdmsr(MTRR_DEF_TYPE_MSR); + printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_DEF_TYPE:%s%s %s\n", + msr.u64, + (msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "", + (msr.u64 & MTRR_DEF_TYPE_FIX_EN) ? " FE," : "", + display_mtrr_type((uint32_t)(msr.u64 & + MTRR_DEF_TYPE_MASK))); +} + +static void display_variable_mtrr(int index, uint64_t address_mask) +{ + const uint32_t msr_reg = MTRR_PHYS_BASE(index); + uint64_t base_address; + uint64_t length; + uint64_t mask; + union { + uint64_t u64; + msr_t s; + } msr_a; + union { + uint64_t u64; + msr_t s; + } msr_m; + + msr_a.s = rdmsr(msr_reg); + msr_m.s = rdmsr(msr_reg + 1); + if (msr_m.u64 & MTRR_PHYS_MASK_VALID) { + base_address = (msr_a.u64 & 0xfffffffffffff000ULL) + & address_mask; + printk(BIOS_DEBUG, + "0x%016llx: PHYBASE%d: Address = 0x%016llx, %s\n", + msr_a.u64, index, base_address, + display_mtrr_type(msr_a.u64 & MTRR_DEF_TYPE_MASK)); + mask = (msr_m.u64 & 0xfffffffffffff000ULL) & address_mask; + length = (~mask & address_mask) + 1; + printk(BIOS_DEBUG, + "0x%016llx: PHYMASK%d: Length = 0x%016llx, Valid\n", + msr_m.u64, index, length); + } else { + printk(BIOS_DEBUG, "0x%016llx: PHYBASE%d\n", msr_a.u64, index); + printk(BIOS_DEBUG, "0x%016llx: PHYMASK%d: Disabled\n", + msr_m.u64, index); + } +} + +static void _display_mtrrs(void) +{ + uint32_t address_bits; + uint64_t address_mask; + int i; + int variable_mtrrs; + + /* Display the fixed MTRRs */ + display_mtrrcap(); + display_mtrr_def_type(); + display_64k_mtrr(); + display_16k_mtrr(MTRR_FIX_16K_80000, 0x80000, "IA32_MTRR_FIX16K_80000"); + display_16k_mtrr(MTRR_FIX_16K_A0000, 0xa0000, "IA32_MTRR_FIX16K_A0000"); + display_4k_mtrr(MTRR_FIX_4K_C0000, 0xc0000, "IA32_MTRR_FIX4K_C0000"); + display_4k_mtrr(MTRR_FIX_4K_C8000, 0xc8000, "IA32_MTRR_FIX4K_C8000"); + display_4k_mtrr(MTRR_FIX_4K_D0000, 0xd0000, "IA32_MTRR_FIX4K_D0000"); + display_4k_mtrr(MTRR_FIX_4K_D8000, 0xd8000, "IA32_MTRR_FIX4K_D8000"); + display_4k_mtrr(MTRR_FIX_4K_E0000, 0xe0000, "IA32_MTRR_FIX4K_E0000"); + display_4k_mtrr(MTRR_FIX_4K_E8000, 0xe8000, "IA32_MTRR_FIX4K_E8000"); + display_4k_mtrr(MTRR_FIX_4K_F0000, 0xf0000, "IA32_MTRR_FIX4K_F0000"); + display_4k_mtrr(MTRR_FIX_4K_F8000, 0xf8000, "IA32_MTRR_FIX4K_F8000"); + address_bits = cpu_phys_address_size(); + address_mask = (1ULL << address_bits) - 1; + + /* Display the variable MTRRs */ + variable_mtrrs = get_var_mtrr_count(); + for (i = 0; i < variable_mtrrs; i++) + display_variable_mtrr(i, address_mask); +} + +asmlinkage void display_mtrrs(void) +{ + if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) + _display_mtrrs(); +} diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 4ee54a3..02ad85f 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -20,13 +20,11 @@ */ int get_free_var_mtrr(void) { - msr_t msr, maskm; + msr_t maskm; int vcnt; int i; - /* Read MTRRCap and get vcnt - variable memory type ranges. */ - msr = rdmsr(MTRR_CAP_MSR); - vcnt = msr.lo & 0xff; + vcnt = get_var_mtrr_count(); /* Identify the first var mtrr which is not valid. */ for (i = 0; i < vcnt; i++) { diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index cd56ea8..cdc8e93 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -66,7 +66,7 @@ 1: #endif /* Display the MTRRs */ - call soc_display_mtrrs + call display_mtrrs /* * The stack contents are initialized in src/soc/intel/common/stack.c diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 4016ba1..13161d6 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -15,10 +15,10 @@ #include <arch/early_variables.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> #include <fsp/car.h> #include <fsp/util.h> #include <program_loading.h> -#include <soc/intel/common/util.h> #include <timestamp.h> FSP_INFO_HEADER *fih_car CAR_GLOBAL; @@ -95,7 +95,7 @@ { timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END); printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n"); - soc_display_mtrrs(); + display_mtrrs(); after_cache_as_ram_stage(); } diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index a9f6a8d..13769b3 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -18,7 +18,6 @@ #define _INTEL_COMMON_RAMSTAGE_H_ #include <fsp/util.h> -#include <soc/intel/common/util.h> #include <stdint.h> /* diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index d79be70..e266bee 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -22,7 +22,6 @@ #include <memory_info.h> #include <fsp/car.h> #include <fsp/util.h> -#include <soc/intel/common/util.h> #include <soc/intel/common/mma.h> #include <soc/pei_wrapper.h> #include <soc/pm.h> /* chip_power_state */ diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c index 06c0e63..eb2a637 100644 --- a/src/drivers/intel/fsp1_1/stack.c +++ b/src/drivers/intel/fsp1_1/stack.c @@ -38,12 +38,12 @@ uint32_t *slot; /* Display the MTRRs */ - soc_display_mtrrs(); + display_mtrrs(); /* Top of stack needs to be aligned to a 8-byte boundary. */ slot = (void *)romstage_ram_stack_top(); num_mtrrs = 0; - max_mtrrs = soc_get_variable_mtrr_count(NULL); + max_mtrrs = get_var_mtrr_count(); /* * The upper bits of the MTRR mask need to set according to the number diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 8f4dc1e..d098772 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -11,8 +11,8 @@ #include <console/console.h> #include <console/streams.h> +#include <cpu/x86/mtrr.h> #include <fsp/util.h> -#include <soc/intel/common/util.h> asmlinkage size_t fsp_write_line(uint8_t *buffer, size_t number_of_bytes) { @@ -28,9 +28,7 @@ const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_new_upd) { - /* Display the MTRRs */ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) - soc_display_mtrrs(); + display_mtrrs(); /* Display the UPD values */ if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) @@ -62,9 +60,7 @@ if (IS_ENABLED(CONFIG_VERIFY_HOBS)) fsp_verify_memory_init_hobs(); - /* Display the MTRRs */ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) - soc_display_mtrrs(); + display_mtrrs(); } /*----------- @@ -75,9 +71,7 @@ const FSPS_UPD *fsps_old_upd, const FSPS_UPD *fsps_new_upd) { - /* Display the MTRRs */ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) - soc_display_mtrrs(); + display_mtrrs(); /* Display the UPD values */ if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) @@ -99,9 +93,7 @@ if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) fsp_display_hobs(); - /* Display the MTRRs */ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) - soc_display_mtrrs(); + display_mtrrs(); } /*----------- @@ -129,7 +121,5 @@ if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) fsp_display_hobs(); - /* Display the MTRRs */ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) - soc_display_mtrrs(); + display_mtrrs(); } diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index c3a2804..a5c7ef0 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -12,8 +12,8 @@ #include <bootstate.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> #include <fsp/util.h> -#include <soc/intel/common/util.h> #include <string.h> #include <timestamp.h> @@ -70,9 +70,7 @@ { enum fsp_notify_phase phase = (uint32_t)arg; - /* Display the MTRRs */ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) - soc_display_mtrrs(); + display_mtrrs(); fsp_notify(phase); if (phase == READY_TO_BOOT) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 1f704ac..eb7d78d 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -99,10 +99,17 @@ * This function needs to be called after the first MTRR solution is derived. */ void mtrr_use_temp_range(uintptr_t begin, size_t size, int type); +static inline int get_var_mtrr_count(void) +{ + return rdmsr(MTRR_CAP_MSR).lo & MTRR_CAP_VCNT; +} + void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, unsigned int type); int get_free_var_mtrr(void); +asmlinkage void display_mtrrs(void); + /* * Set the MTRRs using the data on the stack from setup_stack_and_mtrrs. * Return a new top_of_stack value which removes the setup_stack_and_mtrrs data. diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 27d3f59..b5caf40 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -1,5 +1,6 @@ config SOC_INTEL_COMMON bool + select HAVE_DISPLAY_MTRRS help common code for Intel SOCs @@ -14,10 +15,6 @@ comment "Intel SoC Common coreboot stages" source "src/soc/intel/common/basecode/Kconfig" -config DISPLAY_MTRRS - bool "MTRRs: Display the MTRR settings" - default n - config DISPLAY_SMM_MEMORY_MAP bool "SMM: Display the SMM memory map" default n diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 11a4575..22d350c 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -4,23 +4,18 @@ subdirs-y += block/ subdirs-y += pch/ -bootblock-y += util.c - verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c bootblock-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c -romstage-y += util.c romstage-$(CONFIG_MMA) += mma.c romstage-y += smbios.c -postcar-y += util.c postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-y += hda_verb.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c -ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c diff --git a/src/soc/intel/common/util.c b/src/soc/intel/common/util.c deleted file mode 100644 index fadef60..0000000 --- a/src/soc/intel/common/util.c +++ /dev/null @@ -1,224 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <soc/intel/common/util.h> -#include <stddef.h> - -uint32_t soc_get_variable_mtrr_count(uint64_t *msr) -{ - union { - uint64_t u64; - msr_t s; - } mtrrcap; - - mtrrcap.s = rdmsr(MTRR_CAP_MSR); - if (msr != NULL) - *msr = mtrrcap.u64; - return mtrrcap.u64 & MTRR_CAP_VCNT; -} - -static const char *soc_display_mtrr_type(uint32_t type) -{ - switch (type) { - default: return "reserved"; - case 0: return "UC"; - case 1: return "WC"; - case 4: return "WT"; - case 5: return "WP"; - case 6: return "WB"; - case 7: return "UC-"; - } -} - -static void soc_display_mtrr_fixed_types(uint64_t msr, - uint32_t starting_address, uint32_t memory_size) -{ - uint32_t base_address; - uint32_t index; - uint32_t next_address; - uint32_t next_type; - uint32_t type; - - type = msr & MTRR_DEF_TYPE_MASK; - base_address = starting_address; - next_address = base_address; - for (index = 0; index < 64; index += 8) { - next_address = starting_address + (memory_size * - ((index >> 3) + 1)); - next_type = (msr >> index) & MTRR_DEF_TYPE_MASK; - if (next_type != type) { - printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", - base_address, next_address - 1, - soc_display_mtrr_type(type)); - base_address = next_address; - type = next_type; - } - } - if (base_address != next_address) - printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", - base_address, next_address - 1, - soc_display_mtrr_type(type)); -} - -static void soc_display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address, - const char *name) -{ - union { - uint64_t u64; - msr_t s; - } msr; - - msr.s = rdmsr(msr_reg); - printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); - soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x1000); -} - -static void soc_display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address, - const char *name) -{ - union { - uint64_t u64; - msr_t s; - } msr; - - msr.s = rdmsr(msr_reg); - printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); - soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x4000); -} - -static void soc_display_64k_mtrr(void) -{ - union { - uint64_t u64; - msr_t s; - } msr; - - msr.s = rdmsr(MTRR_FIX_64K_00000); - printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_FIX64K_00000\n", msr.u64); - soc_display_mtrr_fixed_types(msr.u64, 0, 0x10000); -} - -static uint32_t soc_display_mtrrcap(void) -{ - uint64_t msr; - uint32_t variable_mtrrs; - - variable_mtrrs = soc_get_variable_mtrr_count(&msr); - printk(BIOS_DEBUG, - "0x%016llx: IA32_MTRRCAP: %s%s%s%d variable MTRRs\n", - msr, - (msr & MTRR_CAP_SMRR) ? "SMRR, " : "", - (msr & MTRR_CAP_WC) ? "WC, " : "", - (msr & MTRR_CAP_FIX) ? "FIX, " : "", - variable_mtrrs); - return variable_mtrrs; -} - -static void soc_display_mtrr_def_type(void) -{ - union { - uint64_t u64; - msr_t s; - } msr; - - msr.s = rdmsr(MTRR_DEF_TYPE_MSR); - printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_DEF_TYPE:%s%s %s\n", - msr.u64, - (msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "", - (msr.u64 & MTRR_DEF_TYPE_FIX_EN) ? " FE," : "", - soc_display_mtrr_type((uint32_t)(msr.u64 & - MTRR_DEF_TYPE_MASK))); -} - -static void soc_display_variable_mtrr(uint32_t msr_reg, int index, - uint64_t address_mask) -{ - uint64_t base_address; - uint64_t length; - uint64_t mask; - union { - uint64_t u64; - msr_t s; - } msr_a; - union { - uint64_t u64; - msr_t s; - } msr_m; - - msr_a.s = rdmsr(msr_reg); - msr_m.s = rdmsr(msr_reg + 1); - if (msr_m.u64 & MTRR_PHYS_MASK_VALID) { - base_address = (msr_a.u64 & 0xfffffffffffff000ULL) - & address_mask; - printk(BIOS_DEBUG, - "0x%016llx: PHYBASE%d: Address = 0x%016llx, %s\n", - msr_a.u64, index, base_address, - soc_display_mtrr_type(msr_a.u64 & MTRR_DEF_TYPE_MASK)); - mask = (msr_m.u64 & 0xfffffffffffff000ULL) & address_mask; - length = (~mask & address_mask) + 1; - printk(BIOS_DEBUG, - "0x%016llx: PHYMASK%d: Length = 0x%016llx, Valid\n", - msr_m.u64, index, length); - } else { - printk(BIOS_DEBUG, "0x%016llx: PHYBASE%d\n", msr_a.u64, index); - printk(BIOS_DEBUG, "0x%016llx: PHYMASK%d: Disabled\n", - msr_m.u64, index); - } -} - -asmlinkage void soc_display_mtrrs(void) -{ - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) { - uint32_t address_bits; - uint64_t address_mask; - int i; - int variable_mtrrs; - - /* Display the fixed MTRRs */ - variable_mtrrs = soc_display_mtrrcap(); - soc_display_mtrr_def_type(); - soc_display_64k_mtrr(); - soc_display_16k_mtrr(MTRR_FIX_16K_80000, 0x80000, - "IA32_MTRR_FIX16K_80000"); - soc_display_16k_mtrr(MTRR_FIX_16K_A0000, 0xa0000, - "IA32_MTRR_FIX16K_A0000"); - soc_display_4k_mtrr(MTRR_FIX_4K_C0000, 0xc0000, - "IA32_MTRR_FIX4K_C0000"); - soc_display_4k_mtrr(MTRR_FIX_4K_C8000, 0xc8000, - "IA32_MTRR_FIX4K_C8000"); - soc_display_4k_mtrr(MTRR_FIX_4K_D0000, 0xd0000, - "IA32_MTRR_FIX4K_D0000"); - soc_display_4k_mtrr(MTRR_FIX_4K_D8000, 0xd8000, - "IA32_MTRR_FIX4K_D8000"); - soc_display_4k_mtrr(MTRR_FIX_4K_E0000, 0xe0000, - "IA32_MTRR_FIX4K_E0000"); - soc_display_4k_mtrr(MTRR_FIX_4K_E8000, 0xe8000, - "IA32_MTRR_FIX4K_E8000"); - soc_display_4k_mtrr(MTRR_FIX_4K_F0000, 0xf0000, - "IA32_MTRR_FIX4K_F0000"); - soc_display_4k_mtrr(MTRR_FIX_4K_F8000, 0xf8000, - "IA32_MTRR_FIX4K_F8000"); - address_bits = cpu_phys_address_size(); - address_mask = (1ULL << address_bits) - 1; - - /* Display the variable MTRRs */ - for (i = 0; i < variable_mtrrs; i++) - soc_display_variable_mtrr(MTRR_PHYS_BASE(i), i, - address_mask); - } -} diff --git a/src/soc/intel/common/util.h b/src/soc/intel/common/util.h deleted file mode 100644 index 854f2b0..0000000 --- a/src/soc/intel/common/util.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _INTEL_COMMON_UTIL_H_ -#define _INTEL_COMMON_UTIL_H_ - -#include <arch/cpu.h> -#include <cpu/x86/msr.h> -#include <stdint.h> - -asmlinkage void soc_display_mtrrs(void); -uint32_t soc_get_variable_mtrr_count(uint64_t *msr); - -#endif /* _INTEL_COMMON_UTIL_H_ */ diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 741f5d3..654f0a7 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -16,6 +16,7 @@ ifeq ($(CONFIG_SOC_INTEL_QUARK),y) subdirs-y += romstage +subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/esram_init.S diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index 38730ea..d3aa900 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -15,10 +15,10 @@ */ #include <bootblock_common.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> #include <device/pci_def.h> #include <program_loading.h> #include <soc/iomap.h> -#include <soc/intel/common/util.h> #include <soc/pci_devs.h> #include <soc/reg_access.h> @@ -112,8 +112,7 @@ if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_INIT_ENTRY)) light_sd_led(); - /* Display the MTRRs */ - soc_display_mtrrs(); + display_mtrrs(); } void platform_prog_run(struct prog *prog) diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 4ad0fedc..821f43e 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -17,6 +17,7 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ +#include <arch/cpu.h> #include <chip.h> #include <device/device.h> #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c index 6f2f00c..47bfde4 100644 --- a/src/soc/intel/quark/romstage/mtrr.c +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -16,7 +16,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <soc/intel/common/util.h> #include <soc/pci_devs.h> #include <soc/reg_access.h> diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat index 267673a..3417212 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat @@ -40,8 +40,6 @@ smm_region_size soc_after_ram_init soc_display_memory_init_params -soc_display_mtrrs -soc_get_variable_mtrr_count soc_memory_init_params soc_pre_ram_init southbridge_smi_handler diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat index 70f204d..0835190 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat @@ -23,8 +23,6 @@ save_chromeos_gpios soc_after_ram_init soc_display_memory_init_params -soc_display_mtrrs -soc_get_variable_mtrr_count soc_memory_init_params soc_pre_ram_init southbridge_smi_handler diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat index 2124f0f..0910152 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat @@ -22,8 +22,6 @@ platform_prog_run platform_segment_loaded save_chromeos_gpios -soc_display_mtrrs -soc_get_variable_mtrr_count stage_cache_add stage_cache_load_stage timestamp_get diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat index f589eaa..fe1f0d9 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat @@ -9,8 +9,6 @@ mainboard_post platform_prog_run platform_segment_loaded -soc_display_mtrrs -soc_get_variable_mtrr_count stage_cache_add stage_cache_load_stage timestamp_get -- To view, visit https://review.coreboot.org/29684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Gerrit-Change-Number: 29684 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in coreboot[master]: Revert "soc/intel/common/block: add VMX support"
by Nico Huber (Code Review) 17 Nov '18

17 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29683 Change subject: Revert "soc/intel/common/block: add VMX support" ...................................................................... Revert "soc/intel/common/block: add VMX support" This reverts commit 9aae51ad1141a47d5c2f7133b02f5f0ab6168860. Proper code in cpu/intel/common/ should be used instead. Change-Id: I4a5d558b03497d106083eece10c5b34e0e7cbb2d Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- D src/soc/intel/common/block/include/intelblocks/vmx.h D src/soc/intel/common/block/vmx/Kconfig D src/soc/intel/common/block/vmx/Makefile.inc D src/soc/intel/common/block/vmx/vmx.c 4 files changed, 0 insertions(+), 108 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/29683/1 diff --git a/src/soc/intel/common/block/include/intelblocks/vmx.h b/src/soc/intel/common/block/include/intelblocks/vmx.h deleted file mode 100644 index b93ceeb..0000000 --- a/src/soc/intel/common/block/include/intelblocks/vmx.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOC_INTEL_COMMON_BLOCK_VMX_H -#define SOC_INTEL_COMMON_BLOCK_VMX_H - -#include <stdint.h> - -struct vmx_param { - uint8_t enable; -}; - -/* - * Configure VMX. - */ -void vmx_configure(void *unused); - -/* SOC specific API to get VMX params. - * returns 0, if able to get VMX params; otherwise returns -1 */ -int soc_fill_vmx_param(struct vmx_param *vmx_param); - -#endif /* SOC_INTEL_COMMON_BLOCK_VMX_H */ diff --git a/src/soc/intel/common/block/vmx/Kconfig b/src/soc/intel/common/block/vmx/Kconfig deleted file mode 100644 index f8dce07..0000000 --- a/src/soc/intel/common/block/vmx/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config SOC_INTEL_COMMON_BLOCK_VMX - bool "Enable VMX for virtualization" - default n diff --git a/src/soc/intel/common/block/vmx/Makefile.inc b/src/soc/intel/common/block/vmx/Makefile.inc deleted file mode 100644 index 861e2f9..0000000 --- a/src/soc/intel/common/block/vmx/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_VMX) += vmx.c diff --git a/src/soc/intel/common/block/vmx/vmx.c b/src/soc/intel/common/block/vmx/vmx.c deleted file mode 100644 index 2cffdab..0000000 --- a/src/soc/intel/common/block/vmx/vmx.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <intelblocks/msr.h> -#include <intelblocks/vmx.h> -#include <soc/cpu.h> -#include <string.h> - -static bool vmx_param_valid; -static struct vmx_param g_vmx_param; - -static const struct vmx_param *get_vmx_param(void) -{ - if (vmx_param_valid) - return &g_vmx_param; - - memset(&g_vmx_param, 0, sizeof(g_vmx_param)); - if (soc_fill_vmx_param(&g_vmx_param) < 0) { - printk(BIOS_ERR, "VMX : Failed to get soc vmx param\n"); - return NULL; - } - vmx_param_valid = true; - printk(BIOS_INFO, "VMX : param.enable = %d\n", g_vmx_param.enable); - - return &g_vmx_param; -} - -static int soc_vmx_enabled(void) -{ - const struct vmx_param *vmx_param = get_vmx_param(); - return vmx_param ? vmx_param->enable : 0; -} - -void vmx_configure(void *unused) -{ - msr_t msr; - struct cpuid_result regs; - - regs = cpuid(1); - - if (!soc_vmx_enabled() || !(regs.ecx & CPUID_VMX)) { - printk(BIOS_ERR, "VMX: pre-conditions not met\n"); - return; - } - - msr = rdmsr(IA32_FEATURE_CONTROL); - - /* Only enable it when it is not locked */ - if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) { - /* Enable VMX */ - msr.lo |= FEATURE_ENABLE_VMX; - wrmsr(IA32_FEATURE_CONTROL, msr); - } - - /* Report current status */ - msr = rdmsr(IA32_FEATURE_CONTROL); - printk(BIOS_DEBUG, "VMX status: %s, %s\n", - (msr.lo & FEATURE_ENABLE_VMX) ? "enabled" : "disabled", - (msr.lo & FEATURE_CONTROL_LOCK_BIT) ? "locked" : "unlocked"); -} -- To view, visit https://review.coreboot.org/29683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4a5d558b03497d106083eece10c5b34e0e7cbb2d Gerrit-Change-Number: 29683 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in coreboot[master]: Revert "soc/intel/skylake: enable VMX support"
by Nico Huber (Code Review) 17 Nov '18

17 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29682 Change subject: Revert "soc/intel/skylake: enable VMX support" ...................................................................... Revert "soc/intel/skylake: enable VMX support" This reverts commit 969ef10f5409f70f85b76f3a7c5b5a4e4a637ee9. It ignores a devicetree setting based on a Kconfig, probably con- flicts with what FSP does and doesn't use the existing code in cpu/intel/common/. Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M 3rdparty/chromeec M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/cpu.c 3 files changed, 1 insertion(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/29682/1 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 11bd4c0..b45641f 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 11bd4c0f4d11357ab830982d7dec164813c886dd +Subproject commit b45641f331b8ffaff2e2e94ffc758b3d966e2e34 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 3a2b50b..d6de918 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -67,7 +67,6 @@ select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_UART - select SOC_INTEL_COMMON_BLOCK_VMX select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 9e4bbe8..4d99d5e 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -38,7 +38,6 @@ #include <intelblocks/mp_init.h> #include <intelblocks/sgx.h> #include <intelblocks/smm.h> -#include <intelblocks/vmx.h> #include <pc80/mc146818rtc.h> #include <soc/cpu.h> #include <soc/msr.h> @@ -483,8 +482,6 @@ smm_lock(); #endif - mp_run_on_all_cpus(vmx_configure, NULL, 2 * USECS_PER_MSEC); - mp_run_on_all_cpus(sgx_configure, NULL, 14 * USECS_PER_MSEC); } @@ -566,22 +563,3 @@ sgx_param->enable = conf->sgx_enable; return 0; } -int soc_fill_vmx_param(struct vmx_param *vmx_param) -{ - struct device *dev = SA_DEV_ROOT; - config_t *conf; - - if (!dev) { - printk(BIOS_ERR, "Failed to get root dev for checking VMX param\n"); - return -1; - } - - conf = dev->chip_info; - if (!conf) { - printk(BIOS_ERR, "Failed to get chip_info for VMX param\n"); - return -1; - } - - vmx_param->enable = conf->VmxEnable; - return 0; -} -- To view, visit https://review.coreboot.org/29682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f Gerrit-Change-Number: 29682 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in coreboot[master]: soc/intel: Drop pmc_get_mainboard_power_failure_state_choice()
by Nico Huber (Code Review) 17 Nov '18

17 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29681 Change subject: soc/intel: Drop pmc_get_mainboard_power_failure_state_choice() ...................................................................... soc/intel: Drop pmc_get_mainboard_power_failure_state_choice() It's not needed anymore. Change-Id: I273acb2bf1675dc947927e3e6d2ebb78aa94518a Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/cannonlake/pmc.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/icelake/pmc.c M src/soc/intel/skylake/pmc.c 5 files changed, 6 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29681/1 diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index ecd47e0..aebcfc9 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -57,8 +57,7 @@ */ void pmc_soc_restore_power_failure(void) { - pmc_set_afterg3(PCH_DEV_PMC, - pmc_get_mainboard_power_failure_state_choice()); + pmc_set_afterg3(PCH_DEV_PMC, CONFIG_MAINBOARD_POWER_FAILURE_STATE); } static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) @@ -106,8 +105,7 @@ { const char *state; - /* Get the chip configuration */ - int pwr_on = pmc_get_mainboard_power_failure_state_choice(); + const int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; /* * Which state do we want to goto after g3 (power restored)? diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 4569525..e1c29be 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -221,10 +221,4 @@ MAINBOARD_POWER_STATE_PREVIOUS, }; -/* - * Determines what state to go to when power is reapplied - * after a power failure (G3 State) - */ -int pmc_get_mainboard_power_failure_state_choice(void); - #endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */ diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index dcc7cc9..4a1da9e 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -580,12 +580,3 @@ /* Set the routes in the GPIO communities as well. */ gpio_route_gpe(dw0, dw1, dw2); } - -/* - * Determines what state to go to when power is reapplied - * after a power failure (G3 State) - */ -int pmc_get_mainboard_power_failure_state_choice(void) -{ - return CONFIG_MAINBOARD_POWER_FAILURE_STATE; -} diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 2453210..754aa50 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -55,8 +55,7 @@ */ void pmc_soc_restore_power_failure(void) { - pmc_set_afterg3(PCH_DEV_PMC, - pmc_get_mainboard_power_failure_state_choice()); + pmc_set_afterg3(PCH_DEV_PMC, CONFIG_MAINBOARD_POWER_FAILURE_STATE); } static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) @@ -104,8 +103,7 @@ { const char *state; - /* Get the chip configuration */ - int pwr_on = pmc_get_mainboard_power_failure_state_choice(); + const int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; /* * Which state do we want to goto after g3 (power restored)? diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 6b673be..5b82392 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -108,8 +108,7 @@ { const char *state; - /* Get the chip configuration */ - int pwr_on = pmc_get_mainboard_power_failure_state_choice(); + const int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; /* * Which state do we want to goto after g3 (power restored)? @@ -206,8 +205,7 @@ */ void pmc_soc_restore_power_failure(void) { - pmc_set_afterg3(PCH_DEV_PMC, - pmc_get_mainboard_power_failure_state_choice()); + pmc_set_afterg3(PCH_DEV_PMC, CONFIG_MAINBOARD_POWER_FAILURE_STATE); } static void pm1_enable_pwrbtn_smi(void *unused) -- To view, visit https://review.coreboot.org/29681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I273acb2bf1675dc947927e3e6d2ebb78aa94518a Gerrit-Change-Number: 29681 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in coreboot[master]: Kconfig: Unify power-after-failure options
by Nico Huber (Code Review) 17 Nov '18

17 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29680 Change subject: Kconfig: Unify power-after-failure options ...................................................................... Kconfig: Unify power-after-failure options The newest and most useful incarnation was hiding in soc/intel/common/. We move it into the Mainboard menu and extend it with various flags to be selected to control the default and which options are visible. Also add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the boolean to int conversion into Kconfig: 0 - S5 1 - S1 2 - previous state This patch focuses on the Kconfig code. The C code could be unified as well, e.g. starting with a common enum and safe wrapper around the get_option() call. TEST=Did what-jenkins-does with and without this commit and compared binaries. Nothing changed for the default configurations. Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/Kconfig M src/mainboard/asus/kcma-d8/Kconfig M src/mainboard/asus/kfsn4-dre/Kconfig M src/mainboard/asus/kgpe-d16/Kconfig M src/mainboard/msi/ms9652_fam10/Kconfig M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/stumpy/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/pmclib.c M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/amd8111/Kconfig M src/southbridge/amd/amd8111/acpi.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/sb700/Kconfig M src/southbridge/amd/sb700/sm.c M src/southbridge/amd/sb800/sm.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/fsp_bd82x6x/Kconfig M src/southbridge/intel/fsp_bd82x6x/lpc.c M src/southbridge/intel/fsp_bd82x6x/pch.h M src/southbridge/intel/fsp_bd82x6x/smihandler.c M src/southbridge/intel/fsp_i89xx/Kconfig M src/southbridge/intel/fsp_i89xx/lpc.c M src/southbridge/intel/fsp_i89xx/pch.h M src/southbridge/intel/fsp_i89xx/smihandler.c M src/southbridge/intel/fsp_rangeley/soc.h M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/nvidia/ck804/Kconfig M src/southbridge/nvidia/ck804/lpc.c M src/southbridge/nvidia/mcp55/Kconfig M src/southbridge/nvidia/mcp55/lpc.c M src/superio/nuvoton/nct5572d/Kconfig M src/superio/nuvoton/nct5572d/superio.c M src/superio/winbond/w83667hg-a/Kconfig M src/superio/winbond/w83667hg-a/superio.c 62 files changed, 145 insertions(+), 171 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29680/1 diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 04dca4a..cd488f2 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -180,3 +180,59 @@ config ENABLE_POWER_BUTTON def_bool y if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_ENABLE def_bool n if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_DISABLE + +config HAVE_POWER_STATE_AFTER_FAILURE + bool + +if HAVE_POWER_STATE_AFTER_FAILURE + +config HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + bool + +config POWER_STATE_DEFAULT_ON_AFTER_FAILURE + bool + help + Selected by mainboards that want to override a "default off" + that was set at chip level. + +config POWER_STATE_DEFAULT_OFF_AFTER_FAILURE + bool + help + Selected by mainboards or chips that want a "default off" behaviour. + +choice + prompt "System Power State after Failure" + default POWER_STATE_OFF_AFTER_FAILURE \ + if !POWER_STATE_DEFAULT_ON_AFTER_FAILURE && \ + POWER_STATE_DEFAULT_OFF_AFTER_FAILURE + default POWER_STATE_ON_AFTER_FAILURE + +config POWER_STATE_OFF_AFTER_FAILURE + bool "S5 Soft Off" + help + Choose this option if you want to put system into + S5 after reapplying power after failure. + +config POWER_STATE_ON_AFTER_FAILURE + bool "S0 Full On" + help + Choose this option if you want to keep system in + S0 after reapplying power after failure. + +config POWER_STATE_PREVIOUS_AFTER_FAILURE + bool "Keep Previous State" + depends on HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + help + Choose this option if you want to keep system in the + same power state as before failure after reapplying + power. + +endchoice + +config MAINBOARD_POWER_FAILURE_STATE + int + default 2 if POWER_STATE_PREVIOUS_AFTER_FAILURE + default 1 if POWER_STATE_ON_AFTER_FAILURE + default 0 + +endif # HAVE_POWER_STATE_AFTER_FAILURE diff --git a/src/mainboard/asus/kcma-d8/Kconfig b/src/mainboard/asus/kcma-d8/Kconfig index f20cf21..712755e 100644 --- a/src/mainboard/asus/kcma-d8/Kconfig +++ b/src/mainboard/asus/kcma-d8/Kconfig @@ -32,6 +32,7 @@ select DRIVERS_ASPEED_AST2050 select MAINBOARD_FORCE_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT + select POWER_STATE_DEFAULT_ON_AFTER_FAILURE config MAINBOARD_DIR string @@ -90,10 +91,6 @@ bool default y -config MAINBOARD_POWER_ON_AFTER_POWER_FAIL - bool - default y - config MAX_REBOOT_CNT int default 10 diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index 55bd5c3..1597d1c 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -19,6 +19,7 @@ select ENABLE_APIC_EXT_ID select DRIVERS_I2C_W83793 select DRIVERS_XGI_Z9S + select POWER_STATE_DEFAULT_ON_AFTER_FAILURE config MAINBOARD_DIR string @@ -80,10 +81,6 @@ bool default y -config MAINBOARD_POWER_ON_AFTER_POWER_FAIL - bool - default y - config MAX_REBOOT_CNT int default 10 diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 8028849..b21f8ad 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -33,6 +33,7 @@ select DRIVERS_ASPEED_AST2050 select MAINBOARD_FORCE_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT + select POWER_STATE_DEFAULT_ON_AFTER_FAILURE config MAINBOARD_DIR string @@ -95,10 +96,6 @@ string default "1a03,2000" -config MAINBOARD_POWER_ON_AFTER_POWER_FAIL - bool - default y - config MAX_REBOOT_CNT int default 10 diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index 080fc58..6cf8606 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -20,6 +20,7 @@ select LIFT_BSP_APIC_ID select IOAPIC select SMP + select POWER_STATE_DEFAULT_ON_AFTER_FAILURE config MAINBOARD_DIR string @@ -59,10 +60,6 @@ int default 9 -config MAINBOARD_POWER_ON_AFTER_POWER_FAIL - bool - default y - config USBDEBUG bool default n diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 9cb0e5f..6829ecc 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -44,10 +44,6 @@ string default "pci8086,0106.rom" -config MAINBOARD_POWER_ON_AFTER_POWER_FAIL - bool - default n - if EARLY_PCI_BRIDGE config EARLY_PCI_BRIDGE_DEVICE diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index f0ac4f7..49210bc 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -42,8 +42,4 @@ string default "pci8086,0106.rom" -config MAINBOARD_POWER_ON_AFTER_POWER_FAIL - bool - default n - endif # BOARD_SAMSUNG_STUMPY diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 18ec51f..3f06d4a 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -40,6 +40,9 @@ select HAVE_SPI_CONSOLE_SUPPORT select CPU_INTEL_COMMON select INTEL_GMA_ACPI + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE config PCIEXP_ASPM bool diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 87aaf6b..762198b1 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -152,7 +152,7 @@ const char *state; /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; /* Which state do we want to goto after g3 (power restored)? * 0 == S0 Full On diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 24f6a3d..1ba2bdd 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -156,7 +156,7 @@ u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; /* save and recover RTC port values */ u8 tmp70, tmp72; diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 9b21010..4569525 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -213,6 +213,7 @@ * 0 == S5 Soft Off * 1 == S0 Full On * 2 == Keep Previous State + * Keep in sync with `config MAINBOARD_POWER_FAILURE_STATE`. */ enum { MAINBOARD_POWER_STATE_OFF, diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index 2f08408..244f59c 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -2,35 +2,12 @@ depends on SOC_INTEL_COMMON_BLOCK_GPIO depends on ACPI_INTEL_HARDWARE_SLEEP_VALUES bool + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE help Intel Processor common code for Power Management controller(PMC) subsystem -choice - prompt "System Power State after Failure" - default POWER_STATE_ON_AFTER_FAILURE - -config POWER_STATE_OFF_AFTER_FAILURE - bool "S5 Soft Off" - help - Choose this option if you want to keep system into - S5 after reapplying power after failure - -config POWER_STATE_ON_AFTER_FAILURE - bool "S0 Full On" - help - Choose this option if you want to keep system into - S0 after reapplying power after failure - -config POWER_STATE_PREVIOUS_AFTER_FAILURE - bool "Keep Previous State" - help - Choose this option if you want to keep system into - same power state as before failure even after reapplying - power - -endchoice - config PMC_INVALID_READ_AFTER_WRITE bool default n diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index ef4384d..dcc7cc9 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -587,10 +587,5 @@ */ int pmc_get_mainboard_power_failure_state_choice(void) { - if (IS_ENABLED(CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE)) - return MAINBOARD_POWER_STATE_PREVIOUS; - else if (IS_ENABLED(CONFIG_POWER_STATE_ON_AFTER_FAILURE)) - return MAINBOARD_POWER_STATE_ON; - - return MAINBOARD_POWER_STATE_OFF; + return CONFIG_MAINBOARD_POWER_FAILURE_STATE; } diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index 08ec59f..3250585 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -31,10 +31,6 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - #define BIT0 (1 << 0) #define BIT1 (1 << 1) #define BIT2 (1 << 2) diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig index 1436d8c..9764c95 100644 --- a/src/southbridge/amd/amd8111/Kconfig +++ b/src/southbridge/amd/amd8111/Kconfig @@ -16,6 +16,8 @@ config SOUTHBRIDGE_AMD_AMD8111 bool select IOAPIC + select HAVE_POWER_STATE_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index 8dc2007..5216a10 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -29,11 +29,6 @@ #define SLOW_CPU_OFF 0 #define SLOW_CPU__ON 1 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - - static int lsmbus_recv_byte(struct device *dev) { unsigned int device; @@ -148,7 +143,7 @@ pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5)); /* power on after power fail */ - on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 3625f8a..5c809d6 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -31,10 +31,6 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* * HUDSON enables all USB controllers by default in SMBUS Control. * HUDSON enables SATA by default in SMBUS Control. diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 6d62e67..78332cf 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -23,6 +23,9 @@ select IOAPIC select HAVE_USBDEBUG_OPTIONS select SMBUS_HAS_AUX_CHANNELS + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI bool "Enable high speed SPI clock" diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 64c6db3..4c3992d 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -44,10 +44,6 @@ POWER_MODE_LAST = 2, }; -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL POWER_MODE_ON -#endif - static const char *power_mode_names[] = { [POWER_MODE_OFF] = "off", [POWER_MODE_ON] = "on", @@ -152,11 +148,11 @@ pm_iowrite(0x53, byte); /* power after power fail */ - power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + power_state = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&power_state, "power_on_after_fail"); if (power_state > 2) { printk(BIOS_WARNING, "Invalid power_on_after_fail setting, using default\n"); - power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + power_state = CONFIG_MAINBOARD_POWER_FAILURE_STATE; } byte = pm_ioread(0x74); byte &= ~0x03; diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index fdb6283..1d2daed8 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -32,10 +32,6 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - #define BIT0 (1 << 0) #define BIT1 (1 << 1) #define BIT2 (1 << 2) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7ae538e..bee82b9 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -181,7 +181,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 957faa5..951aecb 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -29,6 +29,9 @@ config SOUTHBRIDGE_INTEL_COMMON_SMM def_bool n + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT bool diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index c578982..8b71627 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -35,10 +35,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - #define PM1_STS 0x00 #define WAK_STS (1 << 15) #define PCIEXPWAK_STS (1 << 14) diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 0ad400c..3d51257 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -112,7 +112,7 @@ u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; // save and recover RTC port values u8 tmp70, tmp72; diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index 52810ab..7445012 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -33,6 +33,9 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select HAVE_INTEL_CHIPSET_LOCKDOWN + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE config EHCI_BAR hex diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index bc9e06b..fa664ad 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -192,7 +192,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index 1f1c18a..bfcb9e9 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -96,10 +96,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index dedc4be..156c3ec 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -306,7 +306,7 @@ u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; // save and recover RTC port values u8 tmp70, tmp72; diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig index 0bc9586..d570068 100644 --- a/src/southbridge/intel/fsp_i89xx/Kconfig +++ b/src/southbridge/intel/fsp_i89xx/Kconfig @@ -33,6 +33,9 @@ select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE config EHCI_BAR hex diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c index 8019b02..d079328 100644 --- a/src/southbridge/intel/fsp_i89xx/lpc.c +++ b/src/southbridge/intel/fsp_i89xx/lpc.c @@ -192,7 +192,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h index 3382cbd..7b96708 100644 --- a/src/southbridge/intel/fsp_i89xx/pch.h +++ b/src/southbridge/intel/fsp_i89xx/pch.h @@ -93,10 +93,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) #define PCH_PCIE_DEV_SLOT 28 diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c index e22faad..81fdb43 100644 --- a/src/southbridge/intel/fsp_i89xx/smihandler.c +++ b/src/southbridge/intel/fsp_i89xx/smihandler.c @@ -305,7 +305,7 @@ u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; // save and recover RTC port values u8 tmp70, tmp72; diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index ffadee4..9d86407 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -80,10 +80,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - #define SOC_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCIE_DEV_SLOT0 1 #define PCIE_DEV_SLOT1 2 diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 827f6bb..f4357b8 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -22,6 +22,9 @@ select HAVE_USBDEBUG select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE if SOUTHBRIDGE_INTEL_I82801DX diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 8c7da55..678d5d7 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -45,10 +45,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* * 000 = Non-combined. P0 is primary master. P1 is secondary master. * 001 = Non-combined. P0 is secondary master. P1 is primary master. diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 925251d..3c74e98 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -103,7 +103,7 @@ u32 reg32; const char *state; - int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index b2b4662..e7a9589 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -276,7 +276,7 @@ * CMOS or even better from GNVS. Right now it's hard * coded at compile time. */ - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; /* First, disable further SMIs */ reg8 = inb(pmbase + SMI_EN); diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 28d42ff..69cb2e7 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -28,6 +28,9 @@ select HAVE_INTEL_CHIPSET_LOCKDOWN select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select INTEL_HAS_TOP_SWAP + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d14a809..828f1a9 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -59,10 +59,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7dcec50..13ea221 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -172,7 +172,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 3f537c0..92c6384 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -357,7 +357,7 @@ u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; // save and recover RTC port values u8 tmp70, tmp72; diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index aed1999..f094ed8 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -85,11 +85,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - - /* D31:F0 LPC bridge */ #define D31F0_PMBASE 0x40 #define D31F0_ACPI_CNTL 0x44 diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index a69b879..05fbcdc 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -170,7 +170,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* BIOS must program... */ diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 4308e29..4b523b7 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -29,6 +29,9 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select COMMON_FADT select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE if SOUTHBRIDGE_INTEL_I82801JX diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 3c09746..4813dd8 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -76,11 +76,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - - /* D31:F0 LPC bridge */ #define D31F0_PMBASE 0x40 #define PMBASE D31F0_PMBASE diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index ba79e73..250ce08 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -172,7 +172,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* BIOS must program... */ diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index fe6526d..796e165 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -37,6 +37,9 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select SOUTHBRIDGE_INTEL_COMMON_GPIO select HAVE_INTEL_CHIPSET_LOCKDOWN + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index e5cbc59..a6d1435 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -174,7 +174,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 55478b9..3938662 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -86,10 +86,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index b70273c..125b90a 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -403,7 +403,7 @@ u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; // save and recover RTC port values u8 tmp70, tmp72; diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5b06c4b..92582e5 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -37,6 +37,9 @@ select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select HAVE_INTEL_CHIPSET_LOCKDOWN select COMMON_FADT + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE config INTEL_LYNXPOINT_LP bool diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index ca850c0..181a982 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -189,7 +189,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info; u16 pmbase = get_pmbase(); - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index a02be81..36ef704 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -210,10 +210,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 87848c2..21da3ab 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -107,7 +107,7 @@ u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; u16 pmbase = get_pmbase(); // save and recover RTC port values diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index 338357e..08f213c 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -2,6 +2,8 @@ bool select HAVE_USBDEBUG select IOAPIC + select HAVE_POWER_STATE_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE if SOUTHBRIDGE_NVIDIA_CK804 diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 2c7519b..fe915ee 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -47,10 +47,6 @@ #define SLOW_CPU_OFF 0 #define SLOW_CPU__ON 1 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - static void lpc_common_init(struct device *dev) { u32 dword; @@ -114,7 +110,7 @@ printk(BIOS_INFO, "%s: pm_base = %x\n", __func__, pm_base); /* Power after power fail */ - on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x45; diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index bb1b7df..66dbc99 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -2,6 +2,8 @@ bool select HAVE_USBDEBUG select IOAPIC + select HAVE_POWER_STATE_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE if SOUTHBRIDGE_NVIDIA_MCP55 diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 3ac6464..7e0fc89 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -48,10 +48,6 @@ #define SLOW_CPU_OFF 0 #define SLOW_CPU__ON 1 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - static void lpc_common_init(struct device *dev, int master) { u8 byte; @@ -93,7 +89,7 @@ /* power after power fail */ #if 1 - on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; diff --git a/src/superio/nuvoton/nct5572d/Kconfig b/src/superio/nuvoton/nct5572d/Kconfig index b666174..0a29f97 100644 --- a/src/superio/nuvoton/nct5572d/Kconfig +++ b/src/superio/nuvoton/nct5572d/Kconfig @@ -16,3 +16,6 @@ config SUPERIO_NUVOTON_NCT5572D bool select SUPERIO_NUVOTON_COMMON_ROMSTAGE + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index 10542d5..2026704 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -28,12 +28,9 @@ #include "nct5572d.h" -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 static void nct5572d_init(struct device *dev) { @@ -68,16 +65,16 @@ break; case NCT5572D_ACPI: /* Set power state after power fail */ - power_status = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + power_status = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&power_status, "power_on_after_fail"); pnp_enter_conf_mode_8787(dev); pnp_set_logical_device(dev); byte = pnp_read_config(dev, 0xe4); byte &= ~0x60; - if (power_status == 1) - byte |= (0x1 << 5); /* Force power on */ - else if (power_status == 2) - byte |= (0x2 << 5); /* Use last power state */ + if (power_status == MAINBOARD_POWER_ON) + byte |= (0x1 << 5); + else if (power_status == MAINBOARD_POWER_KEEP) + byte |= (0x2 << 5); pnp_write_config(dev, 0xe4, byte); pnp_exit_conf_mode_aa(dev); printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off"); diff --git a/src/superio/winbond/w83667hg-a/Kconfig b/src/superio/winbond/w83667hg-a/Kconfig index 74b78c2..6274947 100644 --- a/src/superio/winbond/w83667hg-a/Kconfig +++ b/src/superio/winbond/w83667hg-a/Kconfig @@ -17,3 +17,6 @@ config SUPERIO_WINBOND_W83667HG_A bool select SUPERIO_WINBOND_COMMON_ROMSTAGE + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index ceb783d..eabbd67 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -28,12 +28,9 @@ #include "w83667hg-a.h" -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 static void w83667hg_a_init(struct device *dev) { @@ -68,16 +65,16 @@ break; case W83667HG_A_ACPI: /* Set power state after power fail */ - power_status = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + power_status = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&power_status, "power_on_after_fail"); pnp_enter_conf_mode_8787(dev); pnp_set_logical_device(dev); byte = pnp_read_config(dev, 0xe4); byte &= ~0x60; - if (power_status == 1) - byte |= (0x1 << 5); /* Force power on */ - else if (power_status == 2) - byte |= (0x2 << 5); /* Use last power state */ + if (power_status == MAINBOARD_POWER_ON) + byte |= (0x1 << 5); + else if (power_status == MAINBOARD_POWER_KEEP) + byte |= (0x2 << 5); pnp_write_config(dev, 0xe4, byte); pnp_exit_conf_mode_aa(dev); printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off"); -- To view, visit https://review.coreboot.org/29680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0 Gerrit-Change-Number: 29680 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: soc/intel/.../Kconfig: Drop SOC_INTEL_COMMON_BLOCK_I2C_DEBUG
by Nico Huber (Code Review) 17 Nov '18

17 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29679 Change subject: soc/intel/.../Kconfig: Drop SOC_INTEL_COMMON_BLOCK_I2C_DEBUG ...................................................................... soc/intel/.../Kconfig: Drop SOC_INTEL_COMMON_BLOCK_I2C_DEBUG It's dead. Change-Id: I1fc051937a36878eab23f6022bc42028d5606c83 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/common/block/i2c/Kconfig 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/29679/1 diff --git a/src/soc/intel/common/block/i2c/Kconfig b/src/soc/intel/common/block/i2c/Kconfig index e70796a..b0deb084 100644 --- a/src/soc/intel/common/block/i2c/Kconfig +++ b/src/soc/intel/common/block/i2c/Kconfig @@ -3,11 +3,3 @@ select DRIVERS_I2C_DESIGNWARE help Intel Processor Common I2C support - -config SOC_INTEL_COMMON_BLOCK_I2C_DEBUG - bool "Enable debug output for LPSS I2C transactions" - default n - depends on SOC_INTEL_COMMON_BLOCK_I2C - help - Enable debug output for I2C transactions. This can be useful - when debugging I2C drivers. -- To view, visit https://review.coreboot.org/29679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1fc051937a36878eab23f6022bc42028d5606c83 Gerrit-Change-Number: 29679 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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coreboot-gerrit November 2018