coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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1699 discussions

Change in coreboot[master]: mb/intel/icelake_rvp: Enable dptf functionality
by Sumeet R Pawnikar (Code Review) 19 Nov '18

19 Nov '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/29686 Change subject: mb/intel/icelake_rvp: Enable dptf functionality ...................................................................... mb/intel/icelake_rvp: Enable dptf functionality Enable dptf functionality for IceLake based U and Y systems. Change-Id: I8ef396f9df8e39300d5870fd9a147ecdd6f0ba90 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/29686/1 diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index fb39b60..9e6e350 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -64,6 +64,9 @@ # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index b3a7826..98261c9 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -64,6 +64,9 @@ # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" -- To view, visit https://review.coreboot.org/29686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8ef396f9df8e39300d5870fd9a147ecdd6f0ba90 Gerrit-Change-Number: 29686 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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Change in coreboot[master]: nb/intel/sandybridge/acpi: Add RMRR entry for iGPU
by Nico Huber (Code Review) 19 Nov '18

19 Nov '18

Hello Angel Pons, Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29668 to look at the new patch set (#7). Change subject: nb/intel/sandybridge/acpi: Add RMRR entry for iGPU ...................................................................... nb/intel/sandybridge/acpi: Add RMRR entry for iGPU The iGPU always needs access to its stolen memory. For proper IOMMU support, we have to make the OS aware of that. Directly below TOLUD lies the data stolen memory (BDSM) followed by the GTT stolen memory (BGSM), the iGPU needs access to both. Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/intel/sandybridge/acpi.c 1 file changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/29668/7 -- To view, visit https://review.coreboot.org/29668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d Gerrit-Change-Number: 29668 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: tss: implement tlcl_save_state for running TPM_Shutdown(ST_STATE)
by Philipp Deppenwiese (Code Review) 19 Nov '18

19 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29646 ) Change subject: tss: implement tlcl_save_state for running TPM_Shutdown(ST_STATE) ...................................................................... Patch Set 4: Code-Review-1 If this is an API call for both TSS 1.2 and 2.0, please stub them a least. -- To view, visit https://review.coreboot.org/29646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8b51ca68456fc9b655e4dc2d0958b7c040d50510 Gerrit-Change-Number: 29646 Gerrit-PatchSet: 4 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 09:47:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: LinuxBoot: refactor payload
by Philipp Deppenwiese (Code Review) 19 Nov '18

19 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29581 ) Change subject: LinuxBoot: refactor payload ...................................................................... Patch Set 7: Please test every possible configuration. Looks good for me :) -- To view, visit https://review.coreboot.org/29581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41d0275a5f7efb920e881f43b0acda29f41ee221 Gerrit-Change-Number: 29581 Gerrit-PatchSet: 7 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 09:44:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/sandybridge/acpi: Add RMRR entry for iGPU
by Philipp Deppenwiese (Code Review) 19 Nov '18

19 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29668 ) Change subject: nb/intel/sandybridge/acpi: Add RMRR entry for iGPU ...................................................................... Patch Set 6: Code-Review-1 Remove the submodule change -- To view, visit https://review.coreboot.org/29668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d Gerrit-Change-Number: 29668 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 09:41:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/nvidia: Add PCI mapped option rom driver
by Philipp Deppenwiese (Code Review) 19 Nov '18

19 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29676 ) Change subject: drivers/nvidia: Add PCI mapped option rom driver ...................................................................... Patch Set 2: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/29676/2/src/mainboard/lenovo/t430/Kconfig File src/mainboard/lenovo/t430/Kconfig: https://review.coreboot.org/#/c/29676/2/src/mainboard/lenovo/t430/Kconfig@30 PS2, Line 30: one newline too much -- To view, visit https://review.coreboot.org/29676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idd85ed1fe9b5ffe4c9b7944d5360a2898dbb07f8 Gerrit-Change-Number: 29676 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 09:36:10 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: Documentation: Add W530 / T530
by Philipp Deppenwiese (Code Review) 19 Nov '18

19 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29685 ) Change subject: Documentation: Add W530 / T530 ...................................................................... Documentation: Add W530 / T530 Change-Id: Ib253308737f8c7a497c6ca13eab88220b1ac27ad Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/29685 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/w530-1.jpg A Documentation/mainboard/lenovo/w530-2.jpg A Documentation/mainboard/lenovo/w530.md 4 files changed, 29 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Philipp Deppenwiese: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 5df4885..15c2ede 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -52,6 +52,8 @@ ### Ivy Bridge series - [T430](lenovo/t430.md) +- [T530](lenovo/w530.md) +- [W530](lenovo/w530.md) - [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md) ## SiFive diff --git a/Documentation/mainboard/lenovo/w530-1.jpg b/Documentation/mainboard/lenovo/w530-1.jpg new file mode 100644 index 0000000..32827a0 --- /dev/null +++ b/Documentation/mainboard/lenovo/w530-1.jpg Binary files differ diff --git a/Documentation/mainboard/lenovo/w530-2.jpg b/Documentation/mainboard/lenovo/w530-2.jpg new file mode 100644 index 0000000..dd129b9 --- /dev/null +++ b/Documentation/mainboard/lenovo/w530-2.jpg Binary files differ diff --git a/Documentation/mainboard/lenovo/w530.md b/Documentation/mainboard/lenovo/w530.md new file mode 100644 index 0000000..f91d9ce --- /dev/null +++ b/Documentation/mainboard/lenovo/w530.md @@ -0,0 +1,27 @@ +# Lenovo W530 / T530 + +## Flashing instructions +You have to remove the keyboard and the palm rest to access one of the +flash ICs. The second flash ICs is behind the case frame, but can be +flashed by using a simple trick. Connect every pin of the first flash +IC, but tie /CS to Vcc. Connect /CS of the second flash IC to the +programmer. +As all lines except /CS are shared between the flash ICs you can access +both with an external programmer. + +For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and +```eval_rst +:doc:`../../flash_tutorial/ext_power` +``` + +### After removing the keyboard and palm rest +![][w530-1] + +[w530-1]: w530-1.jpg + +### Closeup view of the flash ICs +![][w530-2] + +[w530-2]: w530-2.jpg + +[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md -- To view, visit https://review.coreboot.org/29685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ib253308737f8c7a497c6ca13eab88220b1ac27ad Gerrit-Change-Number: 29685 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marcello Sylvester Bauer <marcello.bauer(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Evgeny Zinoviev <me(a)ch1p.com>

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Change in coreboot[master]: Documentation: Add W530 / T530
by Philipp Deppenwiese (Code Review) 19 Nov '18

19 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29685 ) Change subject: Documentation: Add W530 / T530 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib253308737f8c7a497c6ca13eab88220b1ac27ad Gerrit-Change-Number: 29685 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marcello Sylvester Bauer <marcello.bauer(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Comment-Date: Mon, 19 Nov 2018 09:34:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/braswell: Disable OS use of HPET
by Michał Żygowski (Code Review) 19 Nov '18

19 Nov '18

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/29655 ) Change subject: soc/intel/braswell: Disable OS use of HPET ...................................................................... Patch Set 3: I experience the bug with 4.14.+ kernels. Payload SeaBIOS. -- To view, visit https://review.coreboot.org/29655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie9a78dcc736eb057c040a0a303c812adb1f76f3c Gerrit-Change-Number: 29655 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 09:18:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src: Add required space after "switch"
by Patrick Georgi (Code Review) 19 Nov '18

19 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29623 ) Change subject: src: Add required space after "switch" ...................................................................... src: Add required space after "switch" Change-Id: I85cf93e30606bc7838852bd300a369e79370629a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/29623 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/arch/riscv/trap_handler.c M src/cpu/via/nano/update_ucode.c M src/device/device_util.c M src/drivers/aspeed/common/ast_main.c M src/drivers/xgi/common/xgi_coreboot.c M src/mainboard/amd/inagua/BiosCallOuts.c M src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c M src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c M src/mainboard/amd/serengeti_cheetah_fam10/mptable.c M src/mainboard/amd/torpedo/BiosCallOuts.c M src/mainboard/apple/macbook21/smihandler.c M src/mainboard/google/link/i915.c M src/mainboard/google/link/mainboard.c M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/lenovo/t60/smihandler.c M src/mainboard/lenovo/x60/smihandler.c M src/mainboard/lenovo/z61t/smihandler.c M src/northbridge/amd/agesa/family14/amdfam14_conf.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/amdht/h3ncmn.c M src/northbridge/amd/amdht/ht_wrapper.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/superio.c M src/superio/fintek/f71872/superio.c M src/superio/fintek/f81216h/early_serial.c M src/superio/fintek/f81216h/superio.c M src/superio/ite/it8728f/superio.c M src/superio/nsc/pc87360/superio.c M src/superio/nsc/pc87366/superio.c M src/superio/nsc/pc87382/superio.c M src/superio/nsc/pc87417/superio.c M src/superio/nsc/pc97317/superio.c M src/superio/nuvoton/nct5104d/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/nct6779d/superio.c M src/superio/nuvoton/wpcm450/superio.c M src/superio/smsc/dme1737/superio.c M src/superio/smsc/lpc47b272/superio.c M src/superio/smsc/lpc47b397/superio.c M src/superio/smsc/lpc47m10x/superio.c M src/superio/smsc/lpc47m15x/superio.c M src/superio/smsc/lpc47n217/early_serial.c M src/superio/smsc/lpc47n217/superio.c M src/superio/smsc/mec1308/superio.c M src/superio/smsc/sch4037/superio.c M src/superio/winbond/w83627dhg/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83627thg/superio.c M src/superio/winbond/w83627uhg/superio.c M src/superio/winbond/w83667hg-a/superio.c M src/superio/winbond/w83977tf/superio.c 55 files changed, 67 insertions(+), 67 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 73c5278..e072bf7 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -125,7 +125,7 @@ return; } - switch(tf->cause) { + switch (tf->cause) { case CAUSE_MISALIGNED_FETCH: case CAUSE_FETCH_ACCESS: case CAUSE_ILLEGAL_INSTRUCTION: diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index cb7d1e0..0ccddc7 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -73,7 +73,7 @@ static void nano_print_ucode_status(ucode_update_status stat) { - switch(stat) + switch (stat) { case UCODE_UPDATE_SUCCESS: printk(BIOS_INFO, "Microcode update successful.\n"); diff --git a/src/device/device_util.c b/src/device/device_util.c index 2a26a55..38207eb 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -168,7 +168,7 @@ if (!dev) { memcpy(buffer, "<null>", 7); } else { - switch(dev->path.type) { + switch (dev->path.type) { case DEVICE_PATH_NONE: memcpy(buffer, "NONE", 5); break; diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index 264ef9d..3a0cf20 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -195,7 +195,7 @@ } /* Print stuff for diagnostic purposes */ - switch(ast->tx_chip_type) { + switch (ast->tx_chip_type) { case AST_TX_SIL164: DRM_INFO("Using Sil164 TMDS transmitter\n"); break; diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index 47320fd..d2acb60 100644 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -379,7 +379,7 @@ xgi_fb.reserved_mask_pos = 0; xgi_fb.reserved_mask_size = 0; - switch(xgifb_info->video_bpp){ + switch (xgifb_info->video_bpp) { case 32: case 24: /* packed into 4-byte words */ diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index c995cff..b6267a6 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -91,7 +91,7 @@ TempData8 |= Data8; Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - switch(MemData->ParameterListPtr->DDR3Voltage){ + switch (MemData->ParameterListPtr->DDR3Voltage) { case VOLT1_35: Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); Data8 &= ~(UINT8)BIT6; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index 9f273a4..03b849d 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -150,7 +150,7 @@ current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); /* pci0 and pci1 are in dsdt */ ssdtx = (acpi_header_t *)current; - switch(sysconf.hcid[i]) { + switch (sysconf.hcid[i]) { case 1: file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; break; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index adf43c0..4e84fb2 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -151,7 +151,7 @@ /* check hcid type here */ sysconf.hcid[i] = get_hcid(i); - switch(sysconf.hcid[i]) { + switch (sysconf.hcid[i]) { case 1: /* 8132 */ case 3: /* 8131 */ diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index d9596da..fb9473f 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -70,7 +70,7 @@ if (!(sysconf.pci1234[i] & 0x1)) continue; - switch(sysconf.hcid[i]) { + switch (sysconf.hcid[i]) { case 1: case 3: dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); @@ -137,7 +137,7 @@ int jj; struct device *dev; struct resource *res; - switch(sysconf.hcid[i]) { + switch (sysconf.hcid[i]) { case 1: case 3: dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index 56c48c8..e7b0e29 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -63,7 +63,7 @@ AcpiMmioAddr = (UINT32)Data16 << 16; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch(MemData->ParameterListPtr->DDR3Voltage){ + switch (MemData->ParameterListPtr->DDR3Voltage) { case VOLT1_35: Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); Data8 &= ~(UINT8)BIT6; diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c index 93920f2..ab33801 100644 --- a/src/mainboard/apple/macbook21/smihandler.c +++ b/src/mainboard/apple/macbook21/smihandler.c @@ -49,7 +49,7 @@ int mainboard_smi_apmc(u8 data) { - switch(data) { + switch (data) { case APM_CNT_ACPI_ENABLE: /* route H8SCI to SCI */ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index 8bd758b..e09785d 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -161,7 +161,7 @@ return index; /* state machine! */ for(i = index, id = &iodefs[i]; id->op; i++, id++){ - switch(id->op){ + switch (id->op) { case M: if (verbose & vmsg) printk(BIOS_SPEW, "%ld: %s\n", globalmicroseconds(), id->msg); @@ -193,7 +193,7 @@ if (id->addr == PCH_PP_CONTROL){ if (verbose & vio) printk(BIOS_SPEW, "PCH_PP_CONTROL\n"); - switch(id->data & 0xf){ + switch (id->data & 0xf) { case 8: break; case 7: break; default: udelay(100000); diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 367e288..4919e6b 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -58,7 +58,7 @@ printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", __func__, X86_AX); - switch(X86_AX) { + switch (X86_AX) { case 0x5f34: /* * Set Panel Fitting Hook: diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 3a37290..37f0240 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -39,7 +39,7 @@ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", __func__, X86_AX, X86_BX, X86_CX, X86_DX); - switch(X86_EAX & 0xffff) { + switch (X86_EAX & 0xffff) { case 0x5f34: /* * Set Panel Fitting Hook: diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index bccb7f1..4e6a68d 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -119,7 +119,7 @@ event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - switch(event) { + switch (event) { /* brightness up */ case 0x14: mainboard_smi_brightness_up(); @@ -153,7 +153,7 @@ int mainboard_smi_apmc(u8 data) { - switch(data) { + switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index c66474d..6d95ee1 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -121,7 +121,7 @@ event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - switch(event) { + switch (event) { /* brightness up */ case 0x14: mainboard_smi_brightness_up(); @@ -158,7 +158,7 @@ int mainboard_smi_apmc(u8 data) { - switch(data) { + switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); diff --git a/src/mainboard/lenovo/z61t/smihandler.c b/src/mainboard/lenovo/z61t/smihandler.c index b93f48e..253ab44 100644 --- a/src/mainboard/lenovo/z61t/smihandler.c +++ b/src/mainboard/lenovo/z61t/smihandler.c @@ -121,7 +121,7 @@ event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - switch(event) { + switch (event) { /* brightness up */ case 0x14: mainboard_smi_brightness_up(); @@ -155,7 +155,7 @@ int mainboard_smi_apmc(u8 data) { - switch(data) { + switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index f78e3f5..0eabaa8 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -126,7 +126,7 @@ { u32 new_vendev = vendev; - switch(vendev) { + switch (vendev) { case 0x10029809: case 0x10029808: case 0x10029807: diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 0361a77..ae0830c 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -964,7 +964,7 @@ { u32 new_vendev = vendev; - switch(vendev) { + switch (vendev) { case 0x10029900: /* AMD Radeon HD 7660G (Trinity) */ case 0x10029901: /* AMD Radeon HD 7660D (Trinity) */ case 0x10029903: /* AMD Radeon HD 7640G (Trinity) */ diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index b3b0ba1..03db042 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -989,7 +989,7 @@ { u32 new_vendev = vendev; - switch(vendev) { + switch (vendev) { case 0x10029830: case 0x10029831: case 0x10029832: diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 6173f17..abb7458 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -1252,7 +1252,7 @@ ******************************************************************************/ static u8 convertBitsToWidth(u8 value, cNorthBridge *nb) { - switch(value) { + switch (value) { case 1: return 16; case 0: return 8; case 5: return 4; diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 05b8d12..d005223 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -132,7 +132,7 @@ } printk(log_level, ": "); - switch(event) { + switch (event) { case HT_EVENT_COH_EVENTS: case HT_EVENT_COH_NO_TOPOLOGY: case HT_EVENT_COH_LINK_EXCEED: diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 4e5c0ce..32fa0d9 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -820,7 +820,7 @@ FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { const struct dll_setting *setting; - switch(s->selected_timings.mem_clk) { + switch (s->selected_timings.mem_clk) { default: /* Should not happen */ case MEM_CLOCK_667MHz: setting = default_ddr2_667_ctrl; diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index eed9d8b..2a60158 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -101,7 +101,7 @@ if (src_dimm->Status != DIMM_PRESENT) continue; - switch(memory_info_hob->MemoryType) { + switch (memory_info_hob->MemoryType) { case MRC_DDR_TYPE_DDR4: ddr_type = MEMORY_TYPE_DDR4; break; diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index a19b1d0..1b37bf2 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -29,7 +29,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F71863FG_KBC: res0 = find_resource(dev, PNP_IDX_IO0); diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 5625a35..d466a76 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -30,7 +30,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F71869AD_KBC: pc_keyboard_init(NO_AUX_DEVICE); diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index 47ecf3d..8634451 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -28,7 +28,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F71872_KBC: pc_keyboard_init(NO_AUX_DEVICE); diff --git a/src/superio/fintek/f81216h/early_serial.c b/src/superio/fintek/f81216h/early_serial.c index 782a9ea..9e8e48b 100644 --- a/src/superio/fintek/f81216h/early_serial.c +++ b/src/superio/fintek/f81216h/early_serial.c @@ -38,7 +38,7 @@ void f81216h_enable_serial(pnp_devfn_t dev, u16 iobase, mode_key k) { u8 key; - switch(k) { + switch (k) { case MODE_6767: key = 0x67; break; diff --git a/src/superio/fintek/f81216h/superio.c b/src/superio/fintek/f81216h/superio.c index 2791876..e55ec57 100644 --- a/src/superio/fintek/f81216h/superio.c +++ b/src/superio/fintek/f81216h/superio.c @@ -40,7 +40,7 @@ * * See page 17 of data sheet. */ - switch(conf->conf_key_mode) { + switch (conf->conf_key_mode) { case MODE_6767: case MODE_7777: case MODE_8787: @@ -74,7 +74,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case F81216H_SP1: case F81216H_SP2: case F81216H_SP3: diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index f806d35..57b461c 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -33,7 +33,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { /* TODO: Might potentially need code for FDC etc. */ case IT8728F_EC: res = find_resource(dev, PNP_IDX_IO0); diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index 5b590ea..a9eba4b 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -28,7 +28,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case PC87360_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index feaed3b..dbb763d 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -28,7 +28,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case PC87366_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index a5d9a8b..688f08c 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -26,7 +26,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case PC87382_DOCK: break; diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index c8616f6..bf33d69 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -29,7 +29,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case PC87417_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; diff --git a/src/superio/nsc/pc97317/superio.c b/src/superio/nsc/pc97317/superio.c index 3e664d1..9b2cbac 100644 --- a/src/superio/nsc/pc97317/superio.c +++ b/src/superio/nsc/pc97317/superio.c @@ -26,7 +26,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case PC97317_KBCK: pnp_set_logical_device(dev); pnp_set_enable(dev, 0); /* Disable keyboard */ diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index 47687e1..bc9af3b 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -30,7 +30,7 @@ reg26 |= CR26_LOCK_REG; pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26); - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { //SP1 (UARTA) IRQ type selection (1:level,0:edge) is controlled by CR 10, bit 5 case NCT5104D_SP1: reg10 = pnp_read_config(dev, IRQ_TYPE_SEL_CR10); @@ -116,7 +116,7 @@ pnp_enter_conf_mode(dev); - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case NCT5104D_SP1: case NCT5104D_SP2: set_irq_trigger_type(dev, conf->irq_trigger_type != 0); diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index 10542d5..c6d46bf 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -44,7 +44,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case NCT5572D_KBC: /* Enable mouse controller */ diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c index 465ef66..e582496 100644 --- a/src/superio/nuvoton/nct6779d/superio.c +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -32,7 +32,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case NCT6779D_KBC: pc_keyboard_init(NO_AUX_DEVICE); diff --git a/src/superio/nuvoton/wpcm450/superio.c b/src/superio/nuvoton/wpcm450/superio.c index 3a0cc5d..fa7a8a0 100644 --- a/src/superio/nuvoton/wpcm450/superio.c +++ b/src/superio/nuvoton/wpcm450/superio.c @@ -28,7 +28,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case WPCM450_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; diff --git a/src/superio/smsc/dme1737/superio.c b/src/superio/smsc/dme1737/superio.c index 455fd5e..a6f9a12 100644 --- a/src/superio/smsc/dme1737/superio.c +++ b/src/superio/smsc/dme1737/superio.c @@ -32,7 +32,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case DME1737_KBC: pc_keyboard_init(NO_AUX_DEVICE); break; diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index 3f8bc2b..2db4fac 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -43,7 +43,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case LPC47B272_KBC: pc_keyboard_init(NO_AUX_DEVICE); break; diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index ab2271a..9e943ea 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -43,7 +43,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case LPC47B397_KBC: pc_keyboard_init(NO_AUX_DEVICE); break; @@ -55,7 +55,7 @@ pnp_enable_resources(dev); pnp_enter_conf_mode(dev); - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case LPC47B397_HWM: printk(BIOS_DEBUG, "LPC47B397 SensorBus register access enabled\n"); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index e71b78f..28aa52c 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -41,7 +41,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case LPC47M10X2_KBC: pc_keyboard_init(NO_AUX_DEVICE); break; diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index 23c1311..9cc6470 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -63,7 +63,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case LPC47M15X_KBC: pc_keyboard_init(NO_AUX_DEVICE); break; diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c index 454d77f..f9ff04e 100644 --- a/src/superio/smsc/lpc47n217/early_serial.c +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -43,7 +43,7 @@ /* LPC47N217 requires base ports to be a multiple of 4. */ ASSERT(!(iobase & 0x3)); - switch(dev & 0xFF) { + switch (dev & 0xFF) { case LPC47N217_PP: pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); break; @@ -74,7 +74,7 @@ { u8 power_register = 0, power_mask = 0, current_power, new_power; - switch(dev & 0xFF) { + switch (dev & 0xFF) { case LPC47N217_PP: power_register = 0x01; power_mask = 0x04; diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index e63645e..0a14e4c 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -163,7 +163,7 @@ { ASSERT(!(iobase & 0x3)); - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case LPC47N217_PP: pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); break; @@ -201,7 +201,7 @@ u8 irq_config_register = 0, irq_config_mask = 0; u8 current_config, new_config; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case LPC47N217_PP: irq_config_register = 0x27; irq_config_mask = 0x0F; @@ -231,7 +231,7 @@ { u8 power_register = 0, power_mask = 0, current_power, new_power; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case LPC47N217_PP: power_register = 0x01; power_mask = 0x04; diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index 5b9f0da..3e6b0bf 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -31,7 +31,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case MEC1308_KBC: pc_keyboard_init(NO_AUX_DEVICE); break; diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index 3f2a1dd..5158b12 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -30,7 +30,7 @@ return; } - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case SCH4037_KBC: pc_keyboard_init(NO_AUX_DEVICE); break; diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 23b73a2..363bcc4 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -38,7 +38,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case W83627DHG_SP2: w83627dhg_enable_UR2(dev); break; diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index db1f98e..04dda6e 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -83,7 +83,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case W83627EHG_KBC: pc_keyboard_init(NO_AUX_DEVICE); break; diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 21c3016..e9cc13b 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -90,7 +90,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case W83627HF_KBC: pc_keyboard_init(NO_AUX_DEVICE); break; @@ -110,7 +110,7 @@ pnp_enable_resources(dev); pnp_enter_conf_mode(dev); - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case W83627HF_HWM: printk(BIOS_DEBUG, "W83627HF HWM SMBus enabled\n"); enable_hwm_smbus(dev); diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c index 03afe11..d741a70 100644 --- a/src/superio/winbond/w83627thg/superio.c +++ b/src/superio/winbond/w83627thg/superio.c @@ -30,7 +30,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case W83627THG_KBC: pc_keyboard_init(NO_AUX_DEVICE); break; diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index d86560f..4c7a7ad 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -58,7 +58,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case W83627UHG_SP1: set_uart_clock_source(dev, 0); break; diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index ceb783d..09859cf 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -44,7 +44,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case W83667HG_A_KBC: /* Enable mouse controller */ diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index 9b78b84..40df5b3 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -31,7 +31,7 @@ if (!dev->enabled) return; - switch(dev->path.pnp.device) { + switch (dev->path.pnp.device) { case W83977TF_KBC: pc_keyboard_init(NO_AUX_DEVICE); break; -- To view, visit https://review.coreboot.org/29623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I85cf93e30606bc7838852bd300a369e79370629a Gerrit-Change-Number: 29623 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit November 2018