coreboot-gerrit November 2018

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Change in coreboot[master]: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 19 Nov '18

19 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29662 to look at the new patch set (#5). Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support No working C_ENVIRONMENT_BOOTBLOCK support is available. Enable support and add required files for the Braswell Bootblock in C. BUG=NA TEST=Portwell PQ7-M107 Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/car.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc A src/soc/intel/braswell/bootblock/bootblock_c.c A src/soc/intel/braswell/bootblock/cache_as_ram_cbootblock.S M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/car_stage_entry.S 7 files changed, 320 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29662/5 -- To view, visit https://review.coreboot.org/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: google/kukui: Enable cr50 over SPI
by You-Cheng Syu (Code Review) 19 Nov '18

19 Nov '18

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/29689 Change subject: google/kukui: Enable cr50 over SPI ...................................................................... google/kukui: Enable cr50 over SPI WIP BUG=b:117916698 TEST=gsctool -s -f Change-Id: I46f730f7e02160c361bfc7f7a4e910b24349c5b7 --- M src/mainboard/google/kukui/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/29689/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 7032d67..f49e135 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -9,6 +9,8 @@ select SOC_MEDIATEK_MT8183 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + #select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_TPM2 select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH select FATAL_ASSERTS @@ -24,6 +26,10 @@ string default "Kukui" +config DRIVER_TPM_SPI_BUS + hex + default 0x0 + config BOOT_DEVICE_SPI_FLASH_BUS int default 1 -- To view, visit https://review.coreboot.org/29689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I46f730f7e02160c361bfc7f7a4e910b24349c5b7 Gerrit-Change-Number: 29689 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com>

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Change in coreboot[master]: northbridge/intel/fsp_*: Remove legacy SoCs
by Philipp Deppenwiese (Code Review) 19 Nov '18

19 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29402 ) Change subject: northbridge/intel/fsp_*: Remove legacy SoCs ...................................................................... Patch Set 5: Done -- To view, visit https://review.coreboot.org/29402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e Gerrit-Change-Number: 29402 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: David Guckian (1002172) Gerrit-Comment-Date: Mon, 19 Nov 2018 12:43:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/gm45/northbridge.c: Check for NULL pointers
by Arthur Heymans (Code Review) 19 Nov '18

19 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/29688 Change subject: nb/intel/gm45/northbridge.c: Check for NULL pointers ...................................................................... nb/intel/gm45/northbridge.c: Check for NULL pointers Change-Id: Ic12a8c145d6348086f9931af93ce6d3b3dcb9039 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/northbridge.c 1 file changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/29688/1 diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index a738905..0fd7fe5 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -228,14 +228,23 @@ u32 northbridge_get_tseg_size(void) { - const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), - D0F0_ESMRAMC); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + + if (dev == NULL) + die("could not find pci 00:00.0!\n"); + + const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC); return decode_tseg_size(esmramc) << 10; } void northbridge_write_smram(u8 smram) { - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_SMRAM, smram); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + + if (dev == NULL) + die("could not find pci 00:00.0!\n"); + + pci_write_config8(dev, D0F0_SMRAM, smram); } /* -- To view, visit https://review.coreboot.org/29688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic12a8c145d6348086f9931af93ce6d3b3dcb9039 Gerrit-Change-Number: 29688 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 19 Nov '18

19 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29662 to look at the new patch set (#4). Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support No working C_ENVIRONMENT_BOOTBLOCK support is available. Enable support and add required files for the Braswell Bootblock in C. BUG=NA TEST=Portwell PQ7-M107 Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc A src/soc/intel/braswell/bootblock/bootblock_c.c A src/soc/intel/braswell/bootblock/cache_as_ram_cbootblock.S M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/car_stage_entry.S M src/soc/intel/skylake/romstage/car_stage.S 9 files changed, 325 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29662/4 -- To view, visit https://review.coreboot.org/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S
by Frans Hendriks (Code Review) 19 Nov '18

19 Nov '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29687 Change subject: drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S ...................................................................... drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S soc/car_setup.S is included when SKIP_FSP_CAR is enabled, but no chipset/SoC have car_setup.S available. Remove include and post_code() call always solving build errors. BUG=NA TEST=NA Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/cache_as_ram.inc 1 file changed, 0 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/29687/1 diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index af6f3a9..934ae67 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -37,19 +37,6 @@ cache_as_ram: post_code(0x20) -#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) - - /* - * SOC specific setup - * NOTE: This has to preserve the registers - * mm0, mm1 and edi. - */ - #include <soc/car_setup.S> - - post_code(0x28) - -#endif - /* * Find the FSP binary in cbfs. * Make a fake stack that has the return value back to this code. -- To view, visit https://review.coreboot.org/29687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61 Gerrit-Change-Number: 29687 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 19 Nov '18

19 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29662 to look at the new patch set (#3). Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support No working C_ENVIRONMENT_BOOTBLOCK support is available. Enable support and add required files for the Braswell Bootblock in C. BUG=NA TEST=Portwell PQ7-M107 Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/Makefile.inc A src/drivers/intel/fsp1_1/cache_as_ram_cbootblock.S M src/drivers/intel/fsp1_1/car.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc A src/soc/intel/braswell/bootblock/bootblock_c.c M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/car_stage_entry.S M src/soc/intel/skylake/romstage/car_stage.S 9 files changed, 318 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29662/3 -- To view, visit https://review.coreboot.org/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: soc/intel/braswell: Disable OS use of HPET
by Michał Żygowski (Code Review) 19 Nov '18

19 Nov '18

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/29655 ) Change subject: soc/intel/braswell: Disable OS use of HPET ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/29655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie9a78dcc736eb057c040a0a303c812adb1f76f3c Gerrit-Change-Number: 29655 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 10:02:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/braswell: Disable OS use of HPET
by Patrick Georgi (Code Review) 19 Nov '18

19 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/29655 ) Change subject: soc/intel/braswell: Disable OS use of HPET ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/29655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie9a78dcc736eb057c040a0a303c812adb1f76f3c Gerrit-Change-Number: 29655 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 09:59:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 19 Nov '18

19 Nov '18

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/29662 ) Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29662/2/src/soc/intel/braswell/romstage/car… File src/soc/intel/braswell/romstage/car_stage.S: https://review.coreboot.org/#/c/29662/2/src/soc/intel/braswell/romstage/car… PS2, Line 23: call romstage_c_entry > please replace romstage_c_entry with car_stage_entry of all affected mainboards and get rid of this […] I agree that might change filename into car_stage_entry.S, but don't understand your comment: 1. This entry point is called from arch/x86/assembly_entry.S. It will call romstage_c_entry() to continue in romstage. For sure car_stage_entry() can be created in mainboard, but this function will be call to romstage_c_entry() or copy of romstage_c_entry(). Why not generate common support? 2. Or do you call car_stage_c_entry() and replace the romstage_c_entry function with car_stage_c_entry 3. This is same support a skylake (fsp 1.1) implementation. -- To view, visit https://review.coreboot.org/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 09:58:08 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit November 2018