coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/drivers/intel/fsp1_1: Report returned status of FspTempRamInit() ...
by Frans Hendriks (Code Review) 20 Nov '18

20 Nov '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29695 Change subject: soc/drivers/intel/fsp1_1: Report returned status of FspTempRamInit() always. ...................................................................... soc/drivers/intel/fsp1_1: Report returned status of FspTempRamInit() always. Returned status code FspTempRamInit() is not displayed when error occurs. Move the printk() call before the check for status. BUG=NA TEST=Portwell PQ7-M107 Change-Id: Id87e5c765d09f4ab199db9eba07a949b031a709a Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/bootblock.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/29695/1 diff --git a/src/drivers/intel/fsp1_1/bootblock.c b/src/drivers/intel/fsp1_1/bootblock.c index cf9e134..ce367f7 100644 --- a/src/drivers/intel/fsp1_1/bootblock.c +++ b/src/drivers/intel/fsp1_1/bootblock.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corporation. + * Copryight (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -51,8 +52,8 @@ fsp_temp_ram_init = (FSP_TEMP_RAM_INIT)(fih->ImageBase + fih->TempRamInitEntryOffset); status = fsp_temp_ram_init(&temp_ram_init_params); + printk(BIOS_DEBUG, "FspTempRamInit returned 0x%08x\n", status); if (status != FSP_SUCCESS) die("FspTempRamInit failed. Giving up."); - printk(BIOS_DEBUG, "FspTempRamInit returned 0x%08x\n", status); } -- To view, visit https://review.coreboot.org/29695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id87e5c765d09f4ab199db9eba07a949b031a709a Gerrit-Change-Number: 29695 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: drivers/uart/Kconfig: Be smarter about DRIVERS_UART_8250IO
by Julius Werner (Code Review) 20 Nov '18

20 Nov '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/29571 ) Change subject: drivers/uart/Kconfig: Be smarter about DRIVERS_UART_8250IO ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/29571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e755fe0e4f6d1c31ef2854603a5510c3cdc4967 Gerrit-Change-Number: 29571 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Nov 2018 07:05:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: (console, drivers/uart)/Kconfig: Fix dependencies
by Julius Werner (Code Review) 20 Nov '18

20 Nov '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/29572 ) Change subject: (console,drivers/uart)/Kconfig: Fix dependencies ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/29572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Gerrit-Change-Number: 29572 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Nov 2018 07:04:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/intel/cannonlake_rvp: Enable dptf functionality
by Sumeet R Pawnikar (Code Review) 20 Nov '18

20 Nov '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/29693 Change subject: mb/intel/cannonlake_rvp: Enable dptf functionality ...................................................................... mb/intel/cannonlake_rvp: Enable dptf functionality Enable dptf functionality for CannonLake based U and Y systems. Change-Id: I9393384b64322cb91a339964366388a176ce80a9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/29693/1 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index bb963c9..32b33f4 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -63,6 +63,9 @@ # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 55afde2..ec0ce24 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -63,6 +63,9 @@ # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" -- To view, visit https://review.coreboot.org/29693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9393384b64322cb91a339964366388a176ce80a9 Gerrit-Change-Number: 29693 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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Change in coreboot[master]: mb/google/octopus/variants/fleex: Update TSR1 and TSR2 PSV threshold ...
by John Su (Code Review) 20 Nov '18

20 Nov '18

John Su has uploaded this change for review. ( https://review.coreboot.org/29692 Change subject: mb/google/octopus/variants/fleex: Update TSR1 and TSR2 PSV threshold settings ...................................................................... mb/google/octopus/variants/fleex: Update TSR1 and TSR2 PSV threshold settings Update dptf: TSR1 PSV value change from 57 to 59. TSR2 PSV value change from 53 to 55. The target score for WebGL Aquarium is 50 FPS after 5 minute for 1000 fishes. Refer to b:112448519#comment53. BUG=b:112448519 TEST=Match the result from DPTF UI Change-Id: Ib050194d273b20f8efd73f89d0a6a1fa52b89bc8 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/29692/1 diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl index d5943c7..75e5e90 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl @@ -18,12 +18,12 @@ #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Ambient" -#define DPTF_TSR1_PASSIVE 57 +#define DPTF_TSR1_PASSIVE 59 #define DPTF_TSR1_CRITICAL 127 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Charger" -#define DPTF_TSR2_PASSIVE 53 +#define DPTF_TSR2_PASSIVE 55 #define DPTF_TSR2_CRITICAL 127 /* Charger performance states, board-specific values from charger and EC */ -- To view, visit https://review.coreboot.org/29692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib050194d273b20f8efd73f89d0a6a1fa52b89bc8 Gerrit-Change-Number: 29692 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>

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Change in coreboot[master]: soc/intel/cannonlake: Fix IO decode setup
by Lijian Zhao (Code Review) 20 Nov '18

20 Nov '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/29671 ) Change subject: soc/intel/cannonlake: Fix IO decode setup ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9bd894fea62b78b81e5c80b5e88a539ebddac2df Gerrit-Change-Number: 29671 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Nov 2018 02:30:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/common: Bring DISPLAY_MTRRS into the light
by Julius Werner (Code Review) 19 Nov '18

19 Nov '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/29684 ) Change subject: soc/intel/common: Bring DISPLAY_MTRRS into the light ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29684/2/src/Kconfig File src/Kconfig: https://review.coreboot.org/#/c/29684/2/src/Kconfig@708 PS2, Line 708: depends on HAVE_DISPLAY_MTRRS Should we maybe consider building a better way for arch/soc/mainboard to add options here? This is heavily x86 specific, as are several others already in here... it's going to get pretty full (especially if you need a dummy HAVE_... option for everything as well). In Linux they solve this by having a separate Kconfig.debug file next to the normal Kconfig in every subdirectory that offers debug options. We could do the same. -- To view, visit https://review.coreboot.org/29684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Gerrit-Change-Number: 29684 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 20:37:13 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/cpu/intel/Kconfig: Remove dead source
by Jonathan Neuschäfer (Code Review) 19 Nov '18

19 Nov '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/29690 ) Change subject: src/cpu/intel/Kconfig: Remove dead source ...................................................................... Patch Set 1: Code-Review+2 Thanks -- To view, visit https://review.coreboot.org/29690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If77426fcb9f30f3e8b79d7c134053276701a5ecc Gerrit-Change-Number: 29690 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 20:08:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee/variants/delan: Enable Weida touchscreen device
by Patrick Georgi (Code Review) 19 Nov '18

19 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29656 ) Change subject: mb/google/kahlee/variants/delan: Enable Weida touchscreen device ...................................................................... mb/google/kahlee/variants/delan: Enable Weida touchscreen device This change adds ACPI properties for WDT8752A device. BUG=b:117174180 BRANCH=master TEST=Verify touchscreen on delan works with this change Change-Id: Id1484a482de6282c97f3aac329f217bbcb7dbd18 Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29656 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz(a)google.com> --- M src/mainboard/google/kahlee/variants/delan/devicetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Daniel Kurtz: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/delan/devicetree.cb b/src/mainboard/google/kahlee/variants/delan/devicetree.cb index fd30d5d..b9cfe1b 100644 --- a/src/mainboard/google/kahlee/variants/delan/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/delan/devicetree.cb @@ -170,5 +170,19 @@ register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""WDHT0002"" + register "generic.desc" = ""WDT Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "generic.reset_delay_ms" = "130" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "generic.enable_delay_ms" = "2" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end end end #chip soc/amd/stoneyridge -- To view, visit https://review.coreboot.org/29656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Id1484a482de6282c97f3aac329f217bbcb7dbd18 Gerrit-Change-Number: 29656 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 19 Nov '18

19 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 15: (2 comments) https://review.coreboot.org/#/c/29563/15/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/15/src/include/memlayout.h@168 PS15, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/15/src/include/memlayout.h@168 PS15, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 15 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph (1001864) Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 16:31:56 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit November 2018