coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: soc/intel/common/block/acpi: fix P-States extra entry
by build bot (Jenkins) (Code Review) 20 Nov '18

20 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25429 ) Change subject: soc/intel/common/block/acpi: fix P-States extra entry ...................................................................... Patch Set 8: (3 comments) https://review.coreboot.org/#/c/25429/8/src/soc/intel/common/block/acpi/acp… File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/#/c/25429/8/src/soc/intel/common/block/acpi/acp… PS8, Line 330: if (((ratio_max - ratio_min) % ratio_step) > 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25429/8/src/soc/intel/common/block/acpi/acp… PS8, Line 333: if (turbo) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25429/8/src/soc/intel/common/block/acpi/acp… PS8, Line 336: if (num_entries > PSS_MAX_ENTRIES) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/25429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91090b4d87eb82b57055c24271d679d1cbb3b7a7 Gerrit-Change-Number: 25429 Gerrit-PatchSet: 8 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Nov 2018 13:06:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Move TPM2 NVRAM specific settings
by Philipp Deppenwiese (Code Review) 20 Nov '18

20 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29326 ) Change subject: security/tpm: Move TPM2 NVRAM specific settings ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/29326/5//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29326/5//COMMIT_MSG@9 PS5, Line 9: * Move TPM2 NVRAM default parameters from vboot > why ? Because it can be re-used for defining NVRAM indices -- To view, visit https://review.coreboot.org/c/coreboot/+/29326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec9d1c272ed8d0872c9bbc406e98a19ac7a376bd Gerrit-Change-Number: 29326 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Nov 2018 12:29:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/dram/ddr2: Add TCK_1066MHZ to "normalize_tck" function
by Elyes HAOUAS (Code Review) 20 Nov '18

20 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29726 to look at the new patch set (#2). Change subject: device/dram/ddr2: Add TCK_1066MHZ to "normalize_tck" function ...................................................................... device/dram/ddr2: Add TCK_1066MHZ to "normalize_tck" function Change-Id: Ifdbc645ce5e50850c2ecc6e84835a5cb9659676f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/dram/ddr2.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29726/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdbc645ce5e50850c2ecc6e84835a5cb9659676f Gerrit-Change-Number: 29726 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: device/dram/ddr2: Add TCK_1066MHZ to "normalize_tck" function
by Elyes HAOUAS (Code Review) 20 Nov '18

20 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29726 Change subject: device/dram/ddr2: Add TCK_1066MHZ to "normalize_tck" function ...................................................................... device/dram/ddr2: Add TCK_1066MHZ to "normalize_tck" function Change-Id: Ifdbc645ce5e50850c2ecc6e84835a5cb9659676f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/dram/ddr2.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29726/1 diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 53106f2..309fd88 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -726,7 +726,9 @@ void normalize_tck(u32 *tclk) { - if (*tclk <= TCK_800MHZ) { + if (*tclk <= TCK_1066MHZ { + *tclk = TCK_1066MHZ; + } else if (*tclk <= TCK_800MHZ) { *tclk = TCK_800MHZ; } else if (*tclk <= TCK_666MHZ) { *tclk = TCK_666MHZ; -- To view, visit https://review.coreboot.org/c/coreboot/+/29726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdbc645ce5e50850c2ecc6e84835a5cb9659676f Gerrit-Change-Number: 29726 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: include/spd_ddr2: Remove common SPD byte 2
by Elyes HAOUAS (Code Review) 20 Nov '18

20 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29725 Change subject: include/spd_ddr2: Remove common SPD byte 2 ...................................................................... include/spd_ddr2: Remove common SPD byte 2 Common SPD byte 2 is defined in include/spd.h Change-Id: I29cf4184a32e9e72c1927b8f1f70f099394974af Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/spd_ddr2.h 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/29725/1 diff --git a/src/include/spd_ddr2.h b/src/include/spd_ddr2.h index 724c996..447ba89 100644 --- a/src/include/spd_ddr2.h +++ b/src/include/spd_ddr2.h @@ -18,9 +18,8 @@ #define __SPD_DDR2_H__ /* SPDs for DDR2 SDRAM */ -#define SPD_MEM_TYPE 2 - #define SPD_MEM_TYPE_SDRAM_DDR 0x07 - #define SPD_MEM_TYPE_SDRAM_DDR2 0x08 + +/* SPD Byte [2] memory type, see include/spd.h: spd_memory_type enum */ #define SPD_DIMM_TYPE 20 /* x bit0 or bit4 =1 mean registered*/ #define SPD_DIMM_TYPE_RDIMM 0x01 -- To view, visit https://review.coreboot.org/c/coreboot/+/29725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29cf4184a32e9e72c1927b8f1f70f099394974af Gerrit-Change-Number: 29725 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/icelake: Create macros for FSP consumption as per ICL requi...
by build bot (Jenkins) (Code Review) 20 Nov '18

20 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29697 ) Change subject: soc/intel/icelake: Create macros for FSP consumption as per ICL requirement ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29697/1/src/soc/intel/icelake/include/soc/s… File src/soc/intel/icelake/include/soc/serialio.h: https://review.coreboot.org/#/c/29697/1/src/soc/intel/icelake/include/soc/s… PS1, Line 25: } PCH_SERIAL_IO_MODE; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7e4bc304f93e4b63ac2d7f194ca441dd96dd943 Gerrit-Change-Number: 29697 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Nov 2018 11:43:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: payloads/seabios: Update stable from 1.11.2 to 1.12.0
by Martin Kepplinger (Code Review) 20 Nov '18

20 Nov '18

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29724 Change subject: payloads/seabios: Update stable from 1.11.2 to 1.12.0 ...................................................................... payloads/seabios: Update stable from 1.11.2 to 1.12.0 SeaBIOS 1.12.0 has been tagged. News are * Initial support for "TPM CRB" hardware * Improved cdrom media reporting in the boot menu on QEMU * Improved floppy support on real floppy hardware * SeaVGABIOS support for QEMU "bochs-display" and QEMU "ramfb" displays * Several bug fixes and code cleanups among others, see http://seabios.org/Releases Tested by running it on a Thinkpad X230. Change-Id: I5f8364977ce957d3e8d84d7b046d1cec36b8da6a Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M payloads/external/SeaBIOS/Kconfig M payloads/external/SeaBIOS/Makefile 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/29724/1 diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index fb9f32b..181a9d6 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -5,7 +5,7 @@ default SEABIOS_STABLE config SEABIOS_STABLE - bool "1.11.2" + bool "1.12.0" help Stable SeaBIOS version config SEABIOS_MASTER diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index 4e2ecbd..e505c8c 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=f9626ccb91e771f990fbb2da92e427a399d7d918 +TAG-$(CONFIG_SEABIOS_STABLE)=a698c8995ffb2838296ec284fe3c4ad33dfca307 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) project_git_repo=https://review.coreboot.org/seabios.git -- To view, visit https://review.coreboot.org/c/coreboot/+/29724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f8364977ce957d3e8d84d7b046d1cec36b8da6a Gerrit-Change-Number: 29724 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: device/dram/ddr2: Add TCK_1066MHZ to 'normalize_tck' function
by Elyes HAOUAS (Code Review) 20 Nov '18

20 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29704 Change subject: device/dram/ddr2: Add TCK_1066MHZ to 'normalize_tck' function ...................................................................... device/dram/ddr2: Add TCK_1066MHZ to 'normalize_tck' function Change-Id: Ifdbc645ce5e50850c2ecc6e84835a5cb9659676f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/dram/ddr2.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/29704/1 diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 53106f2..309fd88 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -726,7 +726,9 @@ void normalize_tck(u32 *tclk) { - if (*tclk <= TCK_800MHZ) { + if (*tclk <= TCK_1066MHZ { + *tclk = TCK_1066MHZ; + } else if (*tclk <= TCK_800MHZ) { *tclk = TCK_800MHZ; } else if (*tclk <= TCK_666MHZ) { *tclk = TCK_666MHZ; -- To view, visit https://review.coreboot.org/c/coreboot/+/29704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdbc645ce5e50850c2ecc6e84835a5cb9659676f Gerrit-Change-Number: 29704 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/icelake: Create macros for FSP consumption as per ICL requi...
by Subrata Banik (Code Review) 20 Nov '18

20 Nov '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/29697 Change subject: soc/intel/icelake: Create macros for FSP consumption as per ICL requirement ...................................................................... soc/intel/icelake: Create macros for FSP consumption as per ICL requirement 1. Modify PCIEXBAR to accomodate TCSS RP 2. LPSS device mode selection 3. Add option to emable/disable audio controller. Change-Id: Ib7e4bc304f93e4b63ac2d7f194ca441dd96dd943 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/include/soc/serialio.h 3 files changed, 52 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/29697/1 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index c4ee841..727fccee 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -126,6 +126,10 @@ help This option allows you to select MMIO Base Address of sideband bus. +config MMCONF_BASE_ADDRESS + hex + default 0xc0000000 + config CPU_BCLK_MHZ int default 100 @@ -146,6 +150,10 @@ int default 6 +config SOC_INTEL_UART_DEV_MAX + int + default 3 + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index cb06fcb..6bd836e 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -121,6 +121,7 @@ uint8_t SataPortsDevSlp[8]; /* Audio related */ + uint8_t EnableAzalia; uint8_t PchHdaEnable; uint8_t PchHdaDspEnable; @@ -152,11 +153,16 @@ /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; /* Need to update DLL setting to get Emmc running at HS400 speed */ - uint8_t EmmcHs400DllNeed; - /* 0-39: number of active delay for RX strobe, unit is 125 psec */ - uint8_t EmmcHs400RxStrobeDll1; - /* 0-78: number of active delay for TX data, unit is 125 psec */ - uint8_t EmmcHs400TxDataDll; + uint8_t EmmcUseCustomDlls; + uint32_t EmmcTxCmdDelayRegValue; + uint32_t EmmcTxDataDelay1RegValue; + uint32_t EmmcTxDataDelay2RegValue; + uint32_t EmmcRxCmdDataDelay1RegValue; + uint32_t EmmcRxCmdDataDelay2RegValue; + uint32_t EmmcRxStrobeDelayRegValue; + + /* Enable if SD Card Power Enable Signal is Active High */ + uint8_t SdCardPowerEnableActiveHigh; /* Integrated Sensor */ uint8_t PchIshEnable; @@ -219,28 +225,17 @@ } DebugConsent; /* * SerialIO device mode selection: - * - * Device index: - * PchSerialIoIndexI2C0 - * PchSerialIoIndexI2C1 - * PchSerialIoIndexI2C2 - * PchSerialIoIndexI2C3 - * PchSerialIoIndexI2C4 - * PchSerialIoIndexI2C5 - * PchSerialIoIndexSPI0 - * PchSerialIoIndexSPI1 - * PchSerialIoIndexSPI2 - * PchSerialIoIndexUART0 - * PchSerialIoIndexUART1 - * PchSerialIoIndexUART2 - * - * Mode select: - * PchSerialIoDisabled - * PchSerialIoPci - * PchSerialIoAcpi - * PchSerialIoHidden + * PchSerialIoDisabled, + * PchSerialIoPci, + * PchSerialIoHidden, + * PchSerialIoLegacyUart, + * PchSerialIoSkipInit */ - uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; + uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; @@ -251,6 +246,14 @@ /* Intel VT configuration */ uint8_t VtdDisable; uint8_t VmxEnable; + + /* CNVi BT Audio Offload + Enable/Disable BT Audio Offload. + 0: PLATFORM_POR, + 1: FORCE_ENABLE, + 2: FORCE_DISABLE. + */ + uint8_t CnviBtAudioOffload; }; typedef struct soc_intel_icelake_config config_t; diff --git a/src/soc/intel/icelake/include/soc/serialio.h b/src/soc/intel/icelake/include/soc/serialio.h index 30a48a1..8f18eb8 100644 --- a/src/soc/intel/icelake/include/soc/serialio.h +++ b/src/soc/intel/icelake/include/soc/serialio.h @@ -19,9 +19,10 @@ typedef enum { PchSerialIoDisabled, PchSerialIoPci, - PchSerialIoAcpi, PchSerialIoHidden, -} PCH_SERIAL_IO_MODE; + PchSerialIoLegacyUart, + PchSerialIoSkipInit + } PCH_SERIAL_IO_MODE; typedef enum { PchSerialIoIndexI2C0, @@ -29,14 +30,19 @@ PchSerialIoIndexI2C2, PchSerialIoIndexI2C3, PchSerialIoIndexI2C4, - PchSerialIoIndexI2C5, - PchSerialIoIndexSPI0, - PchSerialIoIndexSPI1, - PchSerialIoIndexSPI2, + PchSerialIoIndexI2C5 +} PCH_SERIAL_IO_I2C_CONTROLLER; + +typedef enum { + PchSerialIoIndexGSPI0, + PchSerialIoIndexGSPI1, + PchSerialIoIndexGSPI2 +} PCH_SERIAL_IO_GSPI_CONTROLLER; + +typedef enum { PchSerialIoIndexUART0, PchSerialIoIndexUART1, - PchSerialIoIndexUART2, - PchSerialIoIndexMAX -} PCH_SERIAL_IO_CONTROLLER; + PchSerialIoIndexUART2 +} PCH_SERIAL_IO_UART_CONTROLLER; #endif -- To view, visit https://review.coreboot.org/29697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib7e4bc304f93e4b63ac2d7f194ca441dd96dd943 Gerrit-Change-Number: 29697 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: util/ifdtool: Add IceLake platform support under IFDv2
by Subrata Banik (Code Review) 20 Nov '18

20 Nov '18

Hello Aamir Bohra, I'd like you to do a code review. Please visit https://review.coreboot.org/29696 to review the following change. Change subject: util/ifdtool: Add IceLake platform support under IFDv2 ...................................................................... util/ifdtool: Add IceLake platform support under IFDv2 Change-Id: Ib69a2cbc3d8ab9f35c940e95b0edb4b04b50b716 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/1162995 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator(a)appspot.gserviceaccount.com> Tested-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Shelley Chen <shchen(a)chromium.org> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/29696/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 671c7d5..ccd27d0 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -214,6 +214,7 @@ static const int ifd_2_platforms[] = { PLATFORM_GLK, PLATFORM_CNL, + PLATFORM_ICL, }; unsigned int i; @@ -1542,6 +1543,8 @@ platform = PLATFORM_CNL; } else if (!strcmp(optarg, "glk")) { platform = PLATFORM_GLK; + } else if (!strcmp(optarg, "icl")) { + platform = PLATFORM_ICL; } else if (!strcmp(optarg, "sklkbl")) { platform = PLATFORM_SKLKBL; } else { diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index aec7c30..49463b9 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -56,6 +56,7 @@ PLATFORM_APL, PLATFORM_CNL, PLATFORM_GLK, + PLATFORM_ICL, PLATFORM_SKLKBL, }; -- To view, visit https://review.coreboot.org/29696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib69a2cbc3d8ab9f35c940e95b0edb4b04b50b716 Gerrit-Change-Number: 29696 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>

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coreboot-gerrit November 2018