coreboot-gerrit November 2018

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Change in coreboot[master]: src/cpu/intel/Kconfig: Remove dead source
by Elyes HAOUAS (Code Review) 19 Nov '18

19 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29690 Change subject: src/cpu/intel/Kconfig: Remove dead source ...................................................................... src/cpu/intel/Kconfig: Remove dead source fsp_model_206ax was removed in Change-Id: I7b6bc4bfd Change-Id: If77426fcb9f30f3e8b79d7c134053276701a5ecc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/29690/1 diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 26b9347..3fad796 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -11,7 +11,6 @@ source src/cpu/intel/model_1067x/Kconfig source src/cpu/intel/model_106cx/Kconfig source src/cpu/intel/model_206ax/Kconfig -source src/cpu/intel/fsp_model_206ax/Kconfig source src/cpu/intel/fsp_model_406dx/Kconfig source src/cpu/intel/model_2065x/Kconfig source src/cpu/intel/model_f2x/Kconfig -- To view, visit https://review.coreboot.org/29690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If77426fcb9f30f3e8b79d7c134053276701a5ecc Gerrit-Change-Number: 29690 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 19 Nov '18

19 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 14: (2 comments) https://review.coreboot.org/#/c/29563/14/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/14/src/include/memlayout.h@168 PS14, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/14/src/include/memlayout.h@168 PS14, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 14 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph (1001864) Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 15:57:29 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: security/tpm: Fix TCPA log feature
by Philipp Deppenwiese (Code Review) 19 Nov '18

19 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 13: (13 comments) https://review.coreboot.org/#/c/29563/13/src/commonlib/include/commonlib/tc… File src/commonlib/include/commonlib/tcpa_log_serialized.h: https://review.coreboot.org/#/c/29563/13/src/commonlib/include/commonlib/tc… PS13, Line 24: 128 > This should be (TCPA_DIGEST_MAX_LENGTH * 2 + 1) Done https://review.coreboot.org/#/c/29563/13/src/commonlib/include/commonlib/tc… PS13, Line 32: char name[TCPA_PCR_HASH_NAME]; > If you are directly exposing this structure how is the tooling supposed to know where the fields end […] TCPA_FORMAT_HASH_LENGTH and TCPA_LOG_STRING_LENGTH are only used from cbmem tool https://review.coreboot.org/#/c/29563/13/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/13/src/security/tpm/tspi/log.c@30 PS13, Line 30: if (!cbmem_possibly_online() && > You should add a comment here about what case you are dealing with. Done https://review.coreboot.org/#/c/29563/13/src/security/tpm/tspi/log.c@43 PS13, Line 43: sizeof(struct tcpa_entry)); > You should memset() to 0 because cbmem is not guarantee to be initialized. Done https://review.coreboot.org/#/c/29563/13/src/security/tpm/tspi/log.c@73 PS13, Line 73: (char *) > hash is already char type. No need to cast. Done https://review.coreboot.org/#/c/29563/13/src/security/tpm/tspi/log.c@74 PS13, Line 74: tce->digest_length, > This length calculation is wrong. You are overwriting the buffer on the last 2 nibbles. Done https://review.coreboot.org/#/c/29563/13/src/security/tpm/tspi/log.c@82 PS13, Line 82: hash > This string is not NUL terminated. It's exactly 2x max hash size. It is not a valid C string. Done https://review.coreboot.org/#/c/29563/13/src/security/tpm/tspi/log.c@102 PS13, Line 102: if (tce) > This would always evaluate to non-NULL unless we were wrapping arithmetic or entries was first field […] Done https://review.coreboot.org/#/c/29563/13/src/security/vboot/Kconfig File src/security/vboot/Kconfig: https://review.coreboot.org/#/c/29563/13/src/security/vboot/Kconfig@258 PS13, Line 258: default y > If it's default y how is anyone supposed to unselect it? If it's driven by VBOOT_MEASURED_BOOT then […] Done https://review.coreboot.org/#/c/29563/13/src/security/vboot/vboot_crtm.c File src/security/vboot/vboot_crtm.c: https://review.coreboot.org/#/c/29563/13/src/security/vboot/vboot_crtm.c@165 PS13, Line 165: tcpa_log_dump() > We can just call this when we're exiting BS_LOAD_PAYLOAD state. […] Done https://review.coreboot.org/#/c/29563/13/src/security/vboot/vboot_crtm.c@170 PS13, Line 170: static void recover_tcpa_log(int is_recovery) > Why isn't this function just in the other file where you handled the rest of the log stuff? It's only needed for measurements in the vboot case https://review.coreboot.org/#/c/29563/13/src/security/vboot/vboot_crtm.c@173 PS13, Line 173: if (tclt) > When would this be NULL? Done https://review.coreboot.org/#/c/29563/13/src/security/vboot/vboot_crtm.c@188 PS13, Line 188: ROMSTAGE_CBMEM_INIT_HOOK(recover_tcpa_log); > Do you want to handle other conditions of cbmem coming online later? If so you need the other CBMEM_ […] mhh I guess you are right. Only ramstage and postcar are leftovers ? -- To view, visit https://review.coreboot.org/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 13 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph (1001864) Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 15:48:45 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 19 Nov '18

19 Nov '18

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/29662 ) Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/#/c/29662/5/src/soc/intel/braswell/bootblock/ca… File src/soc/intel/braswell/bootblock/cache_as_ram_cbootblock.S: https://review.coreboot.org/#/c/29662/5/src/soc/intel/braswell/bootblock/ca… PS5, Line 21: #include <device/pci_def.h> > that looks like a copy of drivers/intel/fsp1_1/cache_as_ram.inc. […] Specific support (provide timestamp, bootblock_pre_c_entry label) for C bootblock is required. https://review.coreboot.org/#/c/29662/2/src/soc/intel/braswell/romstage/car… File src/soc/intel/braswell/romstage/car_stage.S: https://review.coreboot.org/#/c/29662/2/src/soc/intel/braswell/romstage/car… PS2, Line 23: > What I meant is 2. Replace all occurence of romstage_c_entry on braswell with car_stage_c_entry. […] Replacing with car_stage_c_entry() results into a build error on the Intel Quark platforms which have this function in SoC and uses FSP1.1 -- To view, visit https://review.coreboot.org/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 14:38:21 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/gm45/northbridge.c: Check for NULL pointers
by Nico Huber (Code Review) 19 Nov '18

19 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/29688 ) Change subject: nb/intel/gm45/northbridge.c: Check for NULL pointers ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic12a8c145d6348086f9931af93ce6d3b3dcb9039 Gerrit-Change-Number: 29688 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 14:15:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
by Patrick Rudolph (Code Review) 19 Nov '18

19 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29662 ) Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/#/c/29662/5/src/soc/intel/braswell/bootblock/ca… File src/soc/intel/braswell/bootblock/cache_as_ram_cbootblock.S: https://review.coreboot.org/#/c/29662/5/src/soc/intel/braswell/bootblock/ca… PS5, Line 21: #include <device/pci_def.h> that looks like a copy of drivers/intel/fsp1_1/cache_as_ram.inc. Why do you need to duplicate it ? https://review.coreboot.org/#/c/29662/2/src/soc/intel/braswell/romstage/car… File src/soc/intel/braswell/romstage/car_stage.S: https://review.coreboot.org/#/c/29662/2/src/soc/intel/braswell/romstage/car… PS2, Line 23: > I agree that might change filename into car_stage_entry.S, but don't understand your comment: […] What I meant is 2. Replace all occurence of romstage_c_entry on braswell with car_stage_c_entry. In that case you don't need this file at all. -- To view, visit https://review.coreboot.org/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 19 Nov 2018 14:14:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/intel/fsp1_1: Add post console init functions for C bootblock
by Frans Hendriks (Code Review) 19 Nov '18

19 Nov '18

Frans Hendriks has abandoned this change. ( https://review.coreboot.org/29660 ) Change subject: drivers/intel/fsp1_1: Add post console init functions for C bootblock ...................................................................... Abandoned Corrupted this check in by patchset 2 -- To view, visit https://review.coreboot.org/29660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I12e613147e5203022cd453693a115fca002ce480 Gerrit-Change-Number: 29660 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: drivers/intel/fsp1_1: Add post console init functions for C bootblock
by Frans Hendriks (Code Review) 19 Nov '18

19 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29660 to look at the new patch set (#2). Change subject: drivers/intel/fsp1_1: Add post console init functions for C bootblock ...................................................................... drivers/intel/fsp1_1: Add post console init functions for C bootblock The console post init functions are not executed in C_ENVIRONMENT_BOOTBLOCK mode. Add car_XXXX_post_console_init functions to romstage_c_entry(). BUG=NA TEST=Portwell PQ7-M107 Change-Id: I12e613147e5203022cd453693a115fca002ce480 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc A src/soc/intel/braswell/bootblock/bootblock_c.c A src/soc/intel/braswell/bootblock/cache_as_ram_cbootblock.S M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/car_stage_entry.S 6 files changed, 315 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/29660/2 -- To view, visit https://review.coreboot.org/29660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I12e613147e5203022cd453693a115fca002ce480 Gerrit-Change-Number: 29660 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/braswell: Add support for FSP MR2
by Frans Hendriks (Code Review) 19 Nov '18

19 Nov '18

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/29661 ) Change subject: soc/intel/braswell: Add support for FSP MR2 ...................................................................... Patch Set 2: > Patch Set 2: > > FSP MR2 seems to not be compatible (is it possible!?) with the braswell SoC I have: > Intel Atom x5-E8000 CPU 1.04GHz > Cpuid 000406c4 cpus 4 rid 35 step D1 > > Although FPS signature and revision is detected well: > > FSP Signature: BSWSBFSP > FSP Header Version: 2 > FSP Revision: 1.1.4.1 > > I'm stuck at post FSP MemoryInit (0x92). I have to stick to older FSP I guess. I have also checked whether I use the unsupported UPD values, but it is not the case. Is it supported only on CherryChill CRB? Portwell M107 used same CPU, where it works fine. -- To view, visit https://review.coreboot.org/29661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Gerrit-Change-Number: 29661 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Mon, 19 Nov 2018 13:08:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/braswell: Add support for FSP MR2
by Michał Żygowski (Code Review) 19 Nov '18

19 Nov '18

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/29661 ) Change subject: soc/intel/braswell: Add support for FSP MR2 ...................................................................... Patch Set 2: FSP MR2 seems to not be compatible (is it possible!?) with the braswell SoC I have: Intel Atom x5-E8000 CPU 1.04GHz Cpuid 000406c4 cpus 4 rid 35 step D1 Although FPS signature and revision is detected well: FSP Signature: BSWSBFSP FSP Header Version: 2 FSP Revision: 1.1.4.1 I'm stuck at post FSP MemoryInit (0x92). I have to stick to older FSP I guess. I have also checked whether I use the unsupported UPD values, but it is not the case. Is it supported only on CherryChill CRB? -- To view, visit https://review.coreboot.org/29661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Gerrit-Change-Number: 29661 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Mon, 19 Nov 2018 12:59:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit November 2018