coreboot-gerrit November 2018

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Change in ...coreboot[master]: soc/intel/icelake: Create macros for FSP consumption as per ICL requi...
by build bot (Jenkins) (Code Review) 20 Nov '18

20 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29748 ) Change subject: soc/intel/icelake: Create macros for FSP consumption as per ICL requirement ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29748/1/src/soc/intel/icelake/include/soc/s… File src/soc/intel/icelake/include/soc/serialio.h: https://review.coreboot.org/#/c/29748/1/src/soc/intel/icelake/include/soc/s… PS1, Line 25: } PCH_SERIAL_IO_MODE; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I524c7ed116aeb8b353123d7b1d9815b0f249d0e6 Gerrit-Change-Number: 29748 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Nov 2018 22:41:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/icelake: Create macros for FSP consumption as per ICL requi...
by Shelley Chen (Code Review) 20 Nov '18

20 Nov '18

Hello Subrata Banik, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/29748 to review the following change. Change subject: soc/intel/icelake: Create macros for FSP consumption as per ICL requirement ...................................................................... soc/intel/icelake: Create macros for FSP consumption as per ICL requirement 1. Modify PCIEXBAR to accomodate TCSS RP 2. LPSS device mode selection 3. Add option to emable/disable audio controller. Change-Id: I524c7ed116aeb8b353123d7b1d9815b0f249d0e6 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/include/soc/serialio.h 3 files changed, 52 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/29748/1 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index c4ee841..727fccee 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -126,6 +126,10 @@ help This option allows you to select MMIO Base Address of sideband bus. +config MMCONF_BASE_ADDRESS + hex + default 0xc0000000 + config CPU_BCLK_MHZ int default 100 @@ -146,6 +150,10 @@ int default 6 +config SOC_INTEL_UART_DEV_MAX + int + default 3 + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index cb06fcb..6bd836e 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -121,6 +121,7 @@ uint8_t SataPortsDevSlp[8]; /* Audio related */ + uint8_t EnableAzalia; uint8_t PchHdaEnable; uint8_t PchHdaDspEnable; @@ -152,11 +153,16 @@ /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; /* Need to update DLL setting to get Emmc running at HS400 speed */ - uint8_t EmmcHs400DllNeed; - /* 0-39: number of active delay for RX strobe, unit is 125 psec */ - uint8_t EmmcHs400RxStrobeDll1; - /* 0-78: number of active delay for TX data, unit is 125 psec */ - uint8_t EmmcHs400TxDataDll; + uint8_t EmmcUseCustomDlls; + uint32_t EmmcTxCmdDelayRegValue; + uint32_t EmmcTxDataDelay1RegValue; + uint32_t EmmcTxDataDelay2RegValue; + uint32_t EmmcRxCmdDataDelay1RegValue; + uint32_t EmmcRxCmdDataDelay2RegValue; + uint32_t EmmcRxStrobeDelayRegValue; + + /* Enable if SD Card Power Enable Signal is Active High */ + uint8_t SdCardPowerEnableActiveHigh; /* Integrated Sensor */ uint8_t PchIshEnable; @@ -219,28 +225,17 @@ } DebugConsent; /* * SerialIO device mode selection: - * - * Device index: - * PchSerialIoIndexI2C0 - * PchSerialIoIndexI2C1 - * PchSerialIoIndexI2C2 - * PchSerialIoIndexI2C3 - * PchSerialIoIndexI2C4 - * PchSerialIoIndexI2C5 - * PchSerialIoIndexSPI0 - * PchSerialIoIndexSPI1 - * PchSerialIoIndexSPI2 - * PchSerialIoIndexUART0 - * PchSerialIoIndexUART1 - * PchSerialIoIndexUART2 - * - * Mode select: - * PchSerialIoDisabled - * PchSerialIoPci - * PchSerialIoAcpi - * PchSerialIoHidden + * PchSerialIoDisabled, + * PchSerialIoPci, + * PchSerialIoHidden, + * PchSerialIoLegacyUart, + * PchSerialIoSkipInit */ - uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; + uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; @@ -251,6 +246,14 @@ /* Intel VT configuration */ uint8_t VtdDisable; uint8_t VmxEnable; + + /* CNVi BT Audio Offload + Enable/Disable BT Audio Offload. + 0: PLATFORM_POR, + 1: FORCE_ENABLE, + 2: FORCE_DISABLE. + */ + uint8_t CnviBtAudioOffload; }; typedef struct soc_intel_icelake_config config_t; diff --git a/src/soc/intel/icelake/include/soc/serialio.h b/src/soc/intel/icelake/include/soc/serialio.h index 30a48a1..8f18eb8 100644 --- a/src/soc/intel/icelake/include/soc/serialio.h +++ b/src/soc/intel/icelake/include/soc/serialio.h @@ -19,9 +19,10 @@ typedef enum { PchSerialIoDisabled, PchSerialIoPci, - PchSerialIoAcpi, PchSerialIoHidden, -} PCH_SERIAL_IO_MODE; + PchSerialIoLegacyUart, + PchSerialIoSkipInit + } PCH_SERIAL_IO_MODE; typedef enum { PchSerialIoIndexI2C0, @@ -29,14 +30,19 @@ PchSerialIoIndexI2C2, PchSerialIoIndexI2C3, PchSerialIoIndexI2C4, - PchSerialIoIndexI2C5, - PchSerialIoIndexSPI0, - PchSerialIoIndexSPI1, - PchSerialIoIndexSPI2, + PchSerialIoIndexI2C5 +} PCH_SERIAL_IO_I2C_CONTROLLER; + +typedef enum { + PchSerialIoIndexGSPI0, + PchSerialIoIndexGSPI1, + PchSerialIoIndexGSPI2 +} PCH_SERIAL_IO_GSPI_CONTROLLER; + +typedef enum { PchSerialIoIndexUART0, PchSerialIoIndexUART1, - PchSerialIoIndexUART2, - PchSerialIoIndexMAX -} PCH_SERIAL_IO_CONTROLLER; + PchSerialIoIndexUART2 +} PCH_SERIAL_IO_UART_CONTROLLER; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I524c7ed116aeb8b353123d7b1d9815b0f249d0e6 Gerrit-Change-Number: 29748 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: WIP: DSP capabilities need to be enabled to allow DSP firmware to be ...
by Sathyanarayana Nujella (Code Review) 20 Nov '18

20 Nov '18

Sathyanarayana Nujella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29747 ) Change subject: WIP: DSP capabilities need to be enabled to allow DSP firmware to be loaded successfully. ...................................................................... Patch Set 1: Code-Review-1 Under validation in both of the baords now -- To view, visit https://review.coreboot.org/c/coreboot/+/29747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If59810e358eb0127df0c912655fca28124e2814a Gerrit-Change-Number: 29747 Gerrit-PatchSet: 1 Gerrit-Owner: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Nov 2018 20:52:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: WIP: DSP capabilities need to be enabled to allow DSP firmware to be ...
by Sathyanarayana Nujella (Code Review) 20 Nov '18

20 Nov '18

Sathyanarayana Nujella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29747 Change subject: WIP: DSP capabilities need to be enabled to allow DSP firmware to be loaded successfully. ...................................................................... WIP: DSP capabilities need to be enabled to allow DSP firmware to be loaded successfully. Change-Id: If59810e358eb0127df0c912655fca28124e2814a Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29747/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index ee1cca0..958c5c2 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -28,6 +28,9 @@ register "SkipExtGfxScan" = "1" register "VmxEnable" = "1" + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + register "speed_shift_enable" = "1" register "s0ix_enable" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b33c923..ab60855 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -28,6 +28,9 @@ register "SkipExtGfxScan" = "1" register "VmxEnable" = "1" + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + register "speed_shift_enable" = "1" register "s0ix_enable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/29747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If59810e358eb0127df0c912655fca28124e2814a Gerrit-Change-Number: 29747 Gerrit-PatchSet: 1 Gerrit-Owner: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/uart/Kconfig: Be smarter about DRIVERS_UART_8250IO
by Nico Huber (Code Review) 20 Nov '18

20 Nov '18

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29571 ) Change subject: drivers/uart/Kconfig: Be smarter about DRIVERS_UART_8250IO ...................................................................... drivers/uart/Kconfig: Be smarter about DRIVERS_UART_8250IO It defaults to y to avoid having to select it per mainboard. But that makes a mess because it results in linker conflicts unless other UART drivers disable it explicitly. We try to be smarter about the default value for now. The real solu- tion would be to hardcode it per mainboard. But who knows which boards actually have it? Change-Id: I7e755fe0e4f6d1c31ef2854603a5510c3cdc4967 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/29571 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/uart/Kconfig M src/soc/intel/denverton_ns/Kconfig 2 files changed, 4 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 39d20a3..1130aeb 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -4,8 +4,11 @@ default n config DRIVERS_UART_8250IO + # FIXME: Shouldn't have a prompt, should default to n, and + # should be selected by boards that have it instead. bool "Serial port on SuperIO" depends on ARCH_X86 + default n if DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL default n if NO_UART_ON_SUPERIO default y diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index d4ae805..5b704b9 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -162,7 +162,7 @@ endchoice config ENABLE_HSUART - depends on (!DRIVERS_UART_8250IO && NON_LEGACY_UART_MODE) + depends on NON_LEGACY_UART_MODE bool "Enable High-speed UART debug port selected by UART_FOR_CONSOLE." default n select CONSOLE_SERIAL -- To view, visit https://review.coreboot.org/c/coreboot/+/29571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e755fe0e4f6d1c31ef2854603a5510c3cdc4967 Gerrit-Change-Number: 29571 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: (console, drivers/uart)/Kconfig: Fix dependencies
by Nico Huber (Code Review) 20 Nov '18

20 Nov '18

Hello Julius Werner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29572 to look at the new patch set (#5). Change subject: (console,drivers/uart)/Kconfig: Fix dependencies ...................................................................... (console,drivers/uart)/Kconfig: Fix dependencies The dependencies of CONSOLE_SERIAL and DRIVERS_UART were somehow backwards. Fix that. Now, CONSOLE_SERIAL depends on DRIVERS_UART, because it's using its interface. The individual UART drivers select DRIVERS_UART, because they implement the interface and depend on the common UART code. Some guards had to be fixed (using CONSOLE_SERIAL now instead of DRIVERS_UART). Some other guards that were only about compilation of units were removed. We want to build test as much as possible, right? Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/console/Kconfig M src/cpu/allwinner/a10/Makefile.inc M src/cpu/ti/am335x/Makefile.inc M src/drivers/uart/Kconfig M src/mainboard/google/gru/bootblock.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_rialto/bootblock.c M src/soc/broadcom/cygnus/Makefile.inc M src/soc/cavium/cn81xx/Makefile.inc M src/soc/imgtec/pistachio/Makefile.inc M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8183/Makefile.inc M src/soc/nvidia/tegra124/Makefile.inc M src/soc/nvidia/tegra210/Makefile.inc M src/soc/qualcomm/ipq40xx/Makefile.inc M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq806x/Makefile.inc M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/sdm845/Makefile.inc M src/soc/rockchip/rk3288/Makefile.inc M src/soc/rockchip/rk3399/Makefile.inc M src/soc/samsung/exynos5250/Makefile.inc M src/soc/samsung/exynos5420/Makefile.inc 24 files changed, 64 insertions(+), 102 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29572/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/29572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Gerrit-Change-Number: 29572 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: (console, drivers/uart)/Kconfig: Fix dependencies
by Nico Huber (Code Review) 20 Nov '18

20 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29572 ) Change subject: (console,drivers/uart)/Kconfig: Fix dependencies ...................................................................... Patch Set 4: Sorry, I was just about to check if everything is fine after a final rebase... turned out it wasn't even before. I missed cavium/cn81xx and samsung/exynos5420 the first time, don't know how ._. -- To view, visit https://review.coreboot.org/c/coreboot/+/29572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Gerrit-Change-Number: 29572 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Nov 2018 17:37:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: (console, drivers/uart)/Kconfig: Fix dependencies
by Nico Huber (Code Review) 20 Nov '18

20 Nov '18

Hello Julius Werner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29572 to look at the new patch set (#4). Change subject: (console,drivers/uart)/Kconfig: Fix dependencies ...................................................................... (console,drivers/uart)/Kconfig: Fix dependencies The dependencies of CONSOLE_SERIAL and DRIVERS_UART were somehow backwards. Fix that. Now, CONSOLE_SERIAL depends on DRIVERS_UART, because it's using its interface. The individual UART drivers select DRIVERS_UART, because they implement the interface and depend on the common UART code. Some guards had to be fixed (using CONSOLE_SERIAL now instead of DRIVERS_UART). Some other guards that were only about compilation of units were removed. We want to build test as much as possible, right? Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M 3rdparty/chromeec M src/console/Kconfig M src/cpu/allwinner/a10/Makefile.inc M src/cpu/ti/am335x/Makefile.inc M src/drivers/uart/Kconfig M src/mainboard/google/gru/bootblock.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_rialto/bootblock.c M src/soc/broadcom/cygnus/Makefile.inc M src/soc/cavium/cn81xx/Makefile.inc M src/soc/imgtec/pistachio/Makefile.inc M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8183/Makefile.inc M src/soc/nvidia/tegra124/Makefile.inc M src/soc/nvidia/tegra210/Makefile.inc M src/soc/qualcomm/ipq40xx/Makefile.inc M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq806x/Makefile.inc M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/sdm845/Makefile.inc M src/soc/rockchip/rk3288/Makefile.inc M src/soc/rockchip/rk3399/Makefile.inc M src/soc/samsung/exynos5250/Makefile.inc M src/soc/samsung/exynos5420/Makefile.inc 25 files changed, 65 insertions(+), 103 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29572/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Gerrit-Change-Number: 29572 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock
by build bot (Jenkins) (Code Review) 20 Nov '18

20 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25442 ) Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/25442/8/src/soc/intel/denverton_ns/lpc.c File src/soc/intel/denverton_ns/lpc.c: https://review.coreboot.org/#/c/25442/8/src/soc/intel/denverton_ns/lpc.c@418 PS8, Line 418: if(!relax_security) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/25442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd Gerrit-Change-Number: 25442 Gerrit-PatchSet: 8 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Tue, 20 Nov 2018 13:16:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock
by build bot (Jenkins) (Code Review) 20 Nov '18

20 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25442 ) Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/25442/7/src/soc/intel/denverton_ns/lpc.c File src/soc/intel/denverton_ns/lpc.c: https://review.coreboot.org/#/c/25442/7/src/soc/intel/denverton_ns/lpc.c@418 PS7, Line 418: if(!relax_security) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/25442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd Gerrit-Change-Number: 25442 Gerrit-PatchSet: 7 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Tue, 20 Nov 2018 13:09:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2018