coreboot-gerrit November 2018

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Change in ...coreboot[master]: ec/google/wilco/acpi: Add DPTF support
by Duncan Laurie (Code Review) 21 Nov '18

21 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29761 Change subject: ec/google/wilco/acpi: Add DPTF support ...................................................................... ec/google/wilco/acpi: Add DPTF support Add the support needed for DPTF. This includes the methods to write trip point values, read temperatures, and handle events. This was tested on a sarien board by inspecting AML debug output with the kernel while monitoring temperatures and trip points in sysfs and controlling temperatures with a fan to ensure that when a trip point is crossed an SCI is generated and the event is handled properly. Change-Id: I8d8570d176c0896fa709a6c782b319f58d3c1e52 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- A src/ec/google/wilco/acpi/dptf.asl M src/ec/google/wilco/acpi/ec.asl M src/ec/google/wilco/acpi/ec_ram.asl M src/ec/google/wilco/acpi/event.asl 4 files changed, 155 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/29761/1 diff --git a/src/ec/google/wilco/acpi/dptf.asl b/src/ec/google/wilco/acpi/dptf.asl new file mode 100644 index 0000000..0f1663f --- /dev/null +++ b/src/ec/google/wilco/acpi/dptf.asl @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Dynamic Platform Thermal Framework support + */ + +/* Mutex for EC PAT interface */ +Mutex (PATM, 1) + +/* Read requested temperature sensor */ +Method (TSRD, 1, Serialized) +{ + If (Acquire (^PATM, 1000)) { + Return (0) + } + + /* Set sensor ID */ + W (DWTI, ToInteger (Arg0)) + + Local0 = R (DRTV) + + Release (^PATM) + Return (\_SB.DPTF.CTOK (Local0)) +} + +/* + * Set Aux Trip Point 0 + * Arg0 = Temp Sensor ID + * Arg1 = Value to set + */ +Method (PAT0, 2, Serialized) +{ + If (Acquire (^PATM, 1000)) { + Return (0) + } + + /* Set sensor ID */ + W (DWTI, ToInteger (Arg0)) + + /* Set LOW trip point for this sensor */ + W (DWTL, \_SB.DPTF.KTOC (Arg1)) + + Release (^PATM) + Return (1) +} + +/* + * Set Aux Trip Point 1 + * Arg0 = Temp Sensor ID + * Arg1 = Value to set + */ +Method (PAT1, 2, Serialized) +{ + If (Acquire (^PATM, 1000)) { + Return (0) + } + + /* Set sensor ID */ + W (DWTI, ToInteger (Arg0)) + + /* Set HIGH trip point for this sensor */ + W (DWTH, \_SB.DPTF.KTOC (Arg1)) + + Release (^PATM) + Return (1) +} + +/* + * Disable Aux Trip Points + * Arg0 = Temp Sensor ID + */ +Method (PATD, 1, Serialized) +{ + If (Acquire (^PATM, 1000)) { + Return (0) + } + + /* Set sensor ID */ + W (DWTI, ToInteger (Arg0)) + + /* Disable LOW and HIGH trip points */ + W (DWTL, 0xff) + W (DWTH, 0xff) + + Release (^PATM) + Return (1) +} + +/* + * Handle sensor trip events + */ +Method (PATX, 0, Serialized) +{ + Local0 = R (DRTQ) + Local1 = Local0 + + Printf ("Sensor trip mask: %o", Local0) + + If (LNot (Acquire (^PATM, 1000))) { + + /* Handle bits that are set */ + While (FindSetRightBit (Local1, Local2)) + { + /* DPTF will Notify sensor devices */ + \_SB.DPTF.TEVT (Local2) + + /* Clear current sensor number */ + Local1 &= ~(1 << (Local2 - 1)) + } + + Release (^PATM) + } + + /* Clear sensor events */ + W (DWTQ, Local0) +} diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 67a698f..ff8fccc 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -49,6 +49,11 @@ /* Tell EC to stop emulating PS/2 mouse */ W (PS2M, Zero) + + /* Enable DPTF support if enabled in devicetree */ + If (\DPTE == One) { + W (DWST, Arg1) + } } /* @@ -142,4 +147,5 @@ #include "event.asl" #include "lid.asl" #include "platform.asl" + #include "dptf.asl" } diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl index 6ea2366..1563a3c 100644 --- a/src/ec/google/wilco/acpi/ec_ram.asl +++ b/src/ec/google/wilco/acpi/ec_ram.asl @@ -106,6 +106,14 @@ Name (QSEC, Package () { 0x2b, 0xff, RD }) /* QS Event Count */ Name (QSEB, Package () { 0x2c, 0xff, RD }) /* QS Event Byte */ +Name (DRST, Package () { 0x32, 0xff, RD }) /* DPTF: Read State */ +Name (DRTI, Package () { 0x33, 0xff, RD }) /* DPTF: Read Thermal Index */ +Name (DRTV, Package () { 0x34, 0xff, RD }) /* DPTF: Read Thermal Value */ +Name (DRTL, Package () { 0x35, 0xff, RD }) /* DPTF: Read Trip Low */ +Name (DRTH, Package () { 0x36, 0xff, RD }) /* DPTF: Read Trip High */ +Name (DRHY, Package () { 0x37, 0xff, RD }) /* DPTF: Read Hysteresis */ +Name (DRTQ, Package () { 0x38, 0xff, RD }) /* DPTF: Read Trip Query */ + Name (ORST, Package () { 0x39, 0xff, RD }) /* Orientation State */ Name (OREV, Package () { 0x3a, 0xff, RD }) /* Orientation Events */ Name (OECH, Package () { 0x3a, 0x01, RD }) /* Event: Orientation */ @@ -128,3 +136,9 @@ Name (ERDY, Package () { 0x05, 0xff, WR }) /* EC Ready */ Name (FWAK, Package () { 0x06, 0xff, WR }) /* EC _WAK */ Name (PS2M, Package () { 0x20, 0xff, WR }) /* EC PS/2 Mouse Emulation */ +Name (DWST, Package () { 0x32, 0xff, WR }) /* DPTF: Write State */ +Name (DWTI, Package () { 0x33, 0xff, WR }) /* DPTF: Write Thermal Index */ +Name (DWTL, Package () { 0x35, 0xff, WR }) /* DPTF: Write Trip Low */ +Name (DWTH, Package () { 0x36, 0xff, WR }) /* DPTF: Write Trip High */ +Name (DWHY, Package () { 0x37, 0xff, WR }) /* DPTF: Write Hysteresis */ +Name (DWTQ, Package () { 0x38, 0xff, WR }) /* DPTF: Write Trip Query */ diff --git a/src/ec/google/wilco/acpi/event.asl b/src/ec/google/wilco/acpi/event.asl index 4d796b5..21721f2 100644 --- a/src/ec/google/wilco/acpi/event.asl +++ b/src/ec/google/wilco/acpi/event.asl @@ -87,6 +87,11 @@ Method (ECQ3, 1, Serialized) { Printf ("EVT3: %o", Arg0) + + /* Theraml Events */ + If (EBIT (E3TH, Arg0)) { + ^PATX () + } } /* Handle events in PmEv4 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d8570d176c0896fa709a6c782b319f58d3c1e52 Gerrit-Change-Number: 29761 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/google/wilco/acpi: Fix issues and clean up
by Duncan Laurie (Code Review) 21 Nov '18

21 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29760 Change subject: ec/google/wilco/acpi: Fix issues and clean up ...................................................................... ec/google/wilco/acpi: Fix issues and clean up - Disable debug output from read/write methods by default - Use argument to _REG to disable SCI when EC is unregistered - Change read/write macros to sync level 2 so they can be called when a mutex is already held - Define some missing events Change-Id: Ic65ebbb6a6151444c47b4aeff7429e186856c49a Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/acpi/ec.asl M src/ec/google/wilco/acpi/ec_ram.asl 2 files changed, 14 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/29760/1 diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index cddfe3f..67a698f 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -20,6 +20,7 @@ Name (_UID, 1) Name (_GPE, EC_SCI_GPI) Name (_STA, 0xf) + Name (DBUG, Zero) Name (_CRS, ResourceTemplate() { IO (Decode16, @@ -44,7 +45,7 @@ ECPR = R (APWR) /* Indicate to EC that OS is ready for queries */ - W (ERDY, One) + W (ERDY, Arg1) /* Tell EC to stop emulating PS/2 mouse */ W (PS2M, Zero) @@ -71,7 +72,7 @@ * Arg0 = EC field structure * Arg1 = Value to write */ - Method (ECRW, 2, Serialized) + Method (ECRW, 2, Serialized, 2) { If (!EREG) { Return (Zero) @@ -101,11 +102,15 @@ } Local5 = EBIT (Arg0, Local3) - Printf ("ECRD %o = %o", Local0, Local5) + If (DBUG) { + Printf ("ECRD %o = %o", Local0, Local5) + } Return (Local5) } ElseIf (Local2 == WR) { /* Write byte */ - Printf ("ECWR %o = %o", Local0, Arg1) + If (DBUG) { + Printf ("ECWR %o = %o", Local0, Arg1) + } BYT1 = Arg1 } Return (Zero) @@ -115,7 +120,7 @@ * Read a field from EC * Arg0 = EC field structure */ - Method (R, 1, Serialized) + Method (R, 1, Serialized, 2) { Return (ECRW (Arg0, Zero)) } @@ -125,7 +130,7 @@ * Arg0 = EC field structure * Arg1 = Value to write */ - Method (W, 2, Serialized) + Method (W, 2, Serialized, 2) { Return (ECRW (Arg0, Arg1)) } diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl index e2b6a93..6ea2366 100644 --- a/src/ec/google/wilco/acpi/ec_ram.asl +++ b/src/ec/google/wilco/acpi/ec_ram.asl @@ -81,6 +81,9 @@ Name (WBAT, Package () { 0x09, 0x80, RD }) /* Wake: Low Battery */ Name (EVT3, Package () { 0x0b, 0xff, RD }) /* Event 3 */ +Name (E3CP, Package () { 0x0b, 0x08, RD }) /* CS Power Button */ +Name (E3TH, Package () { 0x0b, 0x10, RD }) /* Thermal Event */ + Name (EVT4, Package () { 0x0c, 0xff, RD }) /* Event 4 */ Name (BCST, Package () { 0x10, 0xff, RD }) /* BCACHE: BST */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic65ebbb6a6151444c47b4aeff7429e186856c49a Gerrit-Change-Number: 29760 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/dptf: Add method for temp conversion
by Duncan Laurie (Code Review) 21 Nov '18

21 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29758 Change subject: soc/intel/common/dptf: Add method for temp conversion ...................................................................... soc/intel/common/dptf: Add method for temp conversion Add a method to convert from 1/10 Kelvin to Celsius. This is useful for EC devices where the sensor temperature are stored in Celsius instead of Kelvin. Change-Id: I6b1154f5ba13416131a029966d6d5c1598904881 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/common/acpi/dptf/dptf.asl 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29758/1 diff --git a/src/soc/intel/common/acpi/dptf/dptf.asl b/src/soc/intel/common/acpi/dptf/dptf.asl index beb41e2..1dd57c0 100644 --- a/src/soc/intel/common/acpi/dptf/dptf.asl +++ b/src/soc/intel/common/acpi/dptf/dptf.asl @@ -95,6 +95,21 @@ Return (Local0) } + /* Convert from 1/10 Kelvin to Degrees C for ACPI */ + Method (KTOC, 1) { + If (LLessEqual (Arg0, 2732)) { + Return (0) + } + + /* Convert to Celsius */ + Subtract (Arg0, 2732, Local0) + + /* Convert from 10th of degrees */ + Divide (Local0, 10,, Local0) + + Return (Local0) + } + /* Include Thermal Participants */ #include "thermal.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/29758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1154f5ba13416131a029966d6d5c1598904881 Gerrit-Change-Number: 29758 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add DPTF ACPI code
by Duncan Laurie (Code Review) 21 Nov '18

21 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29759 Change subject: soc/intel/cannonlake: Add DPTF ACPI code ...................................................................... soc/intel/cannonlake: Add DPTF ACPI code Define the constants that DPTF expects from the SOC in order to use the common DPTF ACPI code. For cannonlake this indicates the CPU device is called B0D4 and is at PCI address 00:04.0. Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- A src/soc/intel/cannonlake/acpi/dptf.asl 1 file changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/29759/1 diff --git a/src/soc/intel/cannonlake/acpi/dptf.asl b/src/soc/intel/cannonlake/acpi/dptf.asl new file mode 100644 index 0000000..098a61c --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/dptf.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_DEVICE B0D4 +#define DPTF_CPU_ADDR 0x00040000 + +#ifndef DPTF_CPU_PASSIVE +#define DPTF_CPU_PASSIVE 80 +#endif + +#ifndef DPTF_CPU_CRITICAL +#define DPTF_CPU_CRITICAL 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC0 +#define DPTF_CPU_ACTIVE_AC0 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC1 +#define DPTF_CPU_ACTIVE_AC1 80 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC2 +#define DPTF_CPU_ACTIVE_AC2 70 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC3 +#define DPTF_CPU_ACTIVE_AC3 60 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC4 +#define DPTF_CPU_ACTIVE_AC4 50 +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128 Gerrit-Change-Number: 29759 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/dptf: Make CPU address a define
by Duncan Laurie (Code Review) 21 Nov '18

21 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29757 Change subject: soc/intel/common/dptf: Make CPU address a define ...................................................................... soc/intel/common/dptf: Make CPU address a define In order to support using the common ACPI code on more platforms than just Apollo Lake the DPTF code needs to be told what the PCI address is for the CPU thermal device. Change-Id: I638f2387330bbc42f64eb0fb676ee32c5df6572e Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/apollolake/acpi/dptf.asl M src/soc/intel/common/acpi/dptf/cpu.asl 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29757/1 diff --git a/src/soc/intel/apollolake/acpi/dptf.asl b/src/soc/intel/apollolake/acpi/dptf.asl index b9ba9c3..f34725f 100644 --- a/src/soc/intel/apollolake/acpi/dptf.asl +++ b/src/soc/intel/apollolake/acpi/dptf.asl @@ -14,6 +14,7 @@ */ #define DPTF_CPU_DEVICE TCPU +#define DPTF_CPU_ADDR 0x00000001 #ifndef DPTF_CPU_PASSIVE #define DPTF_CPU_PASSIVE 80 diff --git a/src/soc/intel/common/acpi/dptf/cpu.asl b/src/soc/intel/common/acpi/dptf/cpu.asl index c28c0cc..9414e25 100644 --- a/src/soc/intel/common/acpi/dptf/cpu.asl +++ b/src/soc/intel/common/acpi/dptf/cpu.asl @@ -23,7 +23,7 @@ Device (DPTF_CPU_DEVICE) { - Name(_ADR, 0x00000001) + Name(_ADR, DPTF_CPU_ADDR) Method (_STA) { -- To view, visit https://review.coreboot.org/c/coreboot/+/29757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I638f2387330bbc42f64eb0fb676ee32c5df6572e Gerrit-Change-Number: 29757 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Remove CPU ACPI code
by Duncan Laurie (Code Review) 21 Nov '18

21 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29756 Change subject: soc/intel/cannonlake: Remove CPU ACPI code ...................................................................... soc/intel/cannonlake: Remove CPU ACPI code Remove the cannonlake-specific CPU ACPI code and instead use the newly added common CPU ACPI code. Change-Id: Id526dc503f278b5cf3a8ce5ccec6f751aa777df0 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- D src/soc/intel/cannonlake/acpi/cpu.asl 1 file changed, 0 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/29756/1 diff --git a/src/soc/intel/cannonlake/acpi/cpu.asl b/src/soc/intel/cannonlake/acpi/cpu.asl deleted file mode 100644 index 79314e6..0000000 --- a/src/soc/intel/cannonlake/acpi/cpu.asl +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) -External (\_PR.CP04, DeviceObj) -External (\_PR.CP05, DeviceObj) -External (\_PR.CP06, DeviceObj) -External (\_PR.CP07, DeviceObj) - -/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ -Method (PNOT) -{ - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x81) // _CST - Notify (\_PR.CP05, 0x81) // _CST - Notify (\_PR.CP06, 0x81) // _CST - Notify (\_PR.CP07, 0x81) // _CST - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/29756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id526dc503f278b5cf3a8ce5ccec6f751aa777df0 Gerrit-Change-Number: 29756 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/acpi: Add common CPU methods
by Duncan Laurie (Code Review) 21 Nov '18

21 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29754 Change subject: soc/intel/common/acpi: Add common CPU methods ...................................................................... soc/intel/common/acpi: Add common CPU methods Add a common ASL file for expected CPU methods so it does not need to be duplicated in every SOC implementation. Change-Id: Ifd467ef84a391698cd395172c3f0d4e801bdd09b Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- A src/soc/intel/common/acpi/cpu.asl 1 file changed, 118 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29754/1 diff --git a/src/soc/intel/common/acpi/cpu.asl b/src/soc/intel/common/acpi/cpu.asl new file mode 100644 index 0000000..79eaac4 --- /dev/null +++ b/src/soc/intel/common/acpi/cpu.asl @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* These devices are created at runtime */ +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) + +/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ +Method (PNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST + } +} + +/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ +Method (PPCN) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC + } +} + +/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ +Method (TNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC + } +} + +/* Return a package containing enabled processor entries */ +Method (PPKG) +{ + If (LGreaterEqual (\PCNT, 8)) { + Return (Package() + { + \_PR.CP00, + \_PR.CP01, + \_PR.CP02, + \_PR.CP03, + \_PR.CP04, + \_PR.CP05, + \_PR.CP06, + \_PR.CP07 + }) + } ElseIf (LGreaterEqual (\PCNT, 4)) { + Return (Package () + { + \_PR.CP00, + \_PR.CP01, + \_PR.CP02, + \_PR.CP03 + }) + } ElseIf (LGreaterEqual (\PCNT, 2)) { + Return (Package () + { + \_PR.CP00, + \_PR.CP01 + }) + } Else { + Return (Package () + { + \_PR.CP00 + }) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd467ef84a391698cd395172c3f0d4e801bdd09b Gerrit-Change-Number: 29754 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/{zoombini, sarien}: Use common CPU ACPI code
by Duncan Laurie (Code Review) 21 Nov '18

21 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29755 Change subject: mb/google/{zoombini,sarien}: Use common CPU ACPI code ...................................................................... mb/google/{zoombini,sarien}: Use common CPU ACPI code Instead of using the cannonlake specific CPU ACPI code (which is incomplete) use the newly added common CPU ACPI code that does include the required methods. Change-Id: Ief3de0c8061fd1a985fecbc355062eb23d046d6d Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/zoombini/dsdt.asl 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/29755/1 diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 18fedd5..110a214 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -31,7 +31,7 @@ #include <soc/intel/cannonlake/acpi/globalnvs.asl> /* CPU */ - #include <soc/intel/cannonlake/acpi/cpu.asl> + #include <soc/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PWRB) diff --git a/src/mainboard/google/zoombini/dsdt.asl b/src/mainboard/google/zoombini/dsdt.asl index 3140990..2d8229d 100644 --- a/src/mainboard/google/zoombini/dsdt.asl +++ b/src/mainboard/google/zoombini/dsdt.asl @@ -34,7 +34,7 @@ #include <soc/intel/cannonlake/acpi/globalnvs.asl> // CPU - #include <soc/intel/cannonlake/acpi/cpu.asl> + #include <soc/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) -- To view, visit https://review.coreboot.org/c/coreboot/+/29755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief3de0c8061fd1a985fecbc355062eb23d046d6d Gerrit-Change-Number: 29755 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Fix IO decode setup
by Duncan Laurie (Code Review) 21 Nov '18

21 Nov '18

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29671 ) Change subject: soc/intel/cannonlake: Fix IO decode setup ...................................................................... soc/intel/cannonlake: Fix IO decode setup This change makes the early IO decode setup mirror that of other Intel SOCs and fixes issues with COM1 not being enabled properly. Tested by successfully successfully receiving serial output from an 8250IO UART device at the standard 0x3f8 base address. Change-Id: I9bd894fea62b78b81e5c80b5e88a539ebddac2df Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/29671 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/pch.c 1 file changed, 29 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Lijian Zhao: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 3ef084a..b06c81b 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -46,6 +46,9 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) + #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC @@ -168,23 +171,38 @@ outw(tcocnt, tcobase + TCO1_CNT); } +static int pch_check_decode_enable(void) +{ + uint32_t dmi_control; + + /* + * This cycle decoding is only allowed to set when + * DMICTL.SRLOCK is 0. + */ + dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + if (dmi_control & PCR_DMI_DMICTL_SRLOCK) + return -1; + return 0; +} + void pch_early_iorange_init(void) { - uint16_t dec_rng, dec_en = 0; + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | + LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; /* IO Decode Range */ - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) && - IS_ENABLED(CONFIG_UART_DEBUG)) { - dec_rng = COMA_RANGE | (COMB_RANGE << 4); - dec_en = COMA_LPC_EN | COMB_LPC_EN; - pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, dec_rng); - pcr_write16(PID_DMI, PCR_DMI_LPCIOD, dec_rng); - } + if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN; - pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en); - pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en); + if (pch_check_decode_enable() == 0) { + io_enables = lpc_enable_fixed_io_ranges(io_enables); + /* + * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same + * value program in LPC PCI offset 82h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + } /* Program generic IO Decode Range */ pch_enable_lpc(); -- To view, visit https://review.coreboot.org/c/coreboot/+/29671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bd894fea62b78b81e5c80b5e88a539ebddac2df Gerrit-Change-Number: 29671 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: cpu/x86/Kconfig.debug: Move more options here
by Julius Werner (Code Review) 21 Nov '18

21 Nov '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29751 ) Change subject: cpu/x86/Kconfig.debug: Move more options here ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/29751/1/src/cpu/x86/Kconfig.debug File src/cpu/x86/Kconfig.debug: https://review.coreboot.org/#/c/29751/1/src/cpu/x86/Kconfig.debug@10 PS1, Line 10: if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 nit: I'm okay with leaving it as it is, but in general this doesn't sound like the right thing to do. In some configurations there are ways to change loglevel at runtime, so we probably shouldn't presume here. -- To view, visit https://review.coreboot.org/c/coreboot/+/29751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bb8e759fc6a4871d30fccff47babfb7a291b45c Gerrit-Change-Number: 29751 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 01:14:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2018