coreboot-gerrit November 2018

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Change in ...coreboot[master]: DO-NOT-SUBMIT: test push
by Ting Shen (Code Review) 21 Nov '18

21 Nov '18

Ting Shen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29766 ) Change subject: DO-NOT-SUBMIT: test push ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d9338ee801cbf28098a633deb9f8e4f79d23918 Gerrit-Change-Number: 29766 Gerrit-PatchSet: 1 Gerrit-Owner: Ting Shen <phoenixshen(a)google.com> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: mb/google/dragonegg: Patch for Audio Enabling
by Subrata Banik (Code Review) 21 Nov '18

21 Nov '18

Subrata Banik has uploaded a new patch set (#7) to the change originally created by Shelley Chen. ( https://review.coreboot.org/c/coreboot/+/29753 ) Change subject: mb/google/dragonegg: Patch for Audio Enabling ...................................................................... mb/google/dragonegg: Patch for Audio Enabling 1. Enable Boot Beep support 2. Enable Audio over Speaker Change-Id: Ia4843185dd79a35476c4f0fc0666ebaf3773db4c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb M src/mainboard/google/dragonegg/variants/baseboard/gpio.c 2 files changed, 40 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/29753/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/29753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4843185dd79a35476c4f0fc0666ebaf3773db4c Gerrit-Change-Number: 29753 Gerrit-PatchSet: 7 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src/soc/intel/braswell/include/soc/irq.h: Set bit 7 of PIRQ register ...
by Frans Hendriks (Code Review) 21 Nov '18

21 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29393 to look at the new patch set (#3). Change subject: src/soc/intel/braswell/include/soc/irq.h: Set bit 7 of PIRQ register to disable ...................................................................... src/soc/intel/braswell/include/soc/irq.h: Set bit 7 of PIRQ register to disable PIRQ register is not set to disabled. Set bit 7 of the PIRQ registers to disable the PIRQ BUG=N/A TEST=Intel CherryHill CRB Change-Id: I18706f12e7c2293e948eb10818393f0d1870f514 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/include/soc/irq.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/29393/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18706f12e7c2293e948eb10818393f0d1870f514 Gerrit-Change-Number: 29393 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src/drivers/intel/fsp1_1/raminit.c: Make check FSP HOBs independent o...
by Frans Hendriks (Code Review) 21 Nov '18

21 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29371 to look at the new patch set (#2). Change subject: src/drivers/intel/fsp1_1/raminit.c: Make check FSP HOBs independent of CONFIG_DISPLAY_HOBS ...................................................................... src/drivers/intel/fsp1_1/raminit.c: Make check FSP HOBs independent of CONFIG_DISPLAY_HOBS Check for FSP HOBS is disabled when CONFIG_DISPLAY_HOBS is disabled. Use the CONFIG_DISPLAY_HOBS for determination of display HOB info only. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/raminit.c 1 file changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/29371/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d Gerrit-Change-Number: 29371 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Disable SD controller and update GPIO
by David Wu (Code Review) 21 Nov '18

21 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29765 to look at the new patch set (#2). Change subject: mb/google/fizz/variants/karma: Disable SD controller and update GPIO ...................................................................... mb/google/fizz/variants/karma: Disable SD controller and update GPIO The SD cardreader is on USB bus, not on SDIO/SDXC. BUG=b:119798840 BRANCH=master TEST=Compiles successfully and boot on DUT. Change-Id: I8015fe35a4ff79469b5781942f588c3e1b88b751 Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/fizz/variants/karma/gpio.c M src/mainboard/google/fizz/variants/karma/overridetree.cb 2 files changed, 24 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/29765/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8015fe35a4ff79469b5781942f588c3e1b88b751 Gerrit-Change-Number: 29765 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Disable SD controller and update GPIO
by David Wu (Code Review) 21 Nov '18

21 Nov '18

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29765 Change subject: mb/google/fizz/variants/karma: Disable SD controller and update GPIO ...................................................................... mb/google/fizz/variants/karma: Disable SD controller and update GPIO The SD cardreader is on USB bus, not on SDIO/SDXC. BUG=b:119798840 BRANCH=master TEST=Compiles successfully and boot on DUT. Change-Id: I8015fe35a4ff79469b5781942f588c3e1b88b751 Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/fizz/variants/karma/gpio.c M src/mainboard/google/fizz/variants/karma/overridetree.cb 2 files changed, 25 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/29765/1 diff --git a/src/mainboard/google/fizz/variants/karma/gpio.c b/src/mainboard/google/fizz/variants/karma/gpio.c index 29c6f88..f811b00 100644 --- a/src/mainboard/google/fizz/variants/karma/gpio.c +++ b/src/mainboard/google/fizz/variants/karma/gpio.c @@ -27,8 +27,7 @@ /* ESPI_IO3 */ /* ESPI_CS# */ /* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ -/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, - EDGE), /* SD_CDZ */ +/* PIRQA# */ PAD_CFG_NC(GPP_A7), /* TP104 */ /* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ /* ESPI_CLK */ /* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ @@ -217,13 +216,13 @@ /* EMMC_CLK */ PAD_CFG_NC(GPP_F22), /* RSVD */ PAD_CFG_NC(GPP_F23), -/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), -/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), -/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), -/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), -/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), -/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */ -/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NC(GPP_G0), +/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), +/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), +/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), +/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), +/* SD_CD# */ PAD_CFG_NC(GPP_G5), +/* SD_CLK */ PAD_CFG_NC(GPP_G6), /* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */ /* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */ diff --git a/src/mainboard/google/fizz/variants/karma/overridetree.cb b/src/mainboard/google/fizz/variants/karma/overridetree.cb index f04def2..32eac4d 100644 --- a/src/mainboard/google/fizz/variants/karma/overridetree.cb +++ b/src/mainboard/google/fizz/variants/karma/overridetree.cb @@ -4,9 +4,14 @@ #+----------------+-------+-----------------------------------+ #| Device | Port# | Rev | #+----------------+-------+-----------------------------------+ + #| SD Card | 4 | | #| Touchsreen | 10 | | #+----------------+-------+-----------------------------------+ + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Card reader register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Touchscreen + + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader + register "psys_pmax" = "151" device domain 0 on @@ -14,10 +19,21 @@ chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi + register "desc" = ""USB2 SD Card"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.3 on end + end + chip drivers/usb/acpi register "desc" = ""USB2 Touchscreen"" register "type" = "UPC_TYPE_INTERNAL" device usb 2.9 on end end + chip drivers/usb/acpi + register "desc" = ""USB3 SD Card"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end + end end end # USB xHCI @@ -45,5 +61,6 @@ device i2c 1a on end end end # I2C #5 + device pci 1e.6 off end # SDCard end end -- To view, visit https://review.coreboot.org/c/coreboot/+/29765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8015fe35a4ff79469b5781942f588c3e1b88b751 Gerrit-Change-Number: 29765 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Configure eSPI IO decode range for EC
by Aamir Bohra (Code Review) 21 Nov '18

21 Nov '18

Hello Subrata Banik, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/29764 to review the following change. Change subject: mb/intel/icelake_rvp: Configure eSPI IO decode range for EC ...................................................................... mb/intel/icelake_rvp: Configure eSPI IO decode range for EC This implementation adds eSPI IO decode range for EC. 1. 0x800-0x8FF / 0x200-020F: EC host command range. 2. 0x900-0x9ff: EC memory map range. Change-Id: I69e6b3a83c072036c5b3ae801f8d80dfda82478e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/29764/1 diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index fb39b60..a57d91a 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -27,6 +27,12 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index b3a7826..f8fbfb4 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -27,6 +27,12 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" register "PchHdaAudioLinkSsp0" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/29764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69e6b3a83c072036c5b3ae801f8d80dfda82478e Gerrit-Change-Number: 29764 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/dragonegg: Add initial mainboard code support
by Subrata Banik (Code Review) 21 Nov '18

21 Nov '18

Subrata Banik has uploaded a new patch set (#6) to the change originally created by Shelley Chen. ( https://review.coreboot.org/c/coreboot/+/29749 ) Change subject: mb/google/dragonegg: Add initial mainboard code support ...................................................................... mb/google/dragonegg: Add initial mainboard code support This patch includes support for both ICL ES0 and ES1 samples. Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/mainboard/google/dragonegg/Kconfig A src/mainboard/google/dragonegg/Kconfig.name A src/mainboard/google/dragonegg/Makefile.inc A src/mainboard/google/dragonegg/acpi_tables.c A src/mainboard/google/dragonegg/board_info.txt A src/mainboard/google/dragonegg/bootblock.c A src/mainboard/google/dragonegg/chromeos.c A src/mainboard/google/dragonegg/chromeos.fmd A src/mainboard/google/dragonegg/dsdt.asl A src/mainboard/google/dragonegg/ec.c A src/mainboard/google/dragonegg/mainboard.c A src/mainboard/google/dragonegg/ramstage.c A src/mainboard/google/dragonegg/romstage.c A src/mainboard/google/dragonegg/smihandler.c A src/mainboard/google/dragonegg/spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex A src/mainboard/google/dragonegg/spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex A src/mainboard/google/dragonegg/spd/Makefile.inc A src/mainboard/google/dragonegg/spd/Micron_MT53E2G32D8QD_8GB.spd.hex A src/mainboard/google/dragonegg/spd/Micron_MT53E512M32D2NP_2GB.spd.hex A src/mainboard/google/dragonegg/spd/empty.spd.hex A src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc A src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb A src/mainboard/google/dragonegg/variants/baseboard/gpio.c A src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h A src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/dragonegg/variants/baseboard/memory.c A src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h A src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h 29 files changed, 1,355 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29749/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/29749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9 Gerrit-Change-Number: 29749 Gerrit-PatchSet: 6 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/icelake: Create macros for FSP consumption as per ICL requi...
by Subrata Banik (Code Review) 21 Nov '18

21 Nov '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29748 ) Change subject: soc/intel/icelake: Create macros for FSP consumption as per ICL requirement ...................................................................... Patch Set 1: Shelley, looks like this is redundant patch as i have ready push it once :) https://review.coreboot.org/#/c/coreboot/+/29697/ -- To view, visit https://review.coreboot.org/c/coreboot/+/29748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I524c7ed116aeb8b353123d7b1d9815b0f249d0e6 Gerrit-Change-Number: 29748 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 02:09:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Enable DPTF
by Duncan Laurie (Code Review) 21 Nov '18

21 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29762 Change subject: mb/google/sarien: Enable DPTF ...................................................................... mb/google/sarien: Enable DPTF Enable DPTF support for sarien/arcada boards. This is currently using placeholder values that are identical that will be updated after thermal tuning is done. Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/sarien/variants/arcada/devicetree.cb A src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl M src/mainboard/google/sarien/variants/sarien/devicetree.cb A src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl 5 files changed, 131 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29762/1 diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 110a214..e544ed6 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -63,4 +63,15 @@ #include <ec/google/wilco/acpi/ec.asl> } #endif + + /* Dynamic Platform Thermal Framework */ + Scope (\_SB) + { + /* Per board variant specific definitions. */ + #include <variant/acpi/dptf.asl> + /* Include soc specific DPTF changes */ + #include <soc/intel/cannonlake/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <soc/intel/common/acpi/dptf/dptf.asl> + } } diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index ee1cca0..4bd2d90 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -30,6 +30,7 @@ register "speed_shift_enable" = "1" register "s0ix_enable" = "1" + register "dptf_enable" = "1" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..2d35878 --- /dev/null +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 100 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Thermal 1" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "Thermal 2" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 80 + +#undef DPTF_ENABLE_FAN_CONTROL +#undef DPTF_ENABLE_CHARGER + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, + + /* CPU Effect on Board */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 44000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b33c923..66f1711 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -30,6 +30,7 @@ register "speed_shift_enable" = "1" register "s0ix_enable" = "1" + register "dptf_enable" = "1" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..2d35878 --- /dev/null +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 100 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Thermal 1" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "Thermal 2" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 80 + +#undef DPTF_ENABLE_FAN_CONTROL +#undef DPTF_ENABLE_CHARGER + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, + + /* CPU Effect on Board */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 44000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) -- To view, visit https://review.coreboot.org/c/coreboot/+/29762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5 Gerrit-Change-Number: 29762 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2018